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Gate Bias Dependence of V TH Degradation in Planar and Trench SiC MOSFETs Under Repetitive Short Circuit Tests.
- Source :
-
IEEE Transactions on Electron Devices . May2022, Vol. 69 Issue 5, p2521-2527. 7p. - Publication Year :
- 2022
-
Abstract
- The reliability of SiC MOSFETs under harsh operating conditions, such as short circuit (SC) stress, remains a major concern. In this article, a dedicated aging platform is developed to study the degradation of SiC planar- and trench-gate MOSFETs under repetitive SC conditions. The static characteristics of the devices are monitored in real-time during the test. Depending on the gate bias used in the experiments, a bidirectional ${V}_{\text {TH}}$ shift in both types of devices is observed, yet with a different degradation rate. The underlying degradation mechanisms investigated by device simulation reveal that the damaged region in the SiC planar-gate MOSFET is located near the channel area, while at the trench corner in the SiC trench-gate MOSFET. These research outcomes enable better understanding of the degradation mechanisms of different SiC MOSFET structures and possible ruggedness improvements in the future. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 69
- Issue :
- 5
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 157582590
- Full Text :
- https://doi.org/10.1109/TED.2022.3142237