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This paper presents a detailed investigation of the quasi-static capacitance-voltage (QSCV) technique in pseudo-metal-oxide-semiconductor field effect transistor (pseudo-MOSFET) configuration for evaluating the interface quality of bare silicon-on-insulator (SOI) wafers, without processing dedicated metal-oxide-semiconductor (MOS) test devices. A physical model is developed that is capable of explaining the experimental results. In addition, frequency effects are used to validate the equations by a systematic comparison between experimental and calculated characteristics, as well as by a direct comparison with the standard high-low frequency approach. An extraction procedure for interface trap density based solely on QSCV experimental results is proposed, and limits of the procedure are discussed. The proposed experimental and analytical procedure is demonstrated by characterizing SOI structures with different geometries and with different qualities of surface passivation of the top silicon film. [ABSTRACT FROM AUTHOR]

One of the main issues in the characterization of silicon on insulator (SOI) substrates is to determine the quality of the film-buried oxide interface. This interface quality is strongly connected to the carrier lifetime in the silicon film. In this paper, we extend the well-known pseudo-MOSFET characterization technique for SOI wafers to the extraction of carrier lifetime. The experiment consists in comparing the drain current measured under dark and under laser shining. A model is proposed to evaluate the surface recombination velocity in SOI. Experimental results are validated by numerical simulations. [ABSTRACT FROM AUTHOR]

The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5–10 nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond V D > 1.0 V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations. [ABSTRACT FROM AUTHOR]

We extend the pseudo-metal-oxide-semiconductor field-effect transistor (Ψ-MOSFET) technique to the low-temperature range in order to investigate the transport properties of as-fabricated silicon-on-insulator (SOI) wafers. This paper shows experimental results on the temperature dependence of drain current and extracted parameters (hole and electron mobility, subthreshold slope, and threshold voltage). In ultrathin SOI films, the coupling between channel and free surface is strong, degrading the subthreshold swing and threshold voltage. The impact of interface trap density is significant at low temperature. The good correlation between experimental and theoretical curves proves the feasibility of Ψ-MOSFET measurements on bare silicon-on-insulator wafers at low-temperature. [ABSTRACT FROM AUTHOR]

In order to improve device performance, recent trends in microelectronics are to explore nanowire gate-all-around structures and alternative channel materials with superior properties. In this paper, we investigate the electrical transport properties, at room and low temperature, in as-grown three-dimensional (3D) vertically stacked germanium (Ge)-enriched nanowires. Measurements using the Pseudo-MOSFET (ψ-MOSFET) concept show that the transport in gateless nanowires is controlled by the voltage applied on the substrate, as in a MOS transistor. Interestingly, the substrate bias effect depends on the designed geometry of the nanowire. In nanowires with high width/length aspect ratio, we show the possibility of turning on both electron and hole channels. For nanowires with small width/length ratio, only the hole channel is visible. The impact of series resistance on the drain current level is reported. Transport modification with the concentration of germanium in the nanostructures is also discussed. Low-temperature measurements show the variation of electrical parameters such as threshold voltage, flatband voltage, subthreshold swing and mobility. The transport properties in multi-parallel stacked nanowire are addressed. [ABSTRACT FROM AUTHOR]

SOI technology offers ample room for scaling, performance improvement, and innovations. The current status is reviewed by focusing on several technological options for boosting the transport properties in SOI MOSFETs. The impact of series resistance, high-K dielectrics, and metal gate in advanced transistors is discussed. Carrier mobility measurements as a function of channel length and temperature reveal the beneficial effect of strain, mitigated however by various types of defects. The experimental data is exclusively collected from state-of-the-art, ultrathin body, fully depleted MOSFETs. Simple models are presented to clarify the mobility behavior. [ABSTRACT FROM AUTHOR]

• Double gate structures for channel material and gate stack characterization. • Easy and simple techniques based on the pseudo-MSOFET configuration. • Fast fabrication loop of double gate MOSFET. • Test structures for parameter extraction. • Double-gate pseudo-MOSFET for rapid material characterization. Pseudo-MOSFET delivers a fast, simple and reliable way of characterizing electrically SOI substrates without the need of full CMOS fabrication. However, the information refers to the back interface. Here, to probe the front interface, we extend the concept to a double-gate pseudo-MOSFET. The structure provides a pertinent test vehicle for the characterization and development of transistors channel and gate stack materials in a configuration similar to fully fabricated transistors. We show that the devices with undoped terminals need specialized modeling development to describe the double gate effect. Devices with doped terminals are immediately exploitable for parameter extraction. [ABSTRACT FROM AUTHOR]

Abstract: Low-frequency noise (LFN) is generated by interactions of the channel carriers with interface traps and oxide charges. Therefore, noise measurements on silicon on insulator (SOI) wafers can give important information about the state of the interfaces and their defect density. Here, noise measurements at wafer level were performed using the pseudo-MOSFET (Ψ-MOSFET) configuration. 1/f noise behavior in relatively thick and ultra-thin SOI layers is obtained. No probe pressure dependence of the noise is observed. The influence of wafer surface states is showed and further confirmed in passivated SOI samples. Origins of noise generation are discussed. [Copyright &y& Elsevier]

Pseudo-metal-oxide-semiconductor field-effect transistor (Ψ-MOSFET) is a simple and efficient technique for characterizing electrical properties of silicon-on-insulator wafers. The primary condition for reliable parameter extraction is to achieve ohmic contacts between Ψ-MOSFET probes and silicon film. This paper brings experimental arguments on the probe-pressure impact on contact nature, series resistance, and carrier mobility. The specificity of our study consists of the topographical analysis (by atomic force microscopy) of craters induced by the probes. We correlate the probe-pressure with morphology parameters (size of craters) and electrical parameters (series resistance, mobility). For higher pressures, contacts are improved, changing from Schottky-like to ohmic-like. [ABSTRACT FROM AUTHOR]

Back-gated InGaAs-on-insulator lateral N + NN + MOSFETs are successfully fabricated by direct wafer bonding and selective epitaxial regrowth. These devices were characterized using a revisited pseudo-MOSFET configuration. Two different transport mechanisms are evidenced: volume conduction in the undepleted region of the film and surface conduction at the interface between InGaAs and buried insulator. We propose extraction techniques for the volume mobility and interface mobility. The impact of film thickness, channel width, and length is evaluated. Additional measurements reveal the variation of the transistor parameters at low temperature and under externally applied uniaxial tensile strain. [ABSTRACT FROM AUTHOR]

Abstract: The pseudo-MOSFET (Ψ-MOSFET) method is extended for the electrical characterization of heavily doped (1019–1020 cm−3) SOI wafers with 10–40nm film thickness. The field-effect modulation is small and does not enable the formation of an inversion channel. Only accumulation and depletion-controlled volume conduction modes are activated by increasing the back-gate voltage to 40V. An updated model describing the conduction regimes for heavily doped SOI wafers is derived. This model provides a simple method for parameters extraction such as surface and volume mobility and doping level. Four-point probe and Hall effect measurements fully validate our Ψ-MOSFET results. It is found that high-dose implantation results in good redistribution and electrical activation of impurities, without affecting the quality of the buried oxide and Si–SiO2 interface. [Copyright &y& Elsevier]

The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture and fabrication flow, and using undoped source and drain terminals, the device allows for a fast electrical evaluation of semiconductor films on insulators (SOI) and gate stacks. This paper describes an electrical model that reproduces the peculiar transfer characteristics of a junctionless EZ-FET. The model is then simplified to develop a pragmatic parameter extraction methodology. This methodology is experimentally validated and provides the electrical properties of SOI films (mobility, threshold voltage) for both electrons and holes. [ABSTRACT FROM AUTHOR]

This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified. [ABSTRACT FROM AUTHOR]

• An EZFET is a simple and reliable characterization device for substrates and gate stacks. • Junctionless EZFET removes the temperature limitation of junctions activation for low temperature integration applications. • A complete model reproduces the peculiar device behavior. • A simplified parameters extraction methodology provides reliable substrate and gate stack evaluation. • The junctionless EZFET can be used for two-dimensional that cannot be doped. The junctionless EZ-FET is a device with simplified architecture and processing. With only two lithography levels and using regular process steps, it enables fast electrical characterization of semiconductor films on insulators (SOI) with undoped source and drain. An electrical model reproducing the peculiar transfer characteristics of a junctionless EZ-FET is presented in this work. Based on this model, a simplified parameter extraction methodology is proposed and used to access the electrical properties of SOI structures (i.e. threshold voltage, mobility). [ABSTRACT FROM AUTHOR]

Abstract: We demonstrate for the first time the feasibility of split C–V measurements on as-fabricated SOI wafers using pseudo-MOSFET configuration. An adapted methodology to determine the effective mobility of electrons and holes by split C–V technique is proposed and validated through comparison with the effective mobility extracted from static measurements. The method has been applied to different SOI materials (thin and thick film/BOX, passivated and non-passivated surface). The frequency and substrate depletion effects and the role of probe pressure and spacing are discussed. The electron mobility can exceed 500cm2 V−1 s−1 in thin SOI films with passivated surface. [Copyright &y& Elsevier]