Interface trap density evaluation on bare silicon-on-insulator wafers using the quasi-static capacitance technique.

This paper presents a detailed investigation of the quasi-static capacitance-voltage (QSCV) technique in pseudo-metal-oxide-semiconductor field effect transistor (pseudo-MOSFET) configuration for evaluating the interface quality of bare silicon-on-insulator (SOI) wafers, without processing dedicated metal-oxide-semiconductor (MOS) test devices. A physical model is developed that is capable of explaining the experimental results. In addition, frequency effects are used to validate the equations by a systematic comparison between experimental and calculated characteristics, as well as by a direct comparison with the standard high-low frequency approach. An extraction procedure for interface trap density based solely on QSCV experimental results is proposed, and limits of the procedure are discussed. The proposed experimental and analytical procedure is demonstrated by characterizing SOI structures with different geometries and with different qualities of surface passivation of the top silicon film. [ABSTRACT FROM AUTHOR]