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We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from $1.6 \times 10^{18}$ cm−3 to $4.8 \times 10^{19}$ cm−3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGaAs conduction band is experimentally manifested. It is also revealed that the contact resistivity ( $\rho _{\text {c}}$ ) of Mo/n-InGaAs contact clearly outperforms after annealing. However, for the first time, we demonstrate that the Mo/Pd (2nm)/n-InGaAs contact can achieve a $\rho _{\text {c}}~35$ % and 20% lower than a single Mo/n-InGaAs contact after annealing at 400 °C and 450 °C for 1min, respectively.

Large-area epitaxy of layered materials is one of the cornerstones for a successfulexploitation of van der Waals (vdW) materials in the semiconductorindustry. The formation of 60° twin stacking faults and 60° grain boundariesis of major concern for the defect-free epitaxial growth. Although strategiesto overcome the occurrence of these defects are being considered, morefundamental understanding on the origin of these defects is highly essential.This work focuses on understanding the formation of 60° twins in (quasi-)vdW epitaxy of 2D chalcogenides. Molecular beam epitaxy (MBE) experimentsreveal the striking difference in 60° twin occurrence between WSe2and Bi2Se3 in both quasi-vdW heteroepitaxy and vdW homoepitaxy. Densityfunctional theory (DFT) calculations link this difference to the interlayer vdWcoupling strength at the unit cell level. The stronger interlayer vdW coupling in Bi2Se3 unit cells compared to WSe2 unit cells is explained to resultin a reduced twin occurrence. Hence, such compounds show significantlymore promise for defect-free epitaxial integration. This interesting aspectof (quasi-)vdW epitaxy reveals that the strength of interlayer vdW couplingis key for workable 2D materials and opens perspectives for other stronglycoupled vdW materials.

Layered materials held together by weak van der Waals (vdW) interactions are a promising class of materials in the field of nanotechnology. Besides the potential for single layers, stacking of various vdW layers becomes even more promising since unique properties can hence be precisely engineered. The synthesis of stacked vdW layers, however, remains to date, hardly understood. Therefore, in this work, the vdW epitaxy of transition metal dichalcogenides (TMDs) on single-crystalline TMD templates is investigated in depth. It is demonstrated that the role of lattice mismatch is insignificant. More importantly is the role of surface energy, calculated using density functional theory, which plays an essential role in the activation energy for adatom diffusion, hence nucleation density. This in turn correlates with defect density since the stacking sequence in vdW epitaxy is generally poorly controlled. Moreover, the vapor pressure of the transition metal is also found to correlate with adatom diffusion. Consequently, the proposed study enables important and new insight in the vdW epitaxy of multilayer 2D homo-/heterostructures. ispartof: ACS APPLIED MATERIALS & INTERFACES vol:12 issue:24 pages:27508-27517 ispartof: location:United States status: published

Barium titanate (BaTiO3 or BTO) is a perovskite structure material with interesting intrinsic properties, such as spontaneous ferroelectricity or electro-optical behavior, which strongly depend on thin film crystallinity. For such functional oxide systems, the pulsed-laser deposition (PLD) approach is one promising growth technique due to its precise stoichiometry control of the metals composing the perovskite crystal and higher oxygen environment compared to the classically used molecular beam epitaxy (MBE) approach. In this article, we demonstrate a BTO epitaxial layer by PLD onto an Si(001) substrate thanks to a thin pseudomorphic SrTiO3 buffer layer grown by MBE. In our study, the various investigated PLD parameters show strong impacts on the BTO polarization orientation. Hence, adjusting the growth conditions allows control of the polarization orientation, which is crucial for both electronic and optical applications. In addition, lattice parameter changes of BTO layers are investigated using x-ray diffraction and cross-sectional transmission electron microscopy, which evidenced a correlation between mismatch relaxation and oxygen growth pressure. Finally, with the analysis of BTO C– V curves, the polarization direction transition is demonstrated electrically. ispartof: Journal Of Applied Physics vol:128 issue:10 pages:104104-104104 status: published

© 2018 Elsevier B.V. Quantum Dots (QDs) are considered as an efficient building block of many optoelectronic applications, such as semiconductor laser, photodetector, whereby their physical dimension is the key parameter to be controlled. In this work, we have studied experimentally the growth of InAs QDs on InP(0 0 1) substrate by MOVPE and established a theoretical model explaining the observed epitaxial behaviour. In variance with the classical Stranski-Krastanov growth, we show that during the growth there is an intermediate stage whereby although first large 3D islands are formed, an increased density of small QDs is formed concurrent with the shrinkage of the large 3D islands. As a result, the growth can be divided into three regimes: 2D layer growth, large 3D islands growth and QDs growth. To explain this evolution, a thermodynamic model has been developed accounting for the process driven by surface energy, elastic relaxation energy and inter-island interaction energy. It will be shown that the balance between the surface energy and the elastic relaxation energy provides the transition from 2D layer to large 3D islands (around at 3 ML of InAs growth). This model also supports the energetically favourable truncated pyramidal shape for large 3D islands and the spherical cap shape for QDs. We show in this paper that a balance between surface energy, elastic relaxation energy and inter-island elastic interaction explains the volume shrinkage of the early large 3D islands towards the formation of small QDs in high density. ispartof: JOURNAL OF CRYSTAL GROWTH vol:509 pages:133-140 status: published

The three-dimensional carrier confinement in Quantum Dots (QDs) is the key to achieve superior properties (electronic and optical) compared to the Quantum Well (QWL) for optoelectronic applications, such as semiconductor lasers, photodiodes. After the growth of QDs, the encapsulation is the next crucial step to confine carriers in QDs and achieve the targeted wavelength emission. In this work, we have studied the InP capping of Stranski-Krastanov (S-K) grown InAs QDs on InP(0 0 1) substrate by MOVPE. During the encapsulation, the P/As exchange is a vital process which either transforms the QDs into a 2D layer or reduces QDs’ dimensions. This study shows that a control of Phosphorous concentration on the surface during InP capping facilitates to obtain the expected QDs dimension for 1550 nm wavelength. The emitted photoluminescence peak shifts following the preserved average QDs’ dimensions. By combining simulation with optical response we have proved the Phosphorous incorporation into the InAs structure (QDs or 2D layer) during the encapsulation step. As expected, the carrier lifetime reveals the superior quality of the preserved QDs in InP barrier compared to the 2D layer. Finally, the reduction of the non-radiative recombination sources, e.g. dangling bonds, by passivation treatment demonstrates a further increment in carrier lifetime.

Two-dimensional transition metal dichalcogenide (TMD) semiconductors have risen as an important material class for novel nanoelectronic applications. Molybdenum disulfide (MoS2) is the most representative TMD compound due to its superior stability and attractive properties for (opto-) electronic devices. However, the synthesis of single-crystalline and functional MoS2 across large-area substrates remains crucial for its successful integration in semiconductor industry platforms. Therefore, this work focuses on the study of MoS2 epitaxy via two well-established industry-compatible synthesis methods, promising for the large-area and single-crystalline integration of van der Waals (vdW) materials. These methods are molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE) and have studied MoS2 quasi-vdW heteroepitaxy on reconstructed sapphire substrates and MoS2 vdW homoepitaxy on exfoliated MoS2 flakes. By examining the MoS2 structural properties using diffraction and spectroscopy techniques, the epitaxial relation and crystal quality are assessed, which reveals insights into the prevalence of inter- and intragrain defects such as grain boundaries and sulfur vacancies. The MBE method yields superior epitaxial MoS2 registry on both sapphire and MoS2 surfaces as compared to MOVPE, although inferior defectivity arises from the typical lower MBE growth temperature and chalcogen partial pressure. Moreover, both synthesis methods generate high densities of twinned MoS2 grain boundaries, which hamper defect-free integration. As a result, this challenging integration might become an important bottleneck for industrial TMD-based applications with a low tolerance for material defects.

ispartof: 2D MATERIALS vol:7 issue:2 status: published

Stranski-Krastanow (S-K) grown self-assembled quantum dots (QDs) are considered as an efficient active layer for many optoelectronic applications, such as semiconductor laser, photodetector, due to the possibility to confine carriers in three dimensions. Towards the device application, the subsequent growth of an encapsulation layer is a key step to obtain the desired QDs-based heterostructures. In this work, we have studied step-by-step the encapsulation process of S-K grown InAs QDs/InP(0 0 1) by InAlGaAs (lattice matched to InP) in MOVPE. A detailed investigation with Electron Channeling Contrast Imaging (ECCI) and cross-sectional Transmission Electron Microscopy (TEM), indicated that after the InAlGaAs capping the partially relaxed, dome shaped InAs QDs are transformed into fully biaxially strained, truncated pyramids however without introducing any defects in the heterostructure. The study also presents the important role of the capping layer thickness on the QDs photoluminescence efficiency. The gradual change of the surface morphology during the encapsulation process, has been investigated step-by-step in-depth by atomic force microscopy. The morphological changes can be explained by a capping model based on the localized growth rates. We show that two growth steps of Non-uniform capping, where growth rates are different from each other, result in the successful planarization of the InAlGaAs capping without forming any defect.

© 2018 Author(s). We study in this work the growth and fabrication of top-down highly doped n + InAs(Si)/p + GaSb(Si) Esaki tunneling diodes on (001) GaAs substrates. A careful investigation on the highly mismatched GaSb/GaAs growth is first conducted by means of Reflection High-Energy Electron Diffraction (RHEED), Atomic Force Microscopy (AFM), and X-Ray Diffraction (XRD) analyses. These results are expected to pave the way to methods for III-Sb buffer layer's integration with low threading dislocation (TD) densities. A comparison between AFM, XRD, defect revealing by chemical etching and transmission electron microscopy (TEM) is then presented to calculate the precise TD density and its influence on the device structure. In the last part, we report on first operating sub-30 nm III-V vertical NW tunneling devices on (001) commercial GaAs substrates. ispartof: JOURNAL OF APPLIED PHYSICS vol:124 issue:19 status: published

In this paper we review the details and results of the replacement fin process technique used to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300 mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the performance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with L G = 60 nm have a peak transconductance of 1030 μS/μm with a SS SAT of 125 mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high- k interface. Nanowires with a diameter of 6 nm were demonstrated to show quantization induced immunity to D it resulting in a SS SAT as low as 66 mV/dec for 85 nm L G devices.

aalso at E.E. Dept. KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium Since the 45 nm CMOS node, high-k gate dielectrics and strain engineering go hand in hand to further boost the transistor performance. An example of a so-called global strain platform relies on a thin strained-silicon (sSi) layer on top of a strain-relaxed Si1-xGex buffer (SRB) (Fig. 1). In addition, replacing thermally grown SiO2 by a deposited dielectric opens the door for the implementation of so-called high-mobility channel materials (Ge – pMOS; InxGa1-xAs – nMOS;...), which can be grown hetero-epitaxially on a silicon substrate. Due to the lattice mismatch of most of these materials with silicon, strain relaxation will occur above a certain critical thickness, leading to the introduction of both misfit and threading dislocations (TDs). It is well-known that dislocations introduce a one-dimensional band of states in the band-gap and hence are electrically active [1],[2]. The aim of the present review is to address the impact of such extended defects on the electrical performance of simple devices (p-n junctions, MOSFETs,...) for various high-mobility materials. A first example which will be discussed is the impact of TDs on the current-voltage (I-V) characteristics of p-n junctions fabricated in sSi and relaxed-Ge-on-Si substrates. As can be derived from Fig. 1, the depletion region mainly extends in the SiGe SRB, so that the electrical activity of the dislocations in this layer will be probed. It is clear from Fig. 2 that the reverse current IR of the diodes more or less proportionally increases with the density of TDs [3]. The same applies for the recombination and generation lifetime. Similar studies have been carried out for p-n junctions fabricated in a Si0.2Ge0.8 SRB and in relaxed Ge-on-Si epi layers. Summarizing all these results in Fig. 3, one can observe that the area leakage current density increases proportionally with the density of TDs and exponentially with the Ge content [4]. The latter can be explained by considering the impact on the band gap, yielding an exponential increase of the intrinsic carrier density. Comparing with Fig. 3b, it is clear that there exists a trade-off between leakage current density and epi layer thickness: thinner relaxed Ge layers on silicon will have a higher equilibrium TD density [5] and, hence, leakage current. However, considering a typical SRAM cell design, it can be concluded that for typical TDD values of 107-108 cm-2, the contribution to the off-state leakage is negligible compared with the contribution of the perimeter. A second example investigates the impact of anti-phase boundaries (APBs) on the reverse current of p-n junctions fabricated in GaAs (Fig. 4a) will be discussed. As can be derived from Fig. 4b, there is a modest increase of IRbetween on-axis junctions with a high APB density and off-axis diodes. Overall, it has been concluded that APBs are not so efficient leakage generators in GaAs. Finally, the impact of TDs on other device parameters, like the mobility or the threshold voltage of a MOSFET will be discussed. References [1] W. Schröter and H. Cerva, Solid State Phenomen., 85-86, p. 67 (2002). [2] E. Simoen et al., J. Electrochem. Soc., 158, p. R27 (2011). [3] G. Eneman et al., Appl. Phys. Lett., 87, p. 192112 (2005). [4] E. Simoen et al., J. Electrochem. Soc., 157, p. R1 (2010). [5] G. Wang et al., Appl. Phys. Lett., 94, p. 102115-1 (2009). Figure 1

We study in this paper the epitaxial growth and electrical characterization of an n+In 0.5 Ga 0.5 As/p+GaAs 0.5 Sb 0.5 Esaki diode lattice matched to (001)-oriented InP substrate. First, the effects of molecular beam epitaxy growth temperature and group-V growth rates on the GaAs x Sb 1− x composition are characterized by means of X-ray diffraction (XRD). It is found that GaAs x Sb 1− x lattice constant is mainly determined by the Sb 4 incorporation rather than the As 4 one. After optimization, high quality In 0.54 Ga 0.46 As(Si)/GaAs 0.52 Sb 0.48 (Be) heterostructure is confirmed by XRD, Transmission electron microscope (TEM) and Secondary Ion Mass Spectroscopy (SIMS) profiles meeting requirements for sub-60 mV/dec operating devices. Esaki tunnel diodes are then fabricated to be used as a prediction of Band-To-Band Tunneling (BTBT) for Tunnel Field-Effect transistors (TFETs). The results are compared to previously reported n+/p+In 0.5 Ga 0.5 As homojunction diodes, showing a ×60 factor improvement of BTBT current density for the same electric field with an excellent average Peak-to-Valley Current Ratio (PVCR) of 14.

The ongoing study of {111} planar defects (PDs) in III–V nanowires (NWs) entails a fast and quantitative characterization method beyond transmission electron microscopy (TEM). We report here a simple and reliable method to calculate the PD frequency in InAs NWs using a lab X-ray diffractometer. The fact that the PD distribution is location independent and irrelevant to the NWs diameter in catalyst-free InAs NWs epitaxy makes PD frequency global calculation possible. We demonstrated that the PDs follow a geometric distribution in NWs. As a consequence, applying a 1D disordered layers diffraction model, we relate the diffraction peak angle directly to the PD frequency. The calculated PD frequency values are in good agreement with that extracted from high resolution TEM analysis. As an example, we applied this method to study the influence of growth temperature on PD frequencies in the frame of a 2D nucleation model.

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. Monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy. We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of III-V selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on (001) oriented Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is original and obviously confirm the potential of this heterogeneous integration option for high mobility logic devices, and photonic applications on a common Si platform.

Extracting plasmon-induced hot carriers over a metal-semiconductor Schottky barrier enables photodetection below the semiconductor bandgap energy. However, interfacial carrier recombination hinders the efficiency and stability of this process, severely limiting its implementation in telecommunication. This study proposes and demonstrates the use of epitaxially grown lattice-matched SrTiO3 for interfacial passivation of silicon-based plasmonic Schottky devices. The devices are activated by an electrical soft-breakdown of the interfacial SrTiO3 layer, resulting in reproducible rectified Schottky characteristics. The transition to a low resistance state of the SrTiO3 layer boosts the extraction efficiency of hot holes upon resonant plasmonic excitation, giving rise to a two orders of magnitude higher photocurrent compared to devices with a native oxide layer. Photoresponse, tunability, and barrier height studies under reverse biases as high as 100 V present superior stability with the incorporation of the SrTiO3 layer. The investigation paves the way toward plasmon-induced photodetection for practical applications including those under challenging operating conditions.

This chapter deals with the monolithic integration of InGaAs semiconductor on (001)-oriented Si substrate. This starts with a brief introduction to III-V semiconductor epitaxy, the effect of strain, and the relaxation mechanisms. An overview of the different structural defects' families is also included in the section. In a second part, the two most popular III-V growth techniques that are molecular beam epitaxy and metal-organic vapor phase epitaxy are compared. The main challenge in the heterogeneous integration of InGaAs on Si resides in the material mismatch between both semiconductors that results in the high-density generation of crystalline defects. In this chapter, several options such as strain-relaxed buffers, wafer bonding, epitaxial lateral growth, and selective area growth have been considered to reduce the defect density in III-V compounds on Si, which will be reviewed. Finally, a rich literature completes the chapter.

In this work, we report on the growth of pseudomorphic and highly doped InAs(Si)/GaSb(Si) heterostructures on p-type (0 0 1)-oriented GaSb substrate and the fabrication and characterization of n+/p+ Esaki tunneling diodes. We particularly study the influence of the Molecular Beam Epitaxy shutter sequences on the structural and electrical characteristics of InAs(Si)/GaSb(Si) Esaki diodes structures. We use real time Reflection High Electron Diffraction analysis to monitor different interface stoichiometry at the tunneling interface. With Atomic Force Microscopy, X-ray diffraction and Transmission Electron Microscopy analyses, we demonstrate that an “InSb-like” interface leads to a sharp and defect-free interface exhibiting high quality InAs(Si) crystal growth contrary to the “GaAs-like” one. We then prove by means of Secondary Ion Mass Spectroscopy profiles that Si-diffusion at the interface allows the growth of highly Si-doped InAs/GaSb diodes without any III-V material deterioration. Finally, simulations are conducted to explain our electrical results where a high Band to Band Tunneling (BTBT) peak current density of Jp = 8 mA/μm2 is achieved.

Themechanism of widely observed intermixing of wurtzite and zinc-blende crystal structures in InAs nanowire (NW) grown by selective area epitaxy (SAE) is studied. We demonstrate that the crystal structure in InAs NW grown by SAE can be controlled using basic growth parameters, and wurtzitelike InAs NWs are achieved.We link the polytypic InAs NWs SAE to the reconstruction of the growth front (111)B surface. Surface reconstruction study of InAs (111) substrate and the following homoepitaxy experiment suggest that (111) planar defect nucleation is related to the (1 × 1) reconstruction of InAs (111)B surface. In order to reveal it more clearly, a model is presented to correlate growth temperature and arsenic partial pressure with InAs NW crystal structure. This model considers the transition between (1 × 1) and (2 × 2) surface reconstructions in the frame of adatom atoms adsorption/desorption, and the polytypism is thus linked to reconstruction quantitatively. The experimental data fit well with the model, which highly suggests that surface reconstruction plays an important role in the polytypism phenomenon in InAs NWs SAE.https://doi.org/10.1103/PhysRevMaterials.1.074603

In this presentation we will report on our recent work on new materials that can be monolithically integrated on high-index contrast silicon or silicon nitride photonic ICs to enhance their functionality. This includes graphene and other 2D-materials for realizing compact electro-absorption modulators and non-linear devices, ferroelectric materials for realizing phase modulators and adiabatic couplers for realizing bistable switches.

The low-frequency noise is studied in planar InGaAs channel nMOSFETs, with Al2O3 gate dielectric in combination with different pre- and post-gate treatments, namely, pre-gate TMA exposure or post-gate Forming Gas Annealing (FGA). It is shown that the oxide trap density is reasonably uniform in the gate stack between 1 and 2 nm from the interface, whereby a FGA yields a lower noise power spectral density compared with the TMA or untreated devices.

The relationship between the Threading Dislocation Density (TDD), the generation (τg) and recombination lifetime (τr) in relaxed n-type In.53Ga.47As is investigated for a series of p+n junction diodes, containing an TDD ranging from 105 to 1010 cm-2. The TDs are generated intentionally by lattice-misfit growth on Semi-Insulating (SI) InP and GaAs substrates. The lifetimes have been extracted from diode Current-Voltage (I-V) and Photoluminescence (PL) analysis showing that TDDs affect their values above a density of about 1×107 cm-2 (τg,E~0) and about 1×108 cm-2 (τr and τPL), which can be well-explained by the charged dislocation cylinder model. In addition, a detailed comparison between the results from Deep Level Transient Spectroscopy (DLTS) and from the diode characterization is performed, showing that the responsible G/R center shifts toward mid-gap in In.53Ga.47As and transfers from a native point defect (PD1) to a TD (E2/H1). Finally, the classical concept of generation lifetime and recombination lifetime in terms of dislocations is discussed based on the results.

The increasing scientific and industry interest in 2D MX2 materials within the field of nanotechnology has made the single crystalline integration of large area van der Waals (vdW) layers on commercial substrates an important topic. The c-plane oriented (3D crystal) sapphire surface is believed to be an interesting substrate candidate for this challenging 2D/3D integration. Despite the many attempts that have been made, the yet incomplete understanding of vdW epitaxy still results in synthetic material that shows a crystallinity far too low compared to natural crystals that can be exfoliated onto commercial substrates. Thanks to its atomic control and in situ analysis possibilities, molecular beam epitaxy (MBE) offers a potential solution and an appropriate method to enable a more in-depth understanding of this peculiar 2D/3D hetero-epitaxy. Here, we report on how various sapphire surface reconstructions, that are obtained by thermal annealing of the as-received substrates, influence the vdW epitaxy of the MBE-grown WSe2 monolayers (MLs). The surface chemistry and the interatomic arrangement of the reconstructed sapphire surfaces are shown to control the preferential in-plane epitaxial alignment of the stoichiometric WSe2 crystals. In addition, it is demonstrated that the reconstructions also affect the in-plane lattice parameter and thus the in-plane strain of the 2D vdW-bonded MLs. Hence, the results obtained in this work shine more light on the peculiar concept of vdW epitaxy, especially relevant for 2D materials integration on large-scale 3D crystal commercial substrates.

The observation and interpretation of Frank stacking faults, Shockley stacking faults, Lomer dislocations, and 60 degrees misfit dislocations, which have similar line shapes in the (001) In0.53Ga0.47As crystalline surface, are performed with the electron channeling contrast imaging (ECCI) technique. To minimize the backscattered electron (BSE) contrast that resulted from the surface morphology, a relatively flat region is first selected and compared with an atomic force microscopy (AFM) image and then, subsequently, examining ECCI with transmission electron microscopy (TEM)-like invisibility criteria. By orthogonally choosing the diffraction vector g between (220) and (2-20), misfit dislocations seem to be always visible but partially faint in the g parallel to the line direction on the surface. With respect to the image contrast, Frank stacking faults and Lomer dislocations are likely to be completely invisible for parallel g. The criteria are further confirmed by cross-sectional TEM analysis, which shows a preferred homogeneous surface nucleation.

In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques.In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques.

On-chip optical interconnects still miss a high-performance laser monolithically integrated on silicon. Here, we demonstrate a silicon-integrated InP nanolaser that operates at room temperature with a low threshold of 1.69 pJ and a large spontaneous emission factor of 0.04. An epitaxial scheme to grow relatively thick InP nanowires on (001) silicon is developed. The zincblende/wurtzite crystal phase polytypism and the formed type II heterostructures are found to promote lasing over a wide wavelength range.

Deep levels associated with extended and point defects in MOS capacitors fabricated on unintentionally doped GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep Level Transient Spectroscopy (DLTS). A 9nm layer of Al2O3 is deposited as high-k gate dielectric by Molecular Beam Epitaxy. The trap kinetics and origin of defect states is discussed. Also, it is shown that the dislocation cores in relaxed p-Ge are associated with band-like donor-like states in the lower half of forbidden band gap, and act as carrier trapping and recombination centers. In addition, slow and fast oxide interface traps are observed.

As post-Si era for digital device is incipient, In0.53Ga0.47As is good candidate among n-type active channels with high electron mobility but - unlike Si - it lacks a well-established technology for dielectric gating which may bear aggressive device scaling. Here we propose a viable route for the atomic layer deposition (ALD) of high-κ dielectrics taking advantage from the well-known self-cleaning effect of the trimethylaluminum (TMA) precursor on the III-V compound surfaces. In this respect, the incorporation of Al2O3 cycles both as pre-conditioning surface treatment and inside the ALD growth of a MO2 host matrix (M=Zr, Hf) is here investigated. Al:MO2/In0.53Ga0.47As heterojunctions have been scrutinized by in situ spectroscopic ellipsometry and ex situ chemical depth-profiling analysis which validate a good physical quality of the oxide and elucidate the effect of the pre-conditioning cycles at the interface level. The resulting MOS capacitors have been characterized by means of multifrequency capacitance-voltage measurements and conductance analysis therein yielding a permittivity of 19{plus minus}1 both for Al:HfO2 and Al:ZrO2 and similar electrical quality of the interfaces. On the other hand, Al:HfO2 appears to be electrically more robust against leakage and endowed with a lower frequency dispersion in accumulation.

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

Deep levels present in MOS capacitors, fabricated on GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). The gate dielectric is composed of 9 nm Al2O3 deposited by Molecular Beam Epitaxy (MBE) on two different types of Interfacial Oxide Layers (IOL). It is shown that the density of interface traps (Dit) near the valence band edge is significantly reduced for GeSn epilayers compared with the same gate stack on a Ge cap. At the same time, several deep-level traps in the germanium depletion region have been observed, whereof the origin is discussed.

To design a high performance BaTiO3 (BTO)-integrated Si modulator, understanding how BTO domain orientations influence its electro-optical (EO) properties is crucial. The 100-nm-thick BTO films with c-oriented and a-oriented domains are obtained by exploiting various thickness of SrTiO3 buffer layers grown on Si(001) substrates. Then, the electro-optical behavior for 2 differently oriented samples is analyzed using spectroscopic ellipsometry.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

In this work, we will review the advantages and challenges of vertical devices which are seen as possible candidates to continue CMOS scaling. Different integration schemes will be discussed, also addressing the use of novel channel materials like III-V that could benefit from a vertical architecture to relax both gate length and wire diameter. Next to that, layout efficiency and the benefits of vertical MOSFETs for SRAM will be highlighted.

We will present our work on epitaxially grown III-V on silicon DFB laser arrays, including results of pure InP-based lasers emitting around 900nm and InGaAs-on-InP lasers emitting around 1300nm.

We report In 0.53 GaAs-channel gate-all-around FETs with channel width down to 7nm and L g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g m by 25% compared to InAs S/D. A g m of 1310 µS/µm with an SS sat of 82mV/dec is achieved for an L g =46nm device. At this L g , a record I on above 200µA/µm is obtained at I off of 100nA/µm and V ds =0.5V on a 300mm Si platform.

In the paper, we review our work on heterogeneous integration of InP photonic devices on silicon. We elaborate on two integration technologies that have been widely explored in the Photonics Research group, i.e. the relatively mature adhesive bonding based integration scheme and a newly demonstrated buffer-less epitaxial growth approach. Based on these techniques, we describe a broad range of photonic devices including mode-locked lasers, high speed directly modulated distributed feedback lasers, electro-absorption modulators, photodetectors, super-luminescent light emitting diodes, etc.

An imperative factor in adapting GeSn as the channel material in CMOS technology, is the gate-oxide stack. The performance of GeSn transistors is degraded due to the high density of traps at the oxide-semiconductor interface. Several oxide-gate stacks have been pursued, and a midgap Dit obtained using the ac conductance method, is found in literature. However, a detailed signature of oxide traps like capture cross-section, donor/acceptor behavior and profile in the bandgap, is not yet available. We investigate the transition region between stoichiometric insulators and strained GeSn epitaxially grown on virtual Ge substrates. Al2O3 is used as high-κ oxide and either Ge1-xSnxO2 or GeO2 as interfacial layer oxide. The interface trap density (Dit) profile in the lower half of the bandgap is measured using deep level transient spectroscopy, and the importance of this technique for small bandgap materials like GeSn, is explained. Our results provide evidence for two conclusions. First, an interface traps density of 1.7 × 10(13) cm(-2)eV(-1) close to the valence band edge (Ev + 0.024 eV) and a capture cross-section (σp) of 1.7 × 10(-18) cm(2) is revealed for GeSnO2. These traps are associated with donor states. Second, it is shown that interfacial layer passivation of GeSn using GeO2 reduces the Dit by 1 order of magnitude (2.6 × 10(12) cm(-2)eV(-1)), in comparison to GeSnO2. The results are cross-verified using conductance method and saturation photovoltage technique. The Dit difference is associated with the presence of oxidized (Sn(4+)) and elemental Sn in the interfacial layer oxide.

Si CMOS technology is currently changing with the introduction of strain and new materials (Ge, III/V) to increase carrier mobility and devicesaturationcurrent.Recently,excellentGe-basedpMOSchannel performance has been demonstrated with intrinsic hole mobilities far above the universal Si mobility curve which is reflected in a clear increase in device current. 1‐4 However, while relaxed Ge exhibits significantly higher intrinsic hole mobilities than relaxed Si, it does not out-perform the current “state of the art” uniaxially strained Si pMOS devices. For Ge channel pMOS devices, compressive uni-axial and/or bi-axial strain implementation seems essential to substantially increase carriers velocity and to outperform current Si- and Si1-yGeybased devices, which is confirmed by theoretical calculations of the carrier mobility and device current. 5‐7 Ge1-xSnx offers schemes to implement the required strain types and levels in the active part of the device. Recent breakthroughs in low temperature hetero-epitaxial Ge1-xSnx and SiyGe1-x-ySnx growth on Si substrates as e.g. reported in references 8‐14 have triggered the assessment of this material system for such electrical device applications. In this contribution we discuss the use of Ge1-xSnx for future (electrical) device applications and its fabrication with a special attention on recent achievements from imec.

Integrating high electron mobility III–V materials on an existing Si based CMOS processing platform is considered as a main stepping stone to increase the CMOS performance and continue the scaling trend. Owing to the polar nature of III–V materials versus the nonpolar nature of Si, antiphase boundaries (APBs) arise in epitaxially grown III–V materials on Si. Here, we demonstrate an approach to restrict the generation of APBs by selectively depositing a III–V material in narrow Si-trenches as formed within the shallow trench isolation (STI) patterned Si(001) wafers. Based on the detailed crystal structures of Si and III–V materials, a concept has been developed comprising the deposition in “v-grooves” with {111} facets in the Si wafer. The grooves are formed by anisotropic wet etching of Si. When InP is deposited selectively into these “v-grooves”, the crystallographic alignment between the Si and InP restricts the APBs nucleation to the corners of the “v-grooved” trench. This approach offers a promising m...

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 Ω.cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.

The semiconductor ICT industry continues its neverending pursuit of new approaches for fabricating integrated circuits to reduce device cost and improve device performance. For future device generations, many different approaches are considered, for which the efficient engineering of new materials and architectures are the main challenge to improve device performance. InP is one of these new materials, which is considered to be used as virtual substrate for III-V based nMOS devices.

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel for quantum well devices. In this work we first investigated building blocks such as passivation and contact resistances on both GaSb and InAs epilayer in order to define the optimal heterostructure for the quantum well device. In a second part, we focused on the growth studies of the complex heterostructure made with "6.1" semiconductors as well as the importance of the interface engineering with TEM. Finally, the properties of the optimized quantum well stack have been studied by means of photoluminescence and high resolution X-ray diffraction.

Three advanced architectures for ultimate progress in Ge p-Metal Oxide Semiconductor Field Effect Transistors are discussed in this paper. Different routes for stress implementations in Ge channels, either biaxial or uniaxial, are proposed by advanced selective Chemical Vapor Deposition techniques. Selective SiGe Strained Relaxed Buffer growth in Shallow Trench Isolation is first discussed to implement biaxial compressive strained Ge Quantum Wells on top of it. Next, innovative GeSn chemical vapor deposition technique is described in order to build either uniaxial strained Ge channel with GeSn Source/Drain stressors or compressively biaxial strained GeSn Quantum Well channels on Ge buffer layers.