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The principal design concern in today's very large-scale integration (VLSI) industry is power dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation places a bottleneck in scaling down the dimensions and supply voltage of metal oxide semiconductor field effect transistor (MOSFET). Short channel effects (SCEs) put a limit on MOSFET scaling. At the lower technology nodes, the control of the gate over the channel is lost in MOSFET. Fin-shaped field effect transistor (FinFETs) uses multiple gates to gain much electrostatic control over the channel. FinFET not only improves the drive current but also reduces the subthreshold leakage. This paper proposes a novel power-efficient technique for the nanoscale regime. The simulation results are derived using Mentor Graphics at a 16 nm node. The power is reduced by 91.45% and 89.01% in the proposed MOSFET and FinFET-based inverter, respectively. A chain of 5-inverters is designed as a benchmark circuit to check the performance comparisons. In the proposed MOSFET and FinFET-based benchmark circuit, there is a power delay product (PDP) reduction of 80.28%, and 99.87%, respectively. The effect of process voltage and temperature (PVT) variations for the robustness of the technique is also discussed. The proposed technique provides the power-efficient and robustness operation against the variations as compared to the other methods. [ABSTRACT FROM AUTHOR]

The single gate driven series connected power device stack possesses the advantages of high compactness and low cost. However, research of its short circuit (SC) characteristic remains uncovered. This article fills this gap and points out that, with the single gate driver it has the potential of over-current limitation. Furthermore, based on it, an improved single gate driven silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfet) stack with strong antishort circuit fault capabilities is proposed. By adding auxiliary circuits to adjust the driving process of the single gate driver, the SiC mosfet stack can be automatically turned off in both SC conditions of fault under load and hard switch fault, while the normal working principle of the stack is not influenced. Neither active control nor overcurrent detection is required, which is the biggest merit of the proposed topology. Its design and analysis are presented in detail, followed by the validation by conducting simulations and experiments. [ABSTRACT FROM AUTHOR]

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs' correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs. [ABSTRACT FROM AUTHOR]

This article presents quick analytical prediction methods of switching loss, turn-on/off overvoltage, di/dt, and dv/dt for SiC metal–oxide–semiconductor field-effect transistor based on device datasheet. First, the switching process is analyzed and the simplification principles are discussed based on charge conservation and flux conservation. Second, the analytical equations of switching loss, turn-on/off overvoltage, di/dt, and dv/dt are derived. Third, experimental results under different operating conditions are presented to validate the proposed methods. It is found that the average prediction error is 10.11%. Finally, relationships between switching performance and different parameters, such as parasitic capacitance, parasitic inductance, dc-voltage, and load current, are analyzed and summarized based on the proposed prediction methods. [ABSTRACT FROM AUTHOR]

A unified model for multigate negative capacitance transistors with self-heating effects (SHEs) is developed. With a metal–ferroelectric–insulator–semiconductor (MFIS) structure, thermal effects result in different temperature rises in the channel and ferroelectric layer. A gate control equation for the double-gate and gate-all-around MFIS structures is developed, on top of which both the current–voltage and charge–voltage characteristics are covered. The formulations describe dependences of ferroelectric layer thickness, with backward compatibility for MOSFETs. A unified thermal network is then proposed for SHE, capturing the essential physics of couplings between ferroelectric temperature and conduction current. The model has been verified with TCAD simulations and implemented for circuit simulations. [ABSTRACT FROM AUTHOR]

Metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short‐channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large‐scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor‐level input‐controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low‐power ICS approach is extensively discussed to verify its importance in low‐power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low‐power and high‐speed techniques at a 22‐nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5‐inverters. [ABSTRACT FROM AUTHOR]

In this work, a new type of graphene ICs only comprising multiple graphene field-effect transistor (GFET) components is first reported. Based on the GFET design that enables homogeneous electrical characteristics in batch-made devices, the practicality and functionality significances of multi-GFET integration are experimentally demonstrated via high-fidelity amplifiers for baseband analog signals. Different from the quadratic relationship of the gate-controlled current output (in saturation region) in the traditional silicon-based MOSFETs, the saturation current output of GFETs relating to the gate-controls possesses high linearity. This advantage overcomes the inherent nonlinear distortion issues in the existing silicon MOSFET amplifiers and potentially provides a promising scenario for the accurate preamplification of weak analog signals. Besides, the novel circuit configuration and signaling principle may expand the developmental paradigm of analog amplifiers and set groundwork for the development and practicalization of advanced carbon-based nanoelectronic ICs. [ABSTRACT FROM AUTHOR]

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates. [ABSTRACT FROM AUTHOR]

While the theoretical maximum of the memory window $\Delta {V}_{t}$ in a ferroelectric field-effect transistor (FEFET) is $2{E}_{C}{t}_{F}$ , ${E}_{C}$ and ${t}_{F}$ being coercive field and FE thickness, respectively, experimentally $\Delta {V}_{t}$ is observed to be much less than that, even in the case of complete polarization switching in the ferroelectric layer. This occurs because trapped charges in the gate oxide stack partially or completely screen the ferroelectric polarization, only a fraction of which gets “electrostatically” reflected in the semiconductor channel. In this article, we provide a generalized experimental framework to quantify the efficiency of practical FEFETs in converting the switched ferroelectric polarization into the memory window. To that end, we propose three efficiency metrics: 1) switched ferroelectric polarization $\Delta {P}_{F}$ to memory window conversion ratio, $\eta _{MW}=\Delta {V}_{t}/\Delta {P}_{F}$ ; 2) switched ferroelectric polarization to the semiconductor charge ($\Delta {Q}_{S}$) conversion efficiency or the charge conversion efficiency $\eta _{c}=\Delta {Q}_{s}/\Delta {P}_{F}$ ; and 3) the ratio of memory window to the width of polarization versus gate voltage hysteresis characteristics ($\Delta {V}_{P}$) or the voltage conversation efficiency $\eta _{V}=\Delta {V}_{t}/\Delta {V}_{P}$. We measure and compare these efficiency metrics in n-type and p-type FEFETs, fabricated in different facilities by different groups. In all the cases, we find that the maximum values of memory window efficiency $(\eta _{MW})_{max}$ , charge conversion efficiency $(\eta _{c}$) $_{max}$ , and voltage conversion efficiency ($\eta _{V}$) $_{max}$ are in the range: 2.5–5.5 Vm2/C, 4%–10%, and 5%–20%, respectively. [ABSTRACT FROM AUTHOR]

In this letter, we comprehensively investigate the electrical properties of the 1200 V planner-gate 4H-SiC power metal–oxide–semiconductor field-effect transistors under the mechanical strains. Three kinds of strains, including the biaxial strain, uniaxial strain parallel to the gate channel, and uniaxial strain perpendicular to the gate channel, are applied using the wafer bending system. It is found that all kinds of compressive strains improve the drain current (Id) under the same gate voltage (Vg) and shift the threshold voltage (Vth) negatively, while the tensile strains decrease Id and shift Vth positively. The Vth shift mainly results from the strain modulated band structure in the poly-Si gate. Under the same overdrive gate voltage (Vov), biaxial strains merely change Id, while both the parallel and perpendicular uniaxial compressive strains enhance Id. The uniaxial compressive strain elevates the electron mobility in the inverted channel by repopulating more electrons into the valleys with a smaller conduction effective mass, which results in the current improvement. [ABSTRACT FROM AUTHOR]

We demonstrate a HfZrO2 (HZO) ferroelectric field-effect transistor fabricated on a silicon-on-insulator substrate, targeting MHz synaptic device applications. Stable multistate weights were implemented with robust retention, excellent linearity, and symmetric potentiation/depression (P/D) in the fabricated HZO ferroelectric field-effect transistors (FeFETs). To further improve the linearity and symmetry of the P/D and to expand the operating condition of the FeFETs as a synaptic device, a novel incremental drain-voltage-ramping method was proposed, and its compatibility was verified thoroughly. The results revealed that a linear and symmetric P/D with stable repeatability was obtained under a wide range of operating conditions, and a learning accuracy of 95% was achieved through MNIST pattern recognition simulations. [ABSTRACT FROM AUTHOR]

Stress-induced damage in a MOSFET can be cured by Joule heating, which can be produced by an intentional forward junction current (${I}_{\textbf {FWD}}$). This curing effect can be further enhanced by the simultaneous application of gate biasing, which does not influence the ${I}_{\textbf {FWD}}$. A MOSFET was intentionally degraded by harsh hot-carrier injection (HCI) then the damage was cured and nearly returned to its pristine state. The improved self-curing effect was quantitatively verified using low-frequency noise (LFN) analyses. Self-curing by internal heat from the ${I}_{\textbf {FWD}}$ more effectively cured the HCI damage than a nonself-curing using external heat from a hot chuck. [ABSTRACT FROM AUTHOR]

In this letter, p-type ferroelectric field-effect-transistors (FeFETs) based on HfO2 and embedded in GlobalFoundries 28 nm bulk high- ${k}$ metal gate (HKMG) technology (28SLPe) are systematically investigated and compared to their n-type counterparts. We show that the two device types, based on Si channel, exhibit a symmetric memory window (MW) and very similar switching behavior, yet profoundly different trapping kinetics. In contrast to n-FeFETs, p-FeFETs display a full MW immediately after the write operation and apparently no parasitic electron trapping. Based on this, we demonstrate an immediate read-after-write operation. Finally, we illustrate how slight structural changes of the gate stack, such as the introduction of the SiGe channel material, can enhance charge trapping and nullify the above-mentioned advantages. [ABSTRACT FROM AUTHOR]

An advanced gate-stack design of ferroelectric (FE) transistors has been proposed and investigated for logic compatible program/erase voltage, better scalability, and suppressed depolarization field. The ferroelectric-metal (FeM) FinFET (FeM-FinFET) and stacked nanosheets transistor (FeM-Nanosheet), which have an FE layer on top of the transistor’s gate, could adjust the area ratio (AR) between the FE capacitor (${A}_{\text{FE}}$) and the MOS capacitor (${A}_{\text{MOS}}$) (AR = ${A}_{\text{FE}} / {A}_{\text{MOS}}$) using the floating gate between them, thereby enhancing the electric field on the FE layer. In particular, the proposed FeM-Nanosheet could have the flexibility to lower the operating voltage and depolarization field by increasing the number of nanosheets to reduce the AR. [ABSTRACT FROM AUTHOR]

GaN ${p}$ -channel field-effect transistors (${p}$ -FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage (${V}_{\mathrm {TH}}$) instability of ${p}$ -channel GaN MOSFETs with Al2O3 as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the ${V}_{\mathrm {TH}}$ exhibits a shift toward more negative values. The impacts of such ${V}_{\mathrm {TH}}$ instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of the drifting ${V}_{\mathrm {TH}}$. [ABSTRACT FROM AUTHOR]

We propose a parallel negative-capacitance field-effect transistor (P-NCFET) structure, in which a ferroelectric operating in its negative-capacitance region is placed in parallel with the gate and source terminals of a MOSFET. The P-NCFET is stabilized by combining careful matching of the ferroelectric with the gate capacitance along with simple feedback realized using current mirrors. The novel stabilization approach opens the possibility for a variety of new applications that exploit the negative capacitance of ferroelectrics to cancel capacitance in integrated circuits. As an example, we show the P-NCFET structure has a significantly higher unity-current-gain frequency ${f}_{T}$ compared to a conventional MOSFET. [ABSTRACT FROM AUTHOR]

We present and discuss explicit closed-form expressions for the saturation drain current of short-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz–Krummenacher–Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert ${W}$ function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-current ratio, can be readily expressed as explicit functions of the terminal voltages. [ABSTRACT FROM AUTHOR]

This article presents, for the first time, a study about of behavior of the intrinsic effects from diamond layout style [longitudinal corner effect (LCE) and PArallel connection of MOSFETs with Different channel Lengths Effect (PAMDLE)] for metal–oxide–semiconductor field-effect transistors (MOSFETs) influenced by wide high-temperature ranges. These effects are capable of boosting the electrical performance of analog MOSFETs in relation to that of the standard MOSFET (rectangular gate shape). First, we have developed an experimental comparative study between MOSFETs implemented with the hexagonal layout style diamond MOSFET (DM) and its rectangular MOSFET (RM) counterpart, regarding that they present the same channel width and gate area, operating in a wide high-temperature range (from 300 to 573 K). These devices were manufactured with the technology of bulk complementary MOS (CMOS) integrated circuits (ICs) of 180 nm. The experimental results have shown that DM has obtained a better electrical performance of analog MOSFETs than the one observed in RM counterpart (for example, gains of 67% for saturation drain current and 90% for the transconductance), regardless of temperatures in which they were exposed. 3-D numerical simulations were used to justify the better electrical performance of DMs due to the LCE and PAMDLE effects, in relation to one of the RM counterparts, by observing the behavior of electrostatic potentials, longitudinal electric fields, and drain current densities of the devices as the temperature increases. Besides, a study about the short-channel effect has shown that DM can suppress this effect more effectively than RM at room temperature due to a smaller reduction in effective channel length of DM. [ABSTRACT FROM AUTHOR]

GaN-based high electron mobility transistors (HEMTs) have received much attention due to their potential usage in radio-frequency and high power applications. However, the development of logic gates has remained mostly elusive due to the still challenging reliable operation of the field-effect enhancement-mode n-transistor and nascent stage for the p-transistor. The n-transistor behavior is mainly achieved by combining the aggressive thinning down of the barrier layer, using charged oxides, and p-doping the cap layer. The p-transistor generally requires a heavily doped p-GaN layer. The realization of both transistors on the same substrate remains challenging due to the conflicting requirements for n- and p-transistors. Here, we propose a GaN-based field-effect complementary transistor device using a p-doped InGaN/GaN superlattice (SL) structure on top of the barrier layer of the HEMT heterostructure. The SL structure changes the electrostatics of the heterostructure by the formation of a two-dimensional hole gas region. An undoped SL structure is shown to be enough to lift the conduction band-edge above the Fermi level to convert the n-transistor from depletion-mode (D-mode) to enhancement-mode (E-mode). The lifting of the bands, in turn, creates a natural quantum-well for the holes in the p-transistor. An additional p-doping of the SL moves the threshold voltage of the E-mode n-transistor further into a positive direction and increases the hole density in the quantum-well E-mode p-transistor. The SL structure, which can be grown by a standard epitaxial process, facilitates the realizations of both the n- and p-transistors. The characteristics of individual devices are further analyzed. A digital inverter gate is simulated, and critical static and dynamic performance parameters are reported. The propagation delay indicates that logic operations can be done at a very high speed compared to those offered by other conventional semiconductors. [ABSTRACT FROM AUTHOR]

A dynamic current model for the double gate negative capacitance field-effect transistor (NCFET) of the metal–ferroelectric–insulator–semiconductor (MFIS) structure is presented in this work. With a damping parameter ρ in the Landau–Khalatnikov (LK) theory for general ferroelectric (FE) materials, the gate control equation of NCFET is intrinsically dynamic which is solved directly as a basis of NCFET modeling. With the time-dependent charge densities at the source and drain sides, a dynamic current model is formulated analytically for the first time, considering the dynamic terms in a self-consistent way. The model has been verified with numerical TCAD simulations. It accurately reproduces the static negative capacitance (NC) effect in enhancing the driving current, as well as the dynamic NC effect, in the conduction delay and hysteresis for a wide range of NCFET parameters. The dynamic model after implementations is successfully applied to circuit simulations such as ring oscillators without convergence issues. [ABSTRACT FROM AUTHOR]

In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower technology nodes. This paper designs a low leakage input dependent (INDEP) approach for FinFET devices at 16 nm technology node. Numbers of logic gates are designed and simulated with the help of MOSFET and FinFET devices. Simulation results are compared by calculating the important parameters like leakage power, delay and power delay product (PDP). The designed low leakage INDEP approach is compared with the leakage control transistor (LECTOR) technique. Simulation results for different logic circuits show the large reduction in leakage power in case of FinFET logic gates as compared to MOSFET devices and more leakage saving in case of INDEP approach as compared to conventional as well as LECTOR technique. Reliability in terms of process, voltage and temperature (PVT) variations is checked by running the Monte-Carlo simulations for 1000 samples and observed that INDEP circuits are more reliable. [ABSTRACT FROM AUTHOR]

We have experimentally demonstrated robust beta-gallium oxide (β-Ga2O3) ferroelectric (FE) field-effect transistors (FeFETs) on a sapphire substrate operated up to 400 °C. Atomic layer deposited (ALD) Hf0.5 Zr0.5O2 [hafnium zirconium oxide (HZO)] is used as the FE dielectric. The HZO/β-Ga2O3 FeFETs are studied for their synaptic behavior applications at elevated temperatures. The devices show distinguishable polarization switching operation with the output conductance quasi-linearly controlled by the number of input pulses on the FE gate. In a simulation, on-chip learning accuracy reaches 94% at elevated temperatures using the Modified National Institute of Standards and Technology (MNIST) data set with a simple two-layer multilayer perceptron (MLP) network. These ultra wide bandgap semiconductor devices have the potential to fill the need for harsh environment neuromorphic applications. [ABSTRACT FROM AUTHOR]

An improved lateral power p-channel trench metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed. By using a technique of variation vertical doping (VVD), the threat of charge imbalance posted by the parasitic trench capacitance is eliminated. Moreover, a p-type VVD increases the number of carriers, and an n-type VVD intensifies the charge compensation effect. Hence, compared to the conventional device without VVD, the proposed device gets a significantly improved tradeoff relationship between the breakdown voltage (BV) and the specific ON-resistance (RON,SP). According to the simulation results, the proposed device using the triple piecewise VVD obtains a RON,SP of 10.6 mΩ ⋅ cm2 at a BV of 440 V, reaching a figure of merit (FOM = BV2/RON,SP) being 2.4 times larger than that of the prior art. [ABSTRACT FROM AUTHOR]

In this article, for the first time, a variation of lateral doping (VLD) technique was proposed to improve blocking voltage and ON-resistance properties in the lateral β-Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET). Enhancement-mode operation was achieved in the VLD transistor. The maximum transconductance of this new device is more than three times as large as the uniformly doped (UD) transistor. Moreover, the OFF-state electric field at the channel was suppressed compared to the UD transistor, resulting in higher blocking voltage. We also investigated the optimal device properties with changing channel concentration in the drift region of VLD transistor. A power figure of merit of 332.7 MW/cm2 was reached by VLD design. Thus, this proposed structure provides a new design strategy for high-power β-Ga2O3 MOSFETs. [ABSTRACT FROM AUTHOR]

We report the characterization of the channel mobility properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the heterogeneous β-Ga2O3-on-SiC (GaOSiC) substrate fabricated by an ion-cutting process. The mobility of GaOSiC MOSFETs is significantly improved as the postannealing temperature of Ga2O3 channel increases from 900 °C to 1200 °C. The GaOSiC transistor annealed at 1200 °C exhibits mobility consistent with the β-Ga2O3 donor wafer, which suggests that the defects in Ga2O3 channel induced by the H+ implantation for the ion-cutting step can be eliminated by the high-temperature annealing. As the ambient temperature (Tamb) increases from 0 °C to 150 °C, the mobility within the accumulation regime of GaOSiC MOSFETs decreases with the temperature following a Tamb−1 law, which is limited by the phonon scattering. The results of this work will be critically important for designing the transport properties of the GaOSiC channel, significantly advancing the development of Ga2O3 power devices on high thermal conductivity substrate. [ABSTRACT FROM AUTHOR]

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap. [ABSTRACT FROM AUTHOR]

In this letter, a model that predicates the degradation of 4H-SiC power metal-oxide-semiconductor field-effect transistors under repetitive avalanche stress is proposed. Since positive charges are injected into the gate oxide interface of the JFET region, the gate-drain capacitance $(C_{gd})$ is chosen as the targeted parameter to quantify the avalanche induced degradation. The relationship between the increment of the $C_{gd}$ and the injected charge density is calculated and validated to demonstrate the rationale of the model. It is found that the increment of $C_{gd}$ has a linear relationship with the logarithm of the total avalanche energy (EAV) dissipated on the device. Excellent agreement is also achieved between the simulated degraded data and the measured one, further proving the accuracy of the proposed degradation model. [ABSTRACT FROM AUTHOR]

Hydrogen-terminated (C-H) diamond has a high current density owing to the 2-D hole gas (2DHG) on its C-H diamond surface. The C-H diamond metal-oxide-semiconductor field-effect transistor (MOSFET) has high-breakdown-voltage characteristics but exhibits normally-ON operation. For security and energy-saving purposes, we fabricated the diamond cascode using the C-H diamond p-channel field-effect transistor (p-FET) combination with the normally- OFF silicon p-FET. The diamond cascode exhibits normally- OFF characteristics and a high breakdown voltage of more than 1.7-kV. [ABSTRACT FROM AUTHOR]

Fabrication of gate-recessed SrSnO3 (SSO) metal-semiconductor field-effect transistors (MESFETs) with Ni Schottky gates is reported on bi-layer epitaxial SSO films with a thin heavily-doped cap layer. Devices with 0.5- $\mu \text{m}$ gate length showed enhancement-mode behavior with a saturation drain current, ${I}_{\text {DSAT}}$ , of 33 mA/mm and peak transconductance, ${g}_{\text {m,max}}$ , of 65 mS/mm. The ${g}_{\text {m,max}}$ value is a roughly $2\times $ improvement over control devices fabricated on single-layer films. Gate-recessed SSO MESFETs with Pt Schottky gates were also explored on the bi-layer films. Devices with 1- $\mu \text{m}$ gate length displayed ${I}_{\text {DSAT}} =133$ mA/mm and $g_{\text {m,max}} =73$ mS/mm, after thermal annealing. [ABSTRACT FROM AUTHOR]

The dV/dt in superjunction metal–oxide–semiconductor field-effect transistors (MOSFETs) during the turn-off transient has been shown to be higher than during the turn-on, which can be attributed to a shorter Miller plateau. In this article, we will show that these asymmetrical turn-on and turn-off characteristics are indirectly detected by the hysteresis of the dynamic gate-to-drain capacitance, CGD. Moreover, this article reveals the mechanisms behind the asymmetrical switching and the origin of the hysteresis, which have been shown to be caused by the difference in the CGD displacement current paths for the turn-off and the turn-on. [ABSTRACT FROM AUTHOR]

The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4- bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude. [ABSTRACT FROM AUTHOR]

As the dimensions of the power metal-semiconductor field-effect transistor (MOSFET) are scaling down, and the output capacitance is considerably reduced, the fast dV/dt becomes an issue and can trigger severe oscillations during hard switching. To understand the origin of the dV/dt and the induced gate oscillations, the intricate link between the device operation and the circuit conditions is required. In this article, the dynamic gate-to-drain capacitance, CGD, is extracted by employing a five-terminal method. Through the use of simulations, the relationship between CGD and the induced gate oscillations is explored. In addition to this, the 2-D depletion behavior in a superjunction system, which affects the dynamic CGD, is investigated. [ABSTRACT FROM AUTHOR]

A superjunction metal-oxide-semiconductor field-effect transistor (SJ-MOSFET) with P-base and N-pillar Schottky contacts is proposed and investigated in this article. The dual Schottky contacts form a p-type Schottky diode and an n-type Schottky diode on the surface of the device, respectively. During the reverse conduction stage, the operation of the body p-n junction diode is suppressed by the reverse-biased p-type Schottky diode, and the reverse current is fully conducted by the n-type Schottky diode. Therefore, the minority carrier injection is completely suppressed, leading to an ultralow reverse recovery charge. TCAD simulation results show that, in comparison with the conventional SJ-MOSFET, up to 95.7% reduction in reverse recovery charge could be achieved. [ABSTRACT FROM AUTHOR]

Josephson junction FETs (JJ-FETs) share design similarities with MOSFETs, except for the source/drain contacts being replaced by superconductors. Similarly, the super current due to proximity effect is tunable by the gate voltage. In light of recent advances in novel materials and fabrication techniques, we examine here the feasibility of JJ-FET-based Boolean logic and memory elements for cryogenic computing. Using a 2-D ballistic transport JJ-FET model, we implement circuit-level simulations for JJ-FET logic gates and discuss criteria for realizing signal restoration, as well as fan-out. We show that the JJ-FET is a promising candidate for very low-power, clocked voltage-level dynamic logic at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

Experimental characterization of the damage induced to SiC power MOSFETs by heavy-ion irradiation is presented as a premise to a finite element simulation study aimed at gaining an insight into the physics of damage formation. Thanks to the new experimental setup, which is capable of accurately measuring the time evolution of the gate and drain leakage currents during irradiation, we herein demonstrate that the gate of a SiC power MOSFET is damaged by heavy-ion irradiation at biasing drain voltages lower than 100 V, which is less than 10% of the nominal blocking voltage of the tested devices. The evolution of the gate and drain leakage currents during irradiation is explained considering that localized resistive paths due to damage sites are formed across the gate oxide. The results presented herein indicate the strong sensitivity of SiC power MOSFETs to gate rupture even if the main concern in the literature addressed so far is the rupture of the drain structure due to single-event burnout. [ABSTRACT FROM AUTHOR]

We propose a steep-slope MoS2-nanoribbon field-effect transistor that exploits a narrow-energy conduction band to intrinsically filter out the thermionic tail of the electron energy distribution. We study the device operation principle and the performance dependence on the design parameters through atomistic self-consistent quantum simulations. Our results indicate that the device can provide high ${I_ {\mathrm{\scriptstyle {ON}}}/{I}_{\mathrm{\scriptstyle {OFF}}}}$ ratios, compatible with electronic applications, albeit biased at the ultra-low voltages of around 0.1 V. [ABSTRACT FROM AUTHOR]

Electrostatically formed nanowire (EFN) transistor is a majority carrier silicon-on-insulator (SOI) device, operated in the depletion mode, with the conducting channel size and position modulated by surrounding gates. When operated in the subthreshold regime, the EFN transistor is an efficient temperature sensor. We present a novel EFN transistor design with a top gate, named gate-all-around EFN (GAA EFN), allowing increased temperature sensitivity. The new design enables the formation of the EFN conductive channel in the volume of the SOI device layer, far from the top and bottom silicon/oxide interfaces, thus reducing the noise level and increasing the temperature sensitivity to 13.3%/K. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

How far can the miniaturization of metal–oxide–semiconductor field-effect transistors (MOSFETs) continue is a recurring question, essential to all aspects of digital technology. Recent claims of well-performing MOSFETs with gate lengths below 4 nm apparently defy the fundamental limit of source-to-drain direct tunneling (SDDT). Here, we investigate that limit by simulating gate-all-around Si nanowire FETs with gate lengths between 8 and 3 nm using the state-of-the-art atomistic quantum transport modeling. We find that at 3-nm gate length, the current is dominated by SDDT, resulting in large source–drain leakage and poor switching performance even if the gate modulates the potential barrier between the source and drain sufficiently well. However, at 6-nm gate-length SDDT barely starts to degrade the subthreshold characteristics at large drain bias, and the ballistic ON-/OFF-current ratio is ~106 with a subthreshold swing of 70 mV/decade, on par with contemporary Si technology. This means that in the best case, the technology roadmap could potentially be extended for several generations beyond the currently projected nodes. In addition, the results substantiate that the experimental devices with the claimed gate lengths below 6 nm in fact operate with a longer effective gate lengths. [ABSTRACT FROM AUTHOR]

This paper presents a novel 16-bit arithmetic logic unit (ALU) design by cascading simple 1-bit ALUs using metal–oxide-semiconductor field effect transistor (MOSFET) and FinFET technologies while incorporating adiabatic switching principle. Analyses are carried out at 32 nm Berkley predictive technology module (PTM). The paper has employed popular standard adiabatic logic families– such as quasi-static energy recovery logic (QSERL), two phase drive adiabatic dynamic complementary metal oxide semiconductor (CMOS) logic (2PADCL), adiabatic dynamic CMOS logic (ADCL), and two phase clocked adiabatic static CMOS logic (2PASCL). Single-phase adiabatic logic circuit is also introduced. Results show that the proposed technique has power savings of 67.14 %, 39.47 %, 34.65 %, 8.73 %, and 4.16 % for CMOS, QSERL, 2PADCL, ADCL, and 2PASCL respectively with MOSFET technology whereas, it saves 95.22 %, 21.34 %, 20.75 %, 15.66 %, and 8.69 % respectively for same literatures with FinFET technology. [ABSTRACT FROM AUTHOR]

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( T\textsf {FE}) is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of T\textsf {FE} on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing T\textsf {FE} yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as T\textsf {FE} is increased. Depending on the attributes of the underlying transistor, increasing T\textsf {FE} beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of T\textsf {FE} on the circuit energy–delay. Our analysis shows that for high T\textsf {FE} , the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay. [ABSTRACT FROM PUBLISHER]

A new charge-based analytical compact model for the drain current of junctionless (JL) triple-gate MOSFETs is presented, which includes the short-channel effects, the saturation velocity overshoot, the series resistance, and the mobility degradation effects. The proposed model consists of a single analytical equation that covers the depletion operation region in which the bulk conduction determines the drain current. The model is supported by experimental measurements in JL nanowire transistors with channel length varying from 95 to 25 nm and doping concentration 2 \times 10^19 cm ^\mathrm -3 . The overall results reveal the very good accuracy of the proposed analytical compact model, making it suitable for circuit simulation tools. [ABSTRACT FROM PUBLISHER]

Advancement in the metal oxide semiconductor field effect transistor (MOSFET) technology leads to large power dissipation, and propagation delay due to extreme scaling of the transistor. So, very large-scale integration (VLSI) industry requires alternative options to meet the demands of the customers. Fin-shaped field effect transistor (FinFET) is new innovative device to replace the MOSFET technology in ultra-deep submicron (ultra-DSM) regime. FinFET mitigates power dissipation to the large extent as compared to the MOSFET, but still the impact of power dissipation degrades the circuit performance. Leakage reduction techniques are further needed in ultra-DSM regime to reduce the power dissipation. Domino logic is commonly used in large memories, and high-speed processors. In this article, a low power domino logic is proposed using FinFET devices. The proposed method is compared to the existing similar domino logic approaches for the different performance metrics at 7 nm technology node using Cadence's tools. The proposed method effectively reduces the leakage power dissipation, and delay penalty for the different logic circuits. The reliability of the domino OR logic is checked by estimating the temperature, and multiple parallel fins variations. The proposed method has a high noise tolerance capacity in term of unity noise gain (UNG) for the domino OR logic as compared to the existing approaches. [ABSTRACT FROM AUTHOR]

It is demonstrated that nanoprobing technique is superior in localizing silicide defect rapidly in metal-oxide-semiconductor field-effect transistor (MOSFET). Cobalt silicide (CoSi 2) as an interfacial material below tungsten contact plug, various types of defects about CoSi 2 often cause leakage current in MOSFET, so close studies of problematic silicide is significant regarding MOSFET reliability enhancement. When one MOSFET in a combinational logic circuit is suspected of anomaly, because this kind of circuit is composed of several devices which are sometimes arranged in an active area (AA) of unique geometric shape, it is impossible to collect MOSFET characteristic correctly based on regular nanoprobing flow since conventional method hits limit for combined circuits measurement. Such circumstance almost impedes failure analysis (FA) in device level. Nevertheless, relying on our alternative strategy of multi-probe configuration, a novel nanoprobing analysis flow is adopted for device examination. It is shown that exact I-V characteristic of failed device can be captured by proposed workflow. Following I-V curve analysis further reveals an evident electrical signature of abnormal abrupt junction. It corresponds to an active area shorting with its surrounding nwell region. In addition, sophisticated leakage current behaviors are exhaustively interpreted by simplified models. Eventually, we confirmed CoSi 2 encroachment from the active area into nwell by the means of transmission electron microscopy (TEM) analysis. This paper presents an effective analysis to identify leaky junction of MOSFET in logic circuit that is rarely reported before. Furthermore, our exploration exhibits impressive flexibility of nanoprobing analysis in terms of localizing unusual silicide defect, so nanoprobe analysis is clearly an attractive option to optimize MOSFET manufacturing. • Propose a novel nanoprobing workflow to identify minute silicide encroachment into well of MOSFET. • Sophisticated leakage current behaviors are exhaustively interpreted by simplified models. • Demonstrate the merit of multi-probe configuration regarding analysis of faulty combinational logic circuit. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a model for the surface potential and the drain current of a dual-material double-gate (DMDG) junctionless FET (JLFET) transistor. A finite-differentiation method has been used to decompose the 2-D Poisson’s equation into two 1-D equations, which allows the modeling of the DMDG structure as two individual single-material double-gate JLFETs. The two 1-D models are then combined using appropriate boundary conditions to provide a simple solution to the complex 2-D Poisson’s equation. The proposed model has been verified for different values of doping concentration ( ND ), oxide thickness ( T\mathrm{ ox} ), and channel thickness ( T\mathrm{ si} ) against the numerical simulations. [ABSTRACT FROM AUTHOR]

In this paper, we built potential and current models for quadruple-gate junctionless filed-effect transistor (QGJLFET) in subthreshold regime. A new potential distribution function is provided for the cross section of QGJLFETs, based on which we derived a more accurate expression of natural length for QGJLFETs. The result shows that a quadruple-gate FET is far more than a simple composition of two double-gate FETs, but with some coupling components. To avoid complex computation of potential near the corner, we come up with a new concept of equivalent insulator thickness, transforming the influence of corner into the change of insulator thickness. With these renewed parameters and scaling equation, the potential distribution in channel is finally obtained. Based on this potential model, subthreshold current is derived using drift-diffusion approach and Pao-Sah integral. [ABSTRACT FROM AUTHOR]

We present an array of 225 field-effect transistors (FETs), where each of them has a graphene monolayer channel grown on a 3-layer deposited stack of 22 nm control HfO2/5 nm Ge-HfO2 intermediate layer/8 nm tunnel HfO2/p-Si substrate. The intermediate layer is ferroelectric and acts as a floating gate. All transistors have two top gates, while the p-Si substrate is acting as a back gate. We show that these FETs are acting memtransistors, working as two-input reconfigurable logic gates with memory, the type of the logic gate depending only on the values of the applied gate voltages and the choice of a threshold current. [ABSTRACT FROM AUTHOR]

Highlights: [•] We model the effects of an oxide breakdown on the transistor behaviour. [•] We consider the potentiometer model. [•] We show how the relevant feature that characterize the dielectric breakdown affect the transistor’s transconductances. [Copyright &y& Elsevier]