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In this work, a digital phase‐locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra‐low power consumption adopts the near‐threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low‐supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time‐to‐digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma‐delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz. [ABSTRACT FROM AUTHOR]

A highly integrated three-state diplexer (TSD) on a single planar elliptical structure is for the first time presented in this paper. Three resonant modes are investigated in a planar elliptical resonator, e.g., two TM11 degenerate modes and one TM21 mode. These three resonant modes are designed to form three filtering channels, which are further combined to generate three states of a diplexer, namely, TSD. The planar elliptical triple-mode resonator is fed by three microstrip lines to form a triple-mode TSD. In order to validate the concept, the designed planar TSD is fabricated and measured. The measured results are in good agreement with the simulated ones. [ABSTRACT FROM AUTHOR]

In this paper, we present a low-power low-noise integer-N divider-less digital phase-locked loop (PLL) with high resolution. Phase detection is performed by a proposed analog-to-digital converter (ADC)-based time-to-digital converter composed of subsampling, charge pump (CP), time-domain variable-gain amplifier, and successive-approximation register (SAR) ADCs. Subsampling is well known for its high detection gain. The CP and the pulse generating circuit are also introduced to form the time-domain integral variable-gain amplifier, enhancing the resolution. An SAR ADC voltage signals into the digital domain, avoiding the use of analog filter which occupies large area. Moreover, compared to the conventional analog phase detectors, the SAR-ADC phase detector saves more area and power consumption. The novel PLL is implemented in a standard 65-nm CMOS process, occupying an area of 0.12 mm2. It presents an in-band phase noise of −108 dBc/Hz and an rms jitter of 357 fs at the operating frequency of 5 GHz. In addition, the proposed ADC-PLL achieves a competitively good figure of merit of 243 dB with a power consumption of only 3.9 mW. [ABSTRACT FROM AUTHOR]

Although often analyzed as a second-order system, digital phase-locked loop (DPLL) is actually a third-order system because of the intrinsic latency in the loop filter. The extra pole introduced by this additional clock latency requires the loop filter bandwidth to be correspondingly reduced to ensure stability. In many applications, however, the loop bandwidth needs to be as wideband as possible, since the digital-controlled oscillator (DCO) is often the dominant source of noise. A modified proportional–integral (PI) loop filter is proposed to widen the loop bandwidth. The proposed loop filter employs an additional internal feedback loop that causes a third-order DPLL system to effectively behave as a second-order system. The proposed loop filter is derived based on the observer-controller DPLL. An intuitive explanation based on pole-zero analysis suggests that a wider loop bandwidth can be employed than in the conventional PI loop filter, because the proposed loop filter pushes the extra pole to a higher frequency than in the conventional loop filter. Similarly, for the same open-loop unity gain frequency and phase margin, the proposed loop filter can place the zero at a higher frequency, enabling greater attenuation of the DCO noise while achieving the same lowpass filtering of the reference clock noise as in the conventional loop filter. [ABSTRACT FROM AUTHOR]

A novel electronically steerable phased array antenna is developed for global positioning system/broadband global area network (GPS/BGAN) navigation applications. The array is composed of 2 x 2 printed quadrifilar helical antennas (PQHAs) integrated with digital phase shifters for beam steering over the transmit/receive bands. The feed network of each PQHA is based on a sequential rotation to achieve wideband circular polarisation (CP). An elegant control network with the embedded microcontroller is designed to provide driving bits to the phase shifters with reduced phase error. The meandered line design maintains high-performance CP radiation up to ±60° off-axis, within 1525 to 1660 MHz, and its size is 44% of the design with straight lines. The array gain is positive over 1450-1800 MHz beyond the BGAN band, with better than 13 dB return loss and <2.2 dB axial ratio. The measured broadside gain of the array exceeds 8.5 dBi at 1600 MHz, and has a wide beam steering of ~ ±80° over the BGAN band. The developed antenna represents a significant technical advance to the design and manufacturing of PQHA array, it has a compact size, low cost and lightweight with a relatively large bandwidth and almost hemispherical coverage with excellent right-hand circularly polarized radiation. [ABSTRACT FROM AUTHOR]

A multirate fractional-N RF digital phase-locked loop (DPLL) phase modulator implementation for polar transmitter supporting cellular communication standards up to 4G LTE-A is demonstrated. The RF-DPLL integrates LC-tank-based digital-controlled oscillator (DCO) cores with $\Sigma $ – $\Delta $ -noise shaping and fractional sample rate conversion to account for a broad range of frequency bands and spectral emission requirements. A two-point modulation with different sampling rates and signal scaling is applied to optimize the system for operation in narrow-band and wide-band phase modulation. DCO digital predistortion and DCO gain estimation in combination with open-loop gain auto adjustment and delay calibration are implemented to achieve sufficiently low-in-band distortion. Measurement results of the RF-DPLL system as part of a polar transmitter implemented in 28-nm CMOS are shown, fulfilling 3GPP specifications for 4G, LTE-A uplink and legacy cellular communication standards like 3G, UMTS/HSPA+ and 2G, GSM/EDGE. [ABSTRACT FROM AUTHOR]

A pattern synthesis technique for real and coupled antenna arrays by using digital phase-only excitation weights is introduced here. The method is formulated as an integer linear programming problem incorporating a fast full-wave analysis of the array, based on the finite element method and spherical mode expansions. The method achieves radiation patterns with specified pointing directions, main lobe widths, minimum sidelobe level, and prescribed nulls, controlled by digital phase shifters. [ABSTRACT FROM AUTHOR]

For timing and synchronization system, digital phase-locked loop (DPLL) and Kalman filter all have been widely used as the clock tracking and clock correction schemes for the similar structure and properties. This paper compares the two schemes used for ultrawideband (UWB) location system. The improved Kalman filter is more immune to interference. [ABSTRACT FROM AUTHOR]

This paper presents a novel Time-to-digital converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a gated ring oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. The proposed TDC is designed in 90 nm CMOS process. Simulation results show that the TDC achieves a large detectable conversion range that extends between 0.285 and 10 ns. The attained time resolution is 9.4 ps, which corresponds to half the delay time of an inverter. The TDC is self-calibrating with estimated accuracy better than 0.28%. The structure consumes 6.6 mA current from a 1.0 V voltage supply, when operating at a clock frequency of 13 MSPS. The estimated differential nonlinearity and integral nonlinearity are ±0.48 LSB and ±0.6 LSB respectively. Compared to previously reported TDC, this implementation achieves a competitive FoM without requiring complicate calibration. [ABSTRACT FROM AUTHOR]

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation. [ABSTRACT FROM AUTHOR]

Self-organized synchronization occurs in a variety of natural and technical systems but has so far only attracted limited attention as an engineering principle. In distributed electronic systems, such as antenna arrays and multi-core processors, a common time reference is key to coordinate signal transmission and processing. Here we show how the self-organized synchronization of mutually coupled digital phase-locked loops (DPLLs) can provide robust clocking in large-scale systems. We develop a nonlinear phase description of individual and coupled DPLLs that takes into account filter impulse responses and delayed signal transmission. Our phase model permits analytical expressions for the collective frequencies of synchronized states, the analysis of stability properties and the time scale of synchronization. In particular, we find that signal filtering introduces stability transitions that are not found in systems without filtering. To test our theoretical predictions, we designed and carried out experiments using networks of off-the-shelf DPLL integrated circuitry. We show that the phase model can quantitatively predict the existence, frequency, and stability of synchronized states. Our results demonstrate that mutually delay-coupled DPLLs can provide robust and self-organized synchronous clocking in electronic systems. [ABSTRACT FROM AUTHOR]

This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range as compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS320C6416 DSP development kit.

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model. [ABSTRACT FROM AUTHOR]

A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The digital PLL is simulated in a 65 nm CMOS process, consuming 11.2 mW from a 1.0 V supply. [ABSTRACT FROM AUTHOR]

The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. However, this added delay will limit the stable operation range and hence lock range of the loop. The objective of this work is to extend the lock range of ZCDPLL with time delay by using a chaos control. The tendency of the loop to diverge is measured and fed back as a form of linear stabilization. The lock range extension has been confirmed through the use of a bifurcation diagram, and Lyapunov exponent.

A compact low‐supply‐voltage yet low‐noise digital bang–bang PLL (DBBPLL) is proposed. The bang–bang phase detector is based on a dynamic double‐tail latch which enables high time‐to‐voltage gain and low input‐referred noise under tight power‐supply headroom. The ring‐based digitally controlled oscillator (DCO) is made of multiple gm‐controlled delay units and a constant‐gm‐biased current DAC. By combining these two blocks, the DCO can now better tolerate supply noise and process variations. A prototype DBBPLL has been implemented in a mainstream 28 nm CMOS process with a compact die area of 0.014 mm2. When operating at 2.6 GHz, it consumes 2.9 mW with 0.75 V supply and achieves low in‐band phase noise of −105 dBc/Hz. [ABSTRACT FROM AUTHOR]

A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200-400 mV pp signals at date rates of 1.25-5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm, while the actual driver occupies only 190 μm. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below −138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44-1.4 mW/Gbps with external clock and 2.6-4.7 mW/Gbps with clock synthesizer. [ABSTRACT FROM AUTHOR]

In this study, a fast and fully software‐based algorithm for digital phase‐locked loop (PLL) is proposed via a new hybrid approach in software and hardware by using an advanced digital signal processor architecture. The proposed algorithm is robust against line disturbances such as phase‐angle jump, voltage sag, third harmonic injection, multi‐zero crossing and step change in frequency at the input voltage. Performance and robustness of the proposed method are investigated through experimental studies. Furthermore, it is compared with three different PLL algorithms in detail to show its superiority over existing methods. [ABSTRACT FROM AUTHOR]

The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase‐locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9-7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations. [ABSTRACT FROM AUTHOR]

A new three-phase digital phase-locked loop (DPLL) is proposed to determine the instantaneous grid frequency under power system disturbances. The proposed solution is based on single-phase DPLL algorithms, defining the estimated grid frequency as a nonlinear weighted mean of the three single-phase DPLL outputs. Orthogonal signals required by the DPLL algorithms are obtained through a fictitious quadrature voltage using five different appropriated approaches. The proposed structures have been assessed through extensive analysis under balanced and unbalanced conditions. For this purpose, real voltage dips collected in a Spanish wind farm along several months are included in the paper as examples of frequency estimations. In addition, results from conventional three-phase DPLL topologies are presented to confirm the validity of the proposed DPLL structures. [ABSTRACT FROM AUTHOR]

This article investigates the effect of the conventional and extended time-delayed feedback control techniques of chaos control on a first-order positive zero-crossing digital phase locked loop (ZC1-DPLL) using local stability analysis, two-parameter bifurcation studies and two-parameter Lyapunov exponent spectrum. Starting from the nonlinear dynamics of a ZC1-DPLL, we at first explore the time-delayed feedback control (TDFC) algorithm on a ZC1-DPLL in the parameter space. A condition for the optimum value of the system control parameter is derived analytically for a TDFC based ZC1-DPLL. Next, the extended time-delayed feedback control (ETDFC) technique on a ZC1-DPLL is described. It is observed that the application of the delayed feedback control (DFC) technique on the sampled values of the incoming signal inside the loop finally results in the nonlinear DFC of the phase error dynamics. We prove that, for some suitably chosen control parameters, an ETDFC based ZC1-DPLL has a broader stability zone in comparison with a ZC1-DPLL and its TDFC version. [ABSTRACT FROM AUTHOR]

This paper identifies the unavoidable time skew between counter and TDC inputs, if not properly compensated or corrected, as the major source of spurs in the output spectrum of an All-Digital-Phase-Locked Loops (ADPLLs). The frequency and the level of the main spur induced by the time skew are first analytically estimated. Then, an ADPLL, operating in the 3-4-GHz band, is designed in 90-nm CMOS technology and the reported simulations confirm the theoretical results. A simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts is proposed. The glitch corrector is demonstrated to cancel out the −24-dBc spur and its harmonics, without altering the lock transient behavior of the ADPLL. [ABSTRACT FROM AUTHOR]

Applying gear shifting algorithms to the implementation of Phase Locked Loops (PLLs) can significantly improve their performances. However, the behaviors of gear shifting digital PLLs (GSDPLLs) have not been fully studied due to the existence of newly adaptive control parameters. These parameters play a very important role in the design of GSDPLLs. In this paper, various nonlinear behaviors of GSDPLLs including the steady state periodic behaviors, divergent behaviors and chaotic behaviors, are studied. In particular, the effects of the initial conditions of GSDPLLs on their dynamical behaviors are investigated. The obtained results are useful for the design of GSDPLLs. Numerical simulation results are presented for illustrations. [ABSTRACT FROM AUTHOR]

Abstract: A repetitive-Fuzzy PID and digital phase-locked loop (DPLL) integrating control strategy for High-Frequency(HF) inverter power supply is presented. The power modulation of HF-Inverter used repetitive-Fuzzy PID compound control,which can enhance the ability of the control system to withstand the parameter variations and nonlinear uncertain disturbances, and improve the dynamic characteristic of the control system; the DPLL was applied.to control the output frequency of HF-inverter,which reduce the losses of switching components and improve the efficiency of the power system. The experimental results show that the proposed control scheme can endow the HFinverter power supply with good steady state and dynamic performance and the power modulation control system can keep better precise control quality, high output power factor and verify the validity of the proposed integrated control strategy. [Copyright &y& Elsevier]

The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency. [ABSTRACT FROM AUTHOR]

A spur reduction technique in fractional‐N phase‐locked loops based on a current‐mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45° offset in each quadrant, and this non‐linear property leads to fractional spurs. The proposed 45° phase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement. [ABSTRACT FROM AUTHOR]

A near‐threshold all‐digital phase‐locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near‐threshold condition from 0.52 to 0.58 V VDD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V VDD, a lock‐in time of 9.5 μs at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 μW. Consequently, the proposed ADPLL with PMU is suitable to event‐driven or low‐voltage applications. [ABSTRACT FROM AUTHOR]

In digital phase‐locked loops (PLLs), the finite resolution of digital representation (quantisation) could pose problems, including jitter peaking and limit‐cycle behaviour; both could ruin the frequency stability of a PLL. The resolution of the digitally controlled oscillator (DCO) in the PLL is limited by the smallest dimension available in a given process technology. Currently, one resorts to exhaustive time‐domain simulations to ensure correct operation of a PLL. Using a behavioural model of a PLL as verification, how to choose the DCO resolution without resorting to time‐domain simulations is investigated. The conditions on signal statistics for correct behaviour are repeated and the analysis to estimate the required resolution is provided. As it turns out, the root‐mean‐square value of the frequency deviation – neglecting quantisation – is the coarsest possible DCO resolution. One can estimate this value accurately by the integration of its power‐spectral density, derived from the well‐known phase‐domain model of a PLL. [ABSTRACT FROM AUTHOR]

This Letter presents an 8‐bit fractional frequency divider by utilising current‐mode phase interpolator (PI) for digital phase‐locked loops. A novel track‐and‐hold circuitry is proposed between the PI and divide‐by‐2. It can remove the glitches generated by the current‐interpolation structure. This method also relaxes the requirement of the minimum input frequency, while maintaining the same output frequency. The proposed fractional frequency divider is designed and fabricated with a 65‐nm CMOS technology. It dissipates a DC power of 0.8 mW from a 1.2 V supply. The measurement result shows that the fractional frequency divider achieves an uncalibrated in‐band spur of −43 dBc. [ABSTRACT FROM AUTHOR]

Bang‐bang phase‐locked loops (PLLs) are prone to generate unwanted output spur tones and high noise floor. In this reported work, a spur reduction technique based on dithering is compared to an alternative technique which exploits oscillator intrinsic noise. It is shown how the latter, joined to a proper loop design, allows eliminating unwanted spur tones while yielding a lower noise floor. [ABSTRACT FROM AUTHOR]

The power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal. [ABSTRACT FROM AUTHOR]