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With the development of high-density integrated chips, low-k dielectric materials are used in the back end of line (BEOL) to reduce signal delay. However, due to the application of fine-pitch packages with high-hardness copper pillars, BEOL is susceptible to chip package interaction (CPI), which leads to reliability issues such as the delamination of interlayer dielectric (ILD) layers. In order to improve package reliability, the effect of CPI at multi-scale needs to be explored in terms of package integration. In this paper, the stress of BEOL in the flip-chip chip-scale packaging (FCCSP) model during thermal cycling is investigated by using the finite-element-based sub-model approach. A three-dimensional (3D) multi-level finite element model is established based on the FCCSP. The wiring layers were treated by the equivalent homogenization method to ensure high prediction accuracy. The stress distribution of the BEOL around the critical bump was analyzed. The cracking risk of the interface layer of the BEOL was assessed by pre-cracking at a dangerous location. In addition, the effects of the epoxy molding compound (EMC) thickness, polyimide (PI) opening, and coefficient of thermal expansion (CTE) of the underfill on cracking were investigated. The simulation results show that the first principal stress of BEOL is higher at high-temperature moments than at low-temperature moments, and mainly concentrated near the PI opening. Compared with the oxide layer, the low-k layer has a higher risk of cracking. A smaller EMC thickness, lower CTE of the underfill, and larger PI opening help to reduce the risk of cracking in the BEOL. [ABSTRACT FROM AUTHOR]

With the advancement of high-integration and high-density interconnection in chip manufacturing and packaging, Cu bumping technology in wafer- and panel- level packaging is developed to micrometer-sized structures and pitches to accommodate increased I/O numbers on high-end integrated circuits. Driven by this industrial demand, significant efforts have been dedicated to Cu electroplating techniques for improved pillar shape control and solder joint reliability, which substantially depend on additive formulations and electroplating parameters that regulate the growth morphology, crystal structure, and impurity incorporation in the process of electrodeposition. It is necessary to investigate the effect of an additive on Cu pillar electrodeposition, and to explore the Kirkendall voids formed during the reflowing process, which may result from the additive-induced impurity in the electrodeposited Cu pillars. In this work, a self-synthesized polyquaterntum (PQ) was made out with dual suppressor and leveler effects, and was combined with prototypical accelerator bis- (sodium sulfopropyl)-disulfide (SPS) for patterned Cu pillar electroplating. Then, Sn96.5/Ag3.0/Cu0.5 (SAC305) solder paste were screen printed on electroplated Cu pillars and undergo reflow soldering. Kirkendall voids formed at the joint interfaces were observed and quantified by SEM. Finally, XRD, and EBSD were employed to characterize the microstructure under varying conditions. The results indicate that PQ exhibits significant suppressive and levelled properties with the new structure of both leveler and suppressor. However, its effectiveness is dependent on liquid convection. PQ and SPS work synergistically, influencing the polarization effect in various convective environments. Consequently, uneven adsorption occurs on the surface of the Cu pillars, which results in more Kirkendall voids at the corners than at the center along the Cu pillar surface. [ABSTRACT FROM AUTHOR]

Currently, the high-speed performance of thin-film lithium niobate electro-optic modulator chips is evolving rapidly. Nevertheless, due to the inherent technical limitations imposed by the packaging design and material architecture, the intrinsic electro-optic bandwidth of thin-film lithium niobate electro-optic modulator chips often exceeds the bandwidth of their packaging interfaces, which can constrain the realization of modulation performance. Bump bonding emerges as a high-bandwidth EO interconnection technology, outperforming wire bonding for faster optical communication. In this paper, we present a high-speed thin-film lithium niobate modulator chip tailored for concave–convex bonding, alongside an analysis and design of the chip's flip-chip bonding packaging. By exploiting the superior electrical characteristics of concave–convex bonding, we effectively mitigate the radio frequency losses of modulator chip and packaging. The simulated half-wave voltage (Vπ) of 3.5 V and E-O modulation bandwidth greater than 150 GHz is obtained for a 0.5 cm long modulator after flip-chip bonding packaging. [ABSTRACT FROM AUTHOR]

The article explores the roadmap to neuromorphic computing with a focus on emerging technologies, challenges, and potential solutions in the field. It discusses the significance of materials engineering, various approaches to neuromorphic research, and the importance of balancing performance with sustainability. The text also delves into the potential of 2D-LMs in mimicking synapses and neurons in artificial neural networks, highlighting the stable resistive switching observed in certain materials. Efforts are ongoing to address challenges and further advance the use of 2D-LMs in neuromorphic computing, offering promising solutions to computational challenges faced by traditional digital computers. [Extracted from the article]

The demand for high-performance electromechanical resonators is ever-growing across diverse applications, ranging from sensing and time-keeping to advanced communication devices. Among the electromechanical materials being explored, thin-film lithium niobate stands out due to its strong piezoelectric properties and low acoustic loss. However, in nearly all existing lithium niobate electromechanical devices, the configuration is such that the electrodes are in direct contact with the mechanical resonator. This configuration introduces an undesirable mass-loading effect, producing spurious modes and additional damping. Here, we present an electromechanical platform that mitigates this challenge by leveraging a flip-chip bonding technique to separate the electrodes from the mechanical resonator. By offloading the electrodes from the resonator, our approach yields a substantial increase in the quality factor of these resonators, paving the way for enhanced performance and reliability for their device applications. [ABSTRACT FROM AUTHOR]

Hydraulic technology with smaller sizes and higher reliability trends, including fault prediction and intelligent control, requires high-performance temperature and pressure-integrated sensors. Current designs rely on planar wafer- or chip-level integration, which is limited by pressure range, chip size, and low reliability. We propose a small-size temperature/high-pressure integrated sensor via the flip-chip technique. The pressure and temperature units are arranged vertically, and the sensing signals of the two units are integrated into one plane through silicon vias and gold–gold bonding, reducing the lateral size and improving the efficiency of signal transmission. The flip-chip technique ensures a reliable electrical connection. A square diaphragm with rounded corners is designed and optimised with simulation to sense high pressure based on the piezoresistive effect. The temperature sensing unit with a thin-film platinum resistor measures temperature and provides back-end high-precision compensation, which will improve the precision of the pressure unit. The integrated chip is fabricated by MEMS technology and packaged to fabricate the extremely small integrated sensor. The integrated sensor is characterised, and the pressure sensor exhibits a sensitivity and sensitivity drift of 7.97 mV/MPa and −0.19% FS in the range of 0–20 MPa and −40 to 120 °C. The linearity, hysteresis, repeatability, accuracy, basic error, and zero-time drift are 0.16% FS, 0.04% FS, 0.06% FS, 0.18% FS, ±0.23% FS and 0.04% FS, respectively. The measurement error of the temperature sensor and temperature coefficient of resistance is less than ±1 °C and 3142.997 ppm/°C, respectively. The integrated sensor has broad applicability in fault diagnosis and safety monitoring of high-end equipment such as automobile detection, industrial equipment, and oil drilling platforms. [ABSTRACT FROM AUTHOR]

We discuss the flip-chip mounting process of photodiodes and fiber sleeves on silicon substrates to meet the increasing demand for fabrication of highly integrated and hybrid quantum circuits for operation at cryogenic temperatures. To further increase the yield and success rate of the flip-chip procedure, the size of the gold stud bumps, and flip-chip parameters were optimized. Moreover, to connect optical fibers to the photodiodes in an optimal position, the fiber sleeves were aligned with specially fabricated alignment circles before applying thermocompression with the flip-chip machine. The mounted photodiodes were tested at both room temperature and cryogenic temperature, and we find that mechanical imperfections of the sleeve-ferrule combination limit the overall alignment accuracy. The experimental results show that our flip-chip process is very reliable and promising for various optical and electrical applications and, thus, paves the way for fabrication of hybrid chips, multi-chip modules and chip-on-chip solutions, which are operated at cryogenic temperatures.

Bonding distance is defined by the projected distance on a substrate plane between two solder points of a bonding wire, which can directly affect the morphology of the bonding wire and the performance between internal components of the chip. For the inspection of the bonding distance, it is necessary to accurately recognize gold wires and solder points within the complex imagery of the chip. However, bonding wires at arbitrary angles and small-sized solder points are densely distributed across the complex background of bonding images. These characteristics pose challenges for conventional image detection and deep learning methods to effectively recognize and measure the bonding distances. In this paper, we present a novel method to measure bonding distance using a hierarchical measurement structure. First, we employ an image acquisition device to capture surface images of integrated circuits and use multi-layer convolution to coarsely locate the bonding region and remove redundant background. Second, we apply a multi-branch wire bonding inspection network for detecting bonding spots and segmenting gold wire. This network includes a fine location branch that utilizes low-level features to enhance detection accuracy for small bonding spots and a gold wire segmentation branch that incorporates an edge branch to effectively extract edge information. Finally, we use the bonding distance measurement module to develop four types of gold wire distribution models for bonding spot matching. Together, these modules create a fully automated method for measuring bonding distances in integrated circuits. The effectiveness of the proposed modules and overall framework has been validated through comprehensive experiments. [ABSTRACT FROM AUTHOR]

A novel hybrid bandpass filter (BPF) with wideband and high selectivity is proposed in this paper. The hybrid BPF is composed of two film bulk acoustic resonator (FBAR) cells and three lumped component resonators realized by the integrated passive device (IPD) technology. The ABCD matrix to S-parameters matrix method is used to calculate the frequency response of the BPF. Moreover, the expressions of transmission zeros (TZs) have been extracted. In the design process, an iterative design approach is proposed to improve the circuit and layout of the hybrid filter based on the packaged acoustic-electric hybrid simulation effect. Finally, two parts of the filter are packaged based on the flip-chip method, and two prototypes for the BPF are measured. The measured results of two chips with 3 dB fractional bandwidth of 13.7% and 15.8% are designed and fabricated, which verifies the validity of the proposed design principle. [ABSTRACT FROM AUTHOR]

In this work, Sn-0.7Cu-WO3 nanomodified solders were electrodeposited from an aqueous acidic plating bath containing various fractions of WO3 nanoparticles (0.1, 0.25, 0.5 wt%) NPs for mini-light emitting diodes (mini-LEDs) packaging. The produced nanomodified solders were characterized for their morphology, microhardness, melting point, and electrical resistivity. Further, the nanomodified solder bumps were used to mount a 1608 mini-LED chip/ENIG (Electroless Nickel Immersion Gold) pad by reflowing at 240 °C in the air. High-temperature aging was done at 125 °C for 144, 256, and 400 h and joint shear tests were performed to examine the interfacial properties and growth kinetics of the soldered mini-LED/Sn-0.7Cu-WO3/ENIG joints. The results indicated the formation of (Ni,Cu)3Sn4 intermetallic compounds (IMCs) across the solder/ ENIG pad joint. The thickness of the IMC layer decreases showing the maximum rate of decrease when the composition is Sn-0.7Cu-0.25WO3. It was concluded that the optimal set of microstructure, melting point, electrical resistivity, and joint shear reliability could be achieved when the nanomodified solder is reinforced with 0.25 wt.% WO3 NPs into Sn-0.7Cu matrix and thus it can be a potential contestant for the upcoming applications in mini-LED packaging. [ABSTRACT FROM AUTHOR]

Recent years have witnessed significant advancements in deep learning-based 3D object detection, leading to its widespread adoption in numerous applications. As 3D object detectors become increasingly crucial for security-critical tasks, it is imperative to understand their robustness against adversarial attacks. This paper presents the first comprehensive evaluation and analysis of the robustness of LiDAR-based 3D detectors under adversarial attacks. Specifically, we extend three distinct adversarial attacks to the 3D object detection task, benchmarking the robustness of state-of-the-art LiDAR-based 3D object detectors against attacks on the KITTI and Waymo datasets. We further analyze the relationship between robustness and detector properties. Additionally, we explore the transferability of cross-model, cross-task, and cross-data attacks. Thorough experiments on defensive strategies for 3D detectors are conducted, demonstrating that simple transformations like flipping provide little help in improving robustness when the applied transformation strategy is exposed to attackers. Finally, we propose balanced adversarial focal training, based on conventional adversarial training, to strike a balance between accuracy and robustness. Our findings will facilitate investigations into understanding and defending against adversarial attacks on LiDAR-based 3D object detectors, thus advancing the field. The source code is publicly available at https://github.com/Eaphan/Robust3DOD. [ABSTRACT FROM AUTHOR]

This article investigates the failure mode and mechanism of copper pillar solder joints in temperature cycling experiments, focusing on a Cu/nano Ag/Cu solder joint structure. The hot pressing bonding condition at 300 °C with insulation for 10 s is chosen for the experiments. Based on the life test results, the thermal cycling fatigue life of the nanosilver solder joint is determined to be 2050 cycles. To gain further insights, finite element software ANSYS is employed to simulate nanosilver solder joints in flip chips, revealing the stress–strain distribution within the solder joints. The simulation utilizes the Anand viscoplastic constitutive model for the solder joint, providing a reasonable representation of the stress–strain behavior under thermal cycling load. Notably, the simulation highlights that the maximum stress and strain occur in the contact area between the solder joint and the copper column. To enhance accuracy, the calculation equation is refined using relevant experience, resulting in a prediction of the thermal fatigue life of nanosilver solder joints. This prediction aligns closely with the experimental results. The research outcomes not only contribute valuable insights into the behavior of nanosilver solder but also serve as a reference for its application in electronic packaging. [ABSTRACT FROM AUTHOR]

In the DC-6 GHz band, low-insertion-loss packaging materials were investigated to effectively reduce the heat generated during the working process of the attenuation chip. Based on the working principle of the attenuation chip, when the signal passes through the attenuation chip resistor network, it results in energy loss. This means that the insertion loss of the chip generates heat, which leads to an uneven heat dissipation of the chip and thus functional failure. The microwave characteristics of the packaged joints were investigated using different packaging techniques. The results show that the S21 and S11 of the attenuation chip after nano-silver and Au80Sn20 packaging are optimal in the frequency band of DC-6 GHz, and the insertion loss is low compared with the commonly used packaging materials Sn60Pb40 and Sn96.5Ag3.5, which reduces the heat loss and improves the reliability of the attenuation chip packaging. [ABSTRACT FROM AUTHOR]

A new type of copper (Cu)‑rhodium (Rh)‑alloy, Cu(Rh), films is developed by co‑sputtering copper and rhodium onto silicon (Si) substrates under an argon (Ar) atmosphere. The new films are next annealed at 600 and 670 °C, or alternatively at 100 and 450 °C, for 1 h. Longer annealing to the films, for up to 8 days, is also conducted to explore resistivity variation. The resistivity of the new 300‑nm‑thick film is 2.19 μΩ cm after annealing at 670 °C for 1 h and drifts to 2.26 and 2.14 μΩ after annealing at 400 and 450 °C, respectively, for 200 h. A 2.7‑μm‑thick Sn layer is then thermally evaporated atop the new film for stable flip‑chip solder joints; their metal and Cu‑Sn intermetallic compound (IMC) growth processes vs. various annealing periods are tested. After annealing at 670 °C, the new 300‑nm‑thick film’s adhesive strength reaches 44.2 ± 0.01 MPa, which is 11 ~ 12‑fold that of their pure Cu counterpart. Some key test results of the new film are disclosed herein, including its X‑ray diffraction (XRD) patterns, transmission electron microscopy (TEM) images, secondary‑ion mass spectrometry (SIMS), time‑dependent dielectric‑breakdown (TDDB) lifetime curves, and adhesive strength. The new film’s antibacterial efficacy arrives at an antibacterial ratio of approximately 100% against Staphylococcus aureus (S. aureus) BCRC 10451 for the 300‑nm‑thick film and approximately 99.82% for the 8 nm film, far superior to that of a pure Cu film, which is 0 with the same annealing temperature range. The new film, hence, seems to be a remarkable candidate material for various industrial applications, such as ultra‑large‑scale integrated circuits (ULSIC), micro‑electronic circuits, printed circuits, flip‑chip technology, medical care concerning antibacteria, and the like. [ABSTRACT FROM AUTHOR]

With the advancement of Moore's Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device's failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging. [ABSTRACT FROM AUTHOR]

Despite significant progress made over the past decade in thermally activated delayed fluorescence (TADF) molecules as a material paradigm for enhancing the performance of organic light-emitting diodes, the underlying spin-flip mechanism in these charge-transfer (CT)-type molecular systems remains an enigma, even since its initial report in 2012. While the initial and final electronic states involved in spin-flip between the lowest singlet and lowest triplet excited states are well understood, the exact dynamic processes and the role of intermediate high-lying triplet (T) states are still not fully comprehended. In this context, we propose a comprehensive model to describe the spin-flip processes applicable for a typical CT-type molecule, revealing the origin of the high-lying T state in a partial molecular framework in CT-type molecules. This work provides experimental and theoretical insights into the understanding of intersystem crossing for CT-type molecules, facilitating more precise control over spin-flip rates and thus advancing toward developing the next-generation platform for purely organic luminescent candidates. Kim et al. propose a model for the complex spin-flip process in charge-transfer-type thermally activated delayed fluorescence molecules, uncovering the origin of the high-lying triplet state, addressing a pressing issue discussed over the last decade. [ABSTRACT FROM AUTHOR]

This paper aims to develop a thermal fluid–structure interaction (FSI) methodology to study the effect of different Cu pillar bump diameters on thermal and mechanical performance during the reflow soldering process. The desktop reflow oven is modeled in ANSYS FLUENT, while the ball grid array (BGA) package assembly is modeled in ANSYS STATIC STRUCTURAL. The accuracy of the simulated reflow temperature profile has been verified by comparing it with the experimental temperature data, according to JEDEC standards. The temperature distributions of solder and Cu pillar bumps are compared. A parametric study has been conducted to analyze the effect of different Cu pillar diameters on the reflow soldering process. By coupling the thermal loads with the structural analysis using thermal FSI, Cu pillar bumps with a diameter of 0.20 mm are found to exhibit the lowest reflow temperature, minimum temperature difference, and minimum deformation and thermal stress, making them the most suitable interconnection joints for flip chip technology. The study also examines the effect of soldering materials on the Cu pillar bump. The findings of this research provide valuable insights into the effects of varying Cu pillar diameters on the reflow soldering process, which can help in the development of more reliable electronic assemblies. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of various copper (Cu) pillar bump heights on temperature distribution, deformation and thermal stress during reflow. The virtual reflow oven environment was simulated using the fluid domain of the oven model. The accuracy of the fluid analysis was verified by comparing the obtained results with experimental data, which was conducted based on the Joint Electron Device Engineering Council (JEDEC) Standard. In addition, a grid independence test was carried out on the fluid mesh to determine the optimal mesh size for the simulations. A thermal fluid–structure interaction (FSI) approach was employed to couple the thermal results from the fluid analysis with the solid assembly. The results of the coupling analysis revealed that Cu pillar bumps with a height of 0.09 mm exhibited the lowest reflow temperature, minimal maximum deformation, and thermal stress, indicating that it is the optimal potential height for forming a good joint. The study also examines the impact of soldering materials, such as tin-bismuth (SnBi) and tin-silver-copper solder alloys (SAC305 and SAC405), on the Cu pillar bump. This study enables a comprehensive analysis of the thermal and mechanical performance of different Cu pillar bump parameters during the reflow process. [ABSTRACT FROM AUTHOR]

In this study, we have fabricated a 368 nm LED with an epitaxial Indium Tin Oxide (ITO) contact layer. We analyze the thermal performance of the flip-chip LED with a symmetric electrode and metal reflective layer, applying ANSYS to build a coupled electro-thermal finite element model (FEM) of the temperature distribution in the multiple quantum wells (MQWs). We compare our system with the traditional Au-bump flip-chip LED and a flip-chip LED with a Distributed Bragg Reflector (DBR) layer. The simulation results have shown that the flip-chip LED with a metal reflective layer and symmetric electrode exhibits better heat dissipation performance, particularly at high input power. The influence of the insulating layer on the LED chip junction temperature is also examined. The simulation data establish an effect due to the thermal conductivity of the insulating layer in terms of heat dissipation, but this effect is negligible at an insulation layer thickness ≤1 µm. [ABSTRACT FROM AUTHOR]

The luminous characteristics of flip-chip type high-voltage (HV) blue mini-light-emitting diodes (LEDs), which consist of three serially connected sub-mesas, have been investigated for the first time. The cryogenic electroluminescence below 100 K partially originates from localized excitons. As the driving current reaches 1 μA, the contributions of Shockley–Read–Hall nonradiative recombination and radiative recombination exhibit a remarkably inverse temperature dependence, while the contributions of Auger recombination and carrier leakage are relatively negligible. The mesa corresponding to the anode of the HV blue mini-LED exhibits the lowest temperature among the three sub-mesas due to its smaller thermal resistance. To minimize the temperature-induced shift in chromaticity coordinates, it is necessary to adjust the driving current based on the operating temperature. [ABSTRACT FROM AUTHOR]

In this study, a novel flip-fold removal model was established to reveal the ductile–brittle mixed removal phenomenon in the grinding process of glass-ceramics. This flip-fold model proposed for the ductile–brittle mixed removal mode differs from conventional brittle or ductile removal mechanisms. Using the theoretical exploration method, a theoretical model of flip-fold removal is established based on the analysis of different scenarios of the relationship between the depth of the stagnation region and pile-up height of the interference zone. Through an experimental verification method, the approach of crossing double scratches with a continuously variable scratch distance is proposed to observe the evolution progression and verify the flip-fold removal model. Using the analytical analysis method, the amplitude and direction cosine distributions of the interference stress field were analysed to reveal the internal mechanism of the flip-fold removal model. The results of the three scientific research methods were in good agreement with those of the proposed model. The flip-fold material removal model supports the comprehension of the ductile–brittle mixed removal mode during the grinding of hard-brittle materials. This model provides an approach to controlling the material removal mode from the perspective of regulating the flip-fold behaviour by adjusting the scratch distance. [ABSTRACT FROM AUTHOR]

Gallium oxide (Ga2O3) devices have shown remarkable potential for high-voltage, high-power, and low-loss power applications. However, thermal management of packaging for Ga2O3 devices becomes challenging due to the significant self-heating effect. In this paper, an advanced double-sided cooling flip-chip packaging structure for Ga2O3 devices was proposed and the overall packaging of Ga2O3 chips was researched by simulation in detail. The advanced double-sided cooling flip-chip packaging structure was formed by adding a layer of diamond material on top of the device based on the single-sided flip-chip structure. With a power density of 3.2 W/mm, it was observed that the maximum temperature of the Ga2O3 chip with the advanced double-sided cooling flip-chip packaging structure was 103 °C. Compared with traditional wire bonding packaging and single-sided cooling flip-chip packaging, the maximum temperature was reduced by about 12 °C and 7 °C, respectively. When the maximum temperature of the chip was controlled at 200 °C, the Ga2O3 chip with double-sided cooling packaging could reach a power density of 6.8 W/mm. Finally, by equipping the top of the package with additional water-cooling equipment, the maximum temperature was reduced to 186 °C. These findings highlight the effectiveness of the proposed flip-chip design with double-sided cooling in enhancing the heat dissipation capability of Ga2O3 chips, suggesting promising prospects for this advanced packaging structure. [ABSTRACT FROM AUTHOR]

ChemElectroChem is celebrating its 10-year anniversary as a trusted forum for the electrochemistry community worldwide. The journal has undergone various changes, including rebranding, the introduction of special collections, and the transition to a fully open access publishing model. It has published 192 issues covering a wide range of topics in electrochemistry and has received recognition for its contributions to the field. ChemElectroChem aims to continue publishing excellent electrochemistry content and engaging with the scientific community in the future. [Extracted from the article]

This document is an editorial for a special issue of the journal Micromachines focused on advanced interconnect and packaging technologies in the field of electronics. The editorial highlights the importance of these technologies in achieving high performance, miniaturization, and low power consumption in electronic devices. It introduces several research contributions included in the special issue, covering topics such as built-in packaging methods, bonding strength improvement, accurate characterization of interconnects, signal and power integrity analyses, crosstalk reduction, and reliability issues. The editorial acknowledges the challenges that remain in this field and expresses gratitude to the authors, editors, and reviewers involved in the special issue. [Extracted from the article]

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency. [ABSTRACT FROM AUTHOR]

Laminate substrates in advanced IC packages serve as not only the principal heat dissipation pathway but also the critical component governing the thermomechanical performance of advanced packaging technologies. A solid and profound grasp of their thermomechanical properties is of crucial importance to better understand IC packages' thermomechanical behavior. This study attempts to introduce a subregion homogenization modeling framework for effectively and efficiently modeling and characterizing the equivalent thermomechanical behavior of large-scale and high-density laminate substrates comprising the non-uniform distribution and non-unidirectional orientation of tiny metal traces. This framework incorporates subregion modeling, trace mapping and modeling, and finite element analysis (FEA)-based effective modeling. In addition, the laminates are macroscopically described as elastic orthotropic or elastic anisotropic material. This framework is first validated with simple uniaxial tensile and thermomechanical test simulations, and the calculation results associated with these two effective material models are compared with each other, as well as with those of two existing mixture models, and direct the detailed FEA. This framework is further tested on the prediction of the process-induced warpage of a flip chip chip-scale package, and the results are compared against the measurement data and the results of the whole-domain modeling-based effective approach and two existing mixture models. [ABSTRACT FROM AUTHOR]

Flip chip bonding technology on gold–tin (Au-Sn) microbumps for MEMS (Micro Electro Mechanical Systems) and 3D packaging is becoming increasingly important in the electronics industry. The main advantages of Au-Sn microbumps are a low electrical resistance, high electrical reliability, and fine pitch. However, the bonding temperature is relatively high, and the forming mechanism of an intermetallic compound (IMC) is complicated. In this study, Au-Sn solid-state diffusion (SSD) bonding is performed using the thermal gradient bonding (TGB) method, which lowers bonding temperature and gains high bonding strength in a short time. Firstly, Au-Sn microbumps with a low roughness are prepared by using an optimized process. Then, Au-Sn bonding parameters including bonding temperature, bonding time, and bonding pressure are optimized to obtain a higher bonding quality. The shear strength of 23.898 MPa is obtained when bonding in the HCOOH environment for 10 min at the gradient temperature of 150 °C/250 °C with a bonding pressure of more than 10 MPa. The IMC of Au-Sn is found to be Au-Sn and Au5Sn. The effect of annealing time on the IMC is also investigated. More and more Au5Sn is generated with an increase in annealing time, and Au5Sn is formed after Sn is depleted. Finally, the effect of annealing time on the IMC is verified by using finite element simulation, and the bonding strength of IMC was found to be higher when the bonding temperature is 150 °C at the cold side and 250 °C at the hot side. The temperature in the bonding area can reach 200 °C, which proves that the Au-Sn bonding process is solid-state diffusion because the temperature gradient reaches 2500 °C/cm. [ABSTRACT FROM AUTHOR]

This article presents the significance of using different sizes and positions of IC (Integrated Circuit) chips that are mounted on substrates of different materials. 1631The ICs are cooled by forced convection in a horizontal wind tunnel. COMSOL Multiphysics 5.4 solve the IC chip cooling problem by selecting a conjugate heat transfer module with laminar flow. FR4, ba-kelite, single and multi-layer copper clad boards are used as substrate materials. Numerical simulations are performed for FR4, bakelite with a constant heat flux of 5000 W/m², at 2.5 m/s air velocity. In contrast, single and multi-layer copper clad boards are studied for 10000 W/m² with 1.5 m/s air velocity. The prime objective of this research is to use adequate size and placement of chips generating high heat fluxes for enhanced heat transfer. Results showed that larger chips placed at bottom rows and sequentially decreasing sizes in the subsequent rows for the same overall input for high substrate thermal conductivity give more heat dissipation. Among all configurations A0 - F considered in the study, case E provides minimum tempera-ture using single and multi-layer copper clad boards. In addition to modification of chip sizes, geometric spacing of X1/X2 = 1.8 results in lower maximum temperature. [ABSTRACT FROM AUTHOR]

Semiconductor chips on a substrate have a wide range of applications in electronic devices. However, environmental temperature changes may cause mechanical buckling of the chips, resulting in an urgent demand to develop analytical models to study this issue with high efficiency and accuracy such that safety designs can be sought. In this paper, the thermal buckling of chips on a substrate is considered as that of plates on a Winkler elastic foundation and is studied by the symplectic superposition method (SSM) within the symplectic space-based Hamiltonian system. The solution procedure starts by converting the original problem into two subproblems, which are solved by using the separation of variables and the symplectic eigenvector expansion. Through the equivalence between the original problem and the superposition of subproblems, the final analytical thermal buckling solutions are obtained. The SSM does not require any assumptions of solution forms, which is a distinctive advantage compared with traditional analytical methods. Comprehensive numerical results by the SSM for both buckling temperatures and mode shapes are presented and are well validated through comparison with those using the finite element method. With the solutions obtained, the effects of the moduli of elastic foundations and geometric parameters on critical buckling temperatures and buckling mode shapes are investigated. [ABSTRACT FROM AUTHOR]

In this theoretical study, we explore the use of quantum code-based memories to enhance the lifetime of qubits and exceed the break-even point, which is critical for the implementation of fault-tolerant quantum computing. Specifically, we investigate the quantum phase-flip repetition code as a quantum memory and theoretically demonstrate that it can preserve arbitrary quantum information longer than the lifetime of a single idle qubit in a dephasing-time-limited system, e.g. in semiconductor qubits. Our circuit-based analytical calculations show the efficiency of the phase-flip code as a quantum memory in the presence of relaxation, dephasing, and faulty quantum gates. Moreover, we identify the optimal repetition number of quantum error correction cycles required to reach the break-even point by considering the gate error probabilities of current platforms for quantum computing. Our results provide guidelines for developing quantum memories in semiconductor quantum devices. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the residual stress of different components of the crystal structures of electronic device materials following exposure to elevated temperatures using a combination of experimental tests and finite element simulations. X-ray diffraction (XRD) and LXRD micro-area residual stress analyzer were employed to determine the residual strain and stress of the CBGA sample encapsulation cover and solder joints. Subsequently, the experimental data were utilized to verify the accuracy of the simulation. The discrepancy between experimental measurements and simulation outcomes of the residual stress following reflow soldering of CBGA-assembled micro-solder joints is below 14%. The analysis also included thermal warping deformation of the CBGA encapsulation cover and how the residual stress was influenced by the diameter, spacing, and height of the solder joints. The study reveals that the residual stress following reflow soldering of BGA solder joints is non-uniformly distributed within the array. Within a single solder joint, residual stress gradually increases in distribution from its middle to the point where it make contact with the PCB and chip, with the highest level of residual stress observed where the solder joint contacts the chip. The variation in material parameters, such as the coefficient of thermal expansion, is the primary cause of thermal warping deformation on the surface of CBGA encapsulation covers. Three primary factors significantly impact the residual stress on BGA solder joints: solder joint diameter, spacing, and height. The maximum value is inversely proportional to the height of the solder joints and the residual stress. Conversely, the diameter and spacing of the joints are positively proportional to the highest value. When the diameter of the solder joint is increased from 0.55 mm to 0.75 mm, the maximum residual stress in the BGA solder joint increases from 37.243 MPa to 36.835 MPa. Conversely, increasing the height of the solder joint from 0.36 mm to 0.44 mm reduces the stress from 39.776 MPa to 36.835 MPa. [ABSTRACT FROM AUTHOR]

To bond a semiconductor power chip on a substrate using the formation of bondlines exhibiting long-term mechanical durability at high temperatures such as 300 °C, compression-assisted sinter bonding between Cu finishes was carried out at 300–350 °C in air. Cu flakes of approximately 7 µm were used as the main filler material; their surfaces were modified by pretreatment using a formic acid solution, and the existing oxide layers were transformed into copper formate shells. To increase the amount of the copper formate shells, the shell transformation reaction was controlled by the deliberate addition of 30 nm Cu2O particles and sustained for 50 min. The formate shells formed decomposed at a peak temperature of 250 °C, forming pure Cu, which rapidly induced sintering between the flakes and at the Cu-finish–flake interfaces. Therefore, the paste containing Cu flakes showed a sufficient shear strength of 26.3 MPa even in air after sinter bonding for only 3 min under 5 MPa at 350 °C. Although the bimodal-type paste presented near-full-density bondline structures within 3 min of adding 350 nm pure Cu particles, the strengths with respect to bonding time showed trends of values less than 26.3 MPa, owing to the excessive oxidation of the 350 nm Cu. [ABSTRACT FROM AUTHOR]

With the rapid advancement of next-generation communication technology, traditional Quad Flat No-leads (QFN) packaging is facing challenges to meet functional requirements. Due to its high integration and excellent thermal performance, the Multi-chips Module combined with Quad Flat No-leads (MCM-QFN) packaging is gaining popularity. However, the structural complexity of MCM-QFN packaging and the thermal coupling effect between multiple dies make it challenging to analyze the steady-state thermal distribution of MCM-QFN packaging, which is necessary for assessing the reliability and optimizing the layout design of the multi-chips module. By analyzing the heat dissipation path from each die to the ambient, this paper proposes an analytical thermal resistance network model for calculating each mean die temperature of MCM-QFN packaging. The thermal coupling effect among the multi-chips, the thermal spreading resistance between critical layers, and the boundary conditions and cooling conditions are all considered. All thermal resistances in the model are expressed analytically, and the mean temperature of each chip can be calculated within 0.1 s using MATLAB programming. To validate the accuracy of the proposed model, finite element method (FEM) simulations are conducted to provide a reference for the mean temperature of each chip under four sets of thermal conditions. The data comparison demonstrates that the analytical model is fast and accurate in calculating each mean die temperature of MCM-QFN packaging, with a maximum error of 3.72%, and the calculation speed increased by about 600× compared to that of FEM simulation. Furthermore, the analytical model is able to offer a direction for optimizing the layout design and material selection of MCM-QFN packaging. [ABSTRACT FROM AUTHOR]

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This paper discusses improved design of two-dimensional (2D) arrays, potentially pushing the present state of the art of the high-Tc (and low-Tc) magnetic field detectors to a larger scale, i.e., higher sensitivity. We propose a two-plate geometry for parallel (and two-dimensional) arrays of Josephson junctions (JJs) for application in magnetic field detection. The arrays can be realized either by integration in the same substrate with a multilayer technology or on two different substrates. In the latter case, the substrates can be assembled in a flip-chip or piggyback configuration. A suggestion would be to divide a 2D array in two (equal) parts and to distribute each part on a different layer, one above the other. We model the current distribution in arrays connected in series so that the bias current flowing through the device flows in opposite direction in the layers. We demonstrate that this geometry greatly improves the uniformity of the bias current distribution across the width of the array, thereby restoring the critical current and, in principle, improving the Josephson array response. From the model, we conclude that the alignment of the arrays is not critical and that the realization of the devices requires only conventional techniques. [ABSTRACT FROM AUTHOR]

The article presents a study which proposed a controllable in situ electric field-activated doping method to construct lateral p-n junctions in the short-wave infrared (SWIR) mercury telluride (HgTe) colloidal quantum dot (CQD)-based photodetectors with a simple planar configuration. Topics discussed include planar p-n junction focal play array (FPA) imagers, SWIR imaging using FPA imagers, and device fabrication and characterization.

In this work, rapid failure of a few minutes was observed in real ball grid array solder joints under high current density (8 × 103 and 1 × 104 A cm−2) at room temperature. For each test condition, the failure solder joint was detected at the same position of the daisy chain by computed tomography technology. Furthermore, the open failure for all solder joints was caused by the chip side (anode side) Cu dissolution. Microstructure evolution for a pair of electrically connected solder joints was investigated. In both solder joints, Cu atoms on the chip side were dissolved to the board side with the formation of intermetallic compound particles in solder matrix. Finite element simulation was introduced to calculate the current density, temperature, and heat flux distribution. The temperature gradient along the direction of Cu migration in solder joint was developed due to the accumulation of Joule heating. Thermomigration was confirmed as the dominant mechanism of chip side Cu dissolution. [ABSTRACT FROM AUTHOR]

Scanning acoustic microscopy (SAM) technique has been applied to defect inspection in electronic devices. With the increase of packaging density, detection of the micro-defects in high density devices becomes more and more challenging. The SAM test is suffering from sacrificing the spatial resolution to reach a certain penetration depth of the ultrasonic waves. So it is necessary to enhance the resolution level of the SAM image. In this paper, a wavelet based resolution enhancement technique was investigated to reconstruct a high quality image for SAM test of the flip chip packages. The stationary wavelet transform was adopted to decompose the captured SAM image into four frequency subbands, and the high frequency subbands were enhanced by adding the difference matrix in the intermediate stage, and a super resolution SAM image was derived from combining all the subbands by using the Inverse Discrete Wavelet Transform. Then the solder joints segmented from the SR-SAM image were classified by using the SVM algorithm. The results validated that the proposed technique is effective to improve the detection accuracy of SAM test. • An intelligent system is developed to inspect the solder joints of flip chip. • The SAM image is decomposed into four different frequency components. • High resolution SAM image is reconstructed with the wavelet-based method. • The solder joints are segmented from the SR-SAM image. • The SR-SAM image has high accuracy for defect recognition. [ABSTRACT FROM AUTHOR]

Stand-alone microgrids have become reliable and efficient solutions for remote areas and critical infrastructures. However, the converters within these microgrids experience long-term complex power fluctuations caused by random variations in micro sources and loads. These power fluctuations induce thermal cycling in semiconductor chips, leading to thermal fatigue failure and compromising the safety and reliability of both the converter and microgrid operation. To address this issue, this paper proposes a reactive power injection algorithm aimed at reducing the output power fluctuation of the converter. The algorithm implements reactive power injection at the converter control level, thereby restructuring the output power profile and resulting in reduced junction temperature fluctuations in IGBTs. This approach effectively mitigates thermal stress within the material layers of the module, extending the lifetime of power devices and improving the operational reliability of the microgrid. The algorithm implementation is based on the PQ control strategy, integrating the power triangle with the envelope detection technique. Furthermore, the lifetime prediction process utilizes the electro-thermal coupling model, the rainflow counting algorithm, and the Lesit model. Simulation results demonstrate that, for an active power fluctuation range of 10 kW to 80 kW and an equivalent RC time constant of 22.5 s, the algorithm achieves a significant reduction of 62.64% in the amplitude of output power fluctuation and extends the lifetime of power devices by 74.13%. The obtained data showcase the effectiveness of the algorithm in enhancing the lifetime of power devices and further improving the microgrid operational reliability under specific parameter conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a new type of substrate for manufacturing LEDs based on AlInGaN heterostructures. Instead of depositing SiC layers on the surface of Si using the conventional method, a new method involving the coordinated substitution of atoms (MCSA) to form the SiC layer is proposed. This new approach enables the growth of epitaxial GaN layers with low defect content and facilitates transfer to any surface. The paper details the technology of manufacturing LEDs on SiC/Si substrates obtained by the MCSA and elaborates on the benefits of using these substrates in LED production. Additionally, the advantages of the growth interface between SiC and Si materials are discussed. Moreover, it is found that thinner SiC layers (<200 nm) contribute to the scattering of the LED's own radiation in the heterostructure waveguide, which decreases its absorption by silicon. For flip-chip LEDs with the substrate removed, substrates with thicker SiC layers (~400 nm) and a growth porous layer of several microns at the SiC-Si interface is utilized to simplify Si substrate removal and enhance the manufacturing process's cost-effectiveness. [ABSTRACT FROM AUTHOR]

Roll-to-roll (R2R) printing methods are well known as additive, cost-effective, and ecologically friendly mass-production methods for processing functional materials and fabricating devices. However, implementing R2R printing to fabricate sophisticated devices is challenging because of the efficiency of material processing, the alignment, and the vulnerability of the polymeric substrate during printing. Therefore, this study proposes the fabrication process of a hybrid device to solve the problems. The device was created so that four layers, composed of polymer insulating layers and conductive circuit layers, are entirely screen-printed layer by layer onto a roll of polyethylene terephthalate (PET) film to produce the circuit. Registration control methods were presented to deal with the PET substrate during printing, and then solid-state components and sensors were assembled and soldered to the printed circuits of the completed devices. In this way, the quality of the devices could be ensured, and the devices could be massively used for specific purposes. Specifically, a hybrid device for personal environmental monitoring was fabricated in this study. The importance of environmental challenges to human welfare and sustainable development is growing. As a result, environmental monitoring is essential to protect public health and serve as a basis for policymaking. In addition to the fabrication of the monitoring devices, a whole monitoring system was also developed to collect and process the data. Here, the monitored data from the fabricated device were personally collected via a mobile phone and uploaded to a cloud server for additional processing. The information could then be utilized for local or global monitoring purposes, moving one step toward creating tools for big data analysis and forecasting. The successful deployment of this system could be a foundation for creating and developing systems for other prospective uses. [ABSTRACT FROM AUTHOR]

The magnetic properties of permalloy-based trilayers of the form Py0.8Cu0.2/Py0.4Cu0.6/Py/IrMn were studied as the spacer layer undergoes a paramagnetic to ferromagnetic phase transition. We find the coupling between the free Py0.8Cu0.2 layer and the exchange bias pinned Py to be strongly temperature-dependent: there is negligible coupling above the Curie temperature of the Py0.4Cu0.6 spacer layer, strong ferromagnetic coupling below that temperature, and a tunable coupling between these extremes. Polarized neutron reflectometry was used to measure the depth profile of the magnetic order in the system, allowing us to correlate the order parameter with the coupling strength. The thickness dependence shows that these are interface effects with an inverse relationship to thickness, and that there is a magnetic proximity effect that enhances the Curie temperature of the spacer layer with characteristic length scale of about 7 nm. As a demonstration of potential functionality of such a system, the structure is shown to spontaneously flip from the antiparallel to parallel magnetic configuration once the spacer layer has developed long-range magnetic order. [ABSTRACT FROM AUTHOR]

Covalent organic frameworks (COFs) have been attracting intense research due to their permanent porosity, designable architecture, and high stability. However, COFs are challenging to crystallize and their synthesis often results in tiny crystal sizes and low crystallinities, which hinders an unambiguous structure determination. Herein, we demonstrate that the structure of low-crystallinity COF Py-1P nanocrystals can be solved by coupling three-dimensional electron diffraction (3DED) with simulated annealing (SA). The resulting model is comparable to that obtained from high-crystallinity samples by dual-space method. Moreover, for low-resolution 3DED data, the model obtained by SA shows a better framework than those provided by classic direct method, dual-space method, and charge flipping. We further simulate data with different resolutions to understand the reliability of SA under different crystal quality conditions. The successful determination of Py-1P structure by SA compared to other methods provides new knowledge for using 3DED to analyze low-crystallinity and nanosized materials. Covalent organic frameworks have demonstrated promise for a wide variety of applications, but their synthesis often results in materials with low crystallinity that are challenging to characterize. Here, coupling three dimensional electron diffraction with simulated annealing is shown to enable the structural determination of a low crystallinity pyrene-containing covalent organic framework. [ABSTRACT FROM AUTHOR]

With the rapid development of microelectronic interconnection technology, the reliability requirements of electronic products are becoming higher and higher. Among them, temperature has the greatest impact on electronic devices. Due to the different coefficients of thermal expansion (CTE) between the many materials of a chip, the inside of a solder joint is subjected to cyclic temperature action. Under the effect of cyclic temperature, the solder joints are subject to internal fracture resulting in the failure of the solder joint. Therefore, it is necessary to find a more reliable material for the solder joint. In this paper, the advantages and disadvantages of pure silver material and low silver material are compared by finite element simulation analysis of nano-silver pure silver material and SAC305 low silver material, and the fatigue life prediction of nano-silveris predicted by a life prediction model. Then, using the Electric Power Research Institute estimation method to estimate the fatigue life of solder joints, the results are compared with those calculated by the finite element method. [ABSTRACT FROM AUTHOR]

The integrity of solder joints of components in an electronic device is critical to the device reliability. The miniaturisation trend in the development of electronic products has continued to challenge the shear strength of the solder joints in these devices and necessitates implementation of optimal reflow profiles to achieve maximum joint strength. This study proposes an optimal parameter combination of reflow profile factors which demonstrate potential for delivering maximum shear strength of solder joints. The Taguchi design of experiment (DoE) is employed to generate eight orthogonal array designs of L24 reflow profiles. The factors/parameters investigated are preheat gradient, time above liquidus (TAL), peak temperature and cooling rate. Three test vehicles of varying solder joint sizes are made from R1206, R0805 and R0603 resistors. Reflow profile number 3 constituting 1.2°C/s preheat, 45 s TAL, 245°C peak temperature and 60% cooling rate is optimal because it yielded joints with the highest strength and ca. 4 µm intermetallic compound thickness. The solder joint shear strength decreased with a decrease in the size of the lead-free joint irrespective of the reflow profile implemented. These results will be useful for electronic packaging and reliability engineers faced with challenges of improving device operational mechanical performance in the continuing trend of product miniaturisation. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) power devices have many benefits, including high power density, small footprint, high operating voltage, and excellent power gain capability. However, in contrast to silicon carbide (SiC), its performance and reliability can be negatively impacted by its low thermal conductivity, which can cause overheating. Hence, it is necessary to provide a reliable and workable thermal management model. In this paper, a model of a flip-chip packing (FCP) GaN chip was established, and it was assigned to the Ag sinter paste structure. The different solder bumps and under bump metallurgy (UBM) were considered. The results indicated that the FCP GaN chip with underfill was a promising method because it not only reduced the size of the package model but also reduced thermal stress. When the chip was in operation, the thermal stress was about 79 MPa, only 38.77% of the Ag sinter paste structure, lower than any of the GaN chip packaging methods currently in use. Moreover, the thermal condition of the module often has little to do with the material of the UBM. Additionally, nano-silver was found to be the most suitable bump material for FCP GaN chip. Temperature shock experiments were also conducted with different UBM materials when nano-silver was used as bump. It was found that Al as UBM is a more reliable option. [ABSTRACT FROM AUTHOR]

The main motivation of this work was to demonstrate a hollow telescopic rod structure that could be used for minimally invasive surgery. The telescopic rods were fabricated using 3D printing technology to make mold flips. During fabrication, differences in biocompatibility, light transmission, and ultimate displacement were compared between telescopic rods fabricated via different processes, so as to select the appropriate process. To achieve these goals, flexible telescopic rod structures were designed and 3D-printed molds were fabricated using Fused Deposition Modeling (FDM) and Stereolithography (SLA) techniques. The results showed that the three molding processes had no impact on the doping of the PDMS specimens. However, the FDM molding process had lower surface flatness accuracy compared to SLA. The SLA mold flip fabrication exhibited superior surface accuracy and light transmission compared to the other methods. The sacrificial template method and the use of HTL direct demolding technique had no significant impact on cellular activity and biocompatibility, but the mechanical properties of the PDMS specimens were weakened after swelling recovery. The height and radius of the hollow rod were found to have a significant impact on the mechanical properties of the flexible hollow rod. The hyperelastic model was fitted appropriately with the mechanical test results, and the ultimate elongation increased with an increase in hollow–solid ratios under the uniform force. [ABSTRACT FROM AUTHOR]