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The effects of total ionizing dose (TID) on MOSFETs fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology are analyzed. TID causes positive-trapped charge to accumulate in transistor isolation regions [e.g., the buried oxide (BOX)], thereby generating negative TID-induced threshold-voltage shifts $\Delta V_{\mathrm {th}}$ that facilitate nMOSFET turn-on and inhibit pMOSFET turn-on. Back-gate biasing options in the technology can be used to offset the threshold-voltage shifts. Applying a bias to the back gates of MOSFETs in a conventional-well back-gate configuration mitigates TID-induced $\Delta V_{\mathrm {th}}$ in nMOSFETs (where a negative bias is applied to the P-well back-gate), while enhancing the same in pMOSFETs (where a positive bias is applied to the N-well back-gate). To mitigate and potentially reverse TID-induced $\Delta V_{\mathrm {th}}$ of both nMOSFETs and pMOSFETs simultaneously, a single back-gate bias can be applied to MOSFETs in a common isolated P-well back-gate configuration. 3-D technology computer-aided design (3-D TCAD) device simulation results of the 22-nm FD-SOI technology confirm the conventional-well circuit-level radiation response and support the effectiveness of using the common isolated P-well back-gate configuration for TID mitigation. These results justify the utility of dynamically tuning back-gate bias according to actively monitored TID-induced $\Delta V_{\mathrm {th}}$ feedback. [ABSTRACT FROM AUTHOR]

An on-chip measurement circuit that was specifically designed to capture the high-speed transient characteristics of photocurrent is employed to measure total-ionizing-dose (TID)-induced leakage from 10 keV X-rays. This circuit uses a photocurrent-controlled oscillator (PCO) to produce an analog frequency, which provides linearity comparable to traditional, off-chip methods of TID measurement. The circuit was fabricated in a sub-50 nm, fully depleted silicon-on-insulator (FD-SOI) technology. TID-induced leakage currents were measured using the circuit and results were compared to off-chip direct measurements from identical transistor arrays. Additionally, potential in situ applications of this circuit in conjunction with a TID-compensating back-gate biasing technique are explored. [ABSTRACT FROM AUTHOR]

The effects of high-field stress are evaluated for industrial-quality AlGaN/GaN HEMTs as a function of bias and temperature. Positive and negative threshold voltage shifts are observed, depending on stress conditions, indicating the presence of acceptor-like and donor-like traps in these devices. Worst-case transconductance degradation under rated device operating conditions is observed for devices subjected to high-voltage stress in the ON bias condition at elevated temperature. This contrasts with results on earlier-generation devices, which often show worst-case response under semi-ON bias conditions, emphasizing that each technology requires characterization under multiple bias-stress conditions. Neutral and charged oxygen donor-like DX centers and substitutional acceptor-like $\text{N}_{\mathrm{ Ga}}$ centers are the dominant defects contributing to low-frequency noise in these devices. Dehydrogenation of $\text{O}_{\mathrm{ N}}$ -H complexes during ON-bias stress and the resulting increases in densities of $\text{O}_{\mathrm{ N}}$ -related donor-like defects are evidently the reliability-limiting mechanism in these devices. [ABSTRACT FROM AUTHOR]

At the 14-/16-nm FinFET technology node, experimental heavy-ion single-event upset (SEU) cross sections have been obtained for a D flip-flop (DFF) with variation in supply voltage over a wide range of particle linear energy transfer (LET). An empirical model for predicting the SEU cross section as a function of supply voltage based on experimental data has been developed and verified. The results are consistent with low-LET particle irradiation findings from previous works that have indicated a strong exponential increase in SEU cross section with supply voltage scaling for FinFET technologies. Furthermore, this paper reveals the impact of supply voltage variations on a sensitive area for high-LET particle irradiation. The increase in cross section from nominal (0.8 V) to a specific reduced supply voltage for high-LET particle irradiation is constant and has been observed through experimental results across the high-LET particle spectrum. The 3-D TCAD simulations are used to characterize sensitive area affecting high-LET supply voltage-dependent SEU cross sections in the FinFET technology. The developed model will allow circuit designers to predict changes in the SEU cross section due to supply voltage variation for the 14-/16-nm technology node without extensive testing. [ABSTRACT FROM AUTHOR]

A method is presented to enhance single-event transient (SET) measurements by overcoming a common experimental limitation of minimum measurable pulse widths. As technology scales, SETs decrease in width and measurement circuits fundamentally cannot capture every fast transient capable of causing an error. A method has been developed to overcome this limitation by using a latch as a feedback-assisted fast transient capture circuit. Single-event upset (SEU) data are combined with SET data to extend pulsewidth acuity such that pulses faster than the minimum measurable SET pulsewidth are extracted. The method has been applied for a 14-/16-nm bulk FinFET technology node and predictions for logic single-event cross section reveal the impact of fast transients on the radiation response of logic circuits. Results including the extracted fast transients represent upper bound SEU cross sections. For high linear energy transfer (LET) particle irradiation, accounting for fast transients using the developed method results in negligible variation in logic SE cross section. However, for low LET particle irradiation, the method results in an order of magnitude increase in logic SE cross section. [ABSTRACT FROM AUTHOR]

Bulk and silicon-on-insulator (SOI) n-channel FinFETs with fin widths of 15–40 nm and channel lengths of 45 and 1000 nm were irradiated with 1.8 MeV protons at temperatures of 295 and 90 K. Bulk and SOI FinFETs show improved transconductance and steeper subthreshold slopes before irradiation at 90 K than at 295 K. Increased off-state leakage currents are observed for longer channel bulk FinFETs for doses above 300–500 krad (SiO2) for 295 and 90 K irradiation, and at lower doses for shorter channel devices. Threshold-voltage shifts for irradiation up to 1 Mrad(SiO2) are greater for SOI devices at 90 K than at 295 K due to enhanced charge trapping in the buried oxide (BOX). TCAD simulations provide insight into radiation-induced trapped-charge densities in the SOI devices. [ABSTRACT FROM AUTHOR]

Laser-induced single-event transients (SETs) are observed in black phosphorus (BP) MOSFETs. The SETs are relatively small, which is consistent with expectations for thin-film fully depleted transistors. The position dependence and the bias-dependence of the measured SETs in BP transistors are investigated to study the charge collection mechanisms. The peak drain current is maximized when the pulsed-laser strikes at the center of the channel region. The amplitudes of the SETs are also relatively independent of the overdrive voltage. The drain-to-source SET current increases when $\vert \text {V}_{\mathrm {DS}}\vert $ increases, due to a shunt effect. [ABSTRACT FROM AUTHOR]

Total ionizing dose effects are investigated on a physically unclonable function (PUF) based on CMOS breakdown. Devices irradiated to 2 Mrad(SiO2) show less than 11% change in current ratio at 1.2 V. The read-out window of programmed PUFs decreases significantly at high-dose proton irradiation, and then recovers back to the original value after annealing. The proton test results for the pFET selector, the unbroken nFET, and the broken nFET indicate that the threshold-voltage shift of the pFET selector contributes mainly to the degradation of the PUF. [ABSTRACT FROM AUTHOR]

Single-event transient (SET) data for the 14-/16-nm bulk finFET technology generation are presented and analyzed for variations in threshold voltage and number of fins in the transistor. The heavy-ion experimental data over a range of supply voltage allows for a comparison of the impact of drive current on the SET response of each transistor variant. The results show that the transistor drive current is a key factor for determining SET pulsewidths and cross sections for high linear energy transfer particle irradiation. Transistor variant data that result in matching transistor drive current show an excellent match for SET pulsewidths and cross sections. [ABSTRACT FROM AUTHOR]

Analysis of temporal masking effects of single-event upsets (SEUs) on master–slave flip-flops (FFs) is provided, considering the difference of SEU cross sections between master and slave latches. An improved model of temporal masking effects of SEUs in master–slave FFs is proposed and demonstrated through alpha-particle single-event effect (SEE) experiments. Based on the improved model, an effective and accurate methodology to quantitatively evaluate single-event transient and SEU-induced error cross sections of FF chains is proposed. Implications of SEE hardening for sequential circuits are discussed. [ABSTRACT FROM AUTHOR]

A combinational logic family, termed dual-interlocked logic (DIL), designed for single-event transient (SET) mitigation has been fabricated at a 16nm/14nm bulk FinFET technology generation and irradiated with heavy ions. Through both simulation and heavy-ion irradiation, DIL is shown to be robust to both single- and dual-node strikes. Results are compared to cascode voltage switch and standard logic to show the effectiveness of the logic family in mitigating SETs at the gate level. Three exemplar radiation-hardened-by-design synchronous systems using DIL, spatial triple modular redundancy (TMR), and temporal TMR are compared across area, power, delay, and hardness relative to an unhardened baseline system. The system utilizing DIL exhibits desirable tradeoffs compared to spatial and temporal TMRs. [ABSTRACT FROM AUTHOR]

We have evaluated radiation-induced charge trapping and low-frequency noise in passivated black phosphorus (BP) MOSFETs with HfO2 gate dielectrics. Thinning the gate dielectric reduces total ionizing dose-induced threshold voltage shifts. The defect-energy distribution estimated from low-frequency noise measurements performed as a function of temperature decreases with increasing energy in as-processed devices. Local maxima in noise magnitude are observed in irradiated devices at activation energies of ~0.2 and ~0.5 eV. Larger defect-related peaks in noise magnitude in the range of 0.35–0.5 eV are observed after biased post-irradiation annealing, and/or vacuum storage of the devices after irradiation and annealing. Density functional theory calculations strongly support significant roles for O vacancies in HfO2 and H+ transport and reactions near the BP/HfO2 interface in the observed radiation response and low-frequency noise. [ABSTRACT FROM AUTHOR]

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than $30\times $ in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region. [ABSTRACT FROM PUBLISHER]

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency. [ABSTRACT FROM PUBLISHER]

Single-event transients (SETs) in 16-/14-nm bulk fin field effect transistor (finFET) logic chains have been measured using a custom-designed test IC. A variety of logic gate chains were designed, and SET pulse widths were obtained across a wide range of supply voltages. In light of the increased SET response at reduced supply voltages, the efficacy of filter-based mitigation is assessed by analyzing the voltage dependence of SET duration against the characteristic electrical inverter delay. [ABSTRACT FROM PUBLISHER]

A uniform technology-agnostic time-domain model for both linear and nonlinear all-digital phase-locked loops (ADPLLs) is presented. This time-domain model can be used for single-event upset (SEU)-induced perturbation time prediction and SEU sensitivity characterization of common ADPLL topologies. The model is validated against field-programmable gate array-based fault injection experiments and two photon absorption laser experimental results on three different types of designs. The model is applicable to rad-harden by design activities, failure mode predictions, and general ADPLL design optimizations. [ABSTRACT FROM PUBLISHER]

We have performed a detailed evaluation of radiation-induced charge trapping and low-frequency noise for back-gated graphene transistors fabricated on a thermal SiO2 layer, with Al2O3 or hexagonal boron nitride passivation over-layers. Irradiation with positive or 0 V back-gate bias leads to negative shifts of the charge neutral point (CNP) of the graphene transistors; irradiation under negative back-gate bias leads to positive CNP shifts. The low-frequency noise increases with irradiation and decreases with 400 K postirradiation annealing. The temperature dependence of the noise is described well by the Dutta–Horn model of low-frequency noise. Peaks in effective defect-energy distributions of irradiated devices at ~0.4 and ~0.7 eV are identified via measurements of the temperature dependence of the low-frequency noise. The noise of as-processed devices stored in room ambient also decreases with baking, but does not show the clear peaks observed after irradiation. Density functional theory calculations suggest that OH− and H+ at or near the graphene/dielectric interfaces likely play key roles in both the irradiation and baking response. Low-frequency noise and CNP voltage shifts during switched-bias postirradiation annealing at room temperature also suggest significant roles for O vacancies in the near interfacial SiO2 and/or passivation layers. [ABSTRACT FROM PUBLISHER]

The 1T polytype of TaS2 exhibits voltage-triggered threshold switching as a result of a phase transition from nearly commensurate to incommensurate charge density wave states. Threshold switching, persistent above room temperature, can be utilized in a variety of electronic devices, e.g., voltage controlled oscillators. We evaluated the total-ionizing-dose response of thin film 1T -TaS2 at doses up to 1 Mrad (SiO2). The threshold voltage changed by less than 2% after irradiation, with persistent self-sustained oscillations observed through the full irradiation sequence. The radiation hardness is attributed to the high intrinsic carrier concentration of 1T -TaS2 in both of the phases that lead to threshold switching. These results suggest that charge density wave devices, implemented with thin films of 1T -TaS2, are promising for applications in high radiation environments. [ABSTRACT FROM AUTHOR]

Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed. [ABSTRACT FROM PUBLISHER]

The single-event sensitivity of bulk 40-nm sequential circuits is investigated as a function of temperature and supply voltage. An overall increase in SEU cross section versus temperature is observed at relatively high supply voltages. However, at low supply voltages, there is a threshold temperature beyond which the SEU cross section decreases with further increases in temperature. Single-event transient induced errors in flip-flops also increase versus temperature at relatively high supply voltages and are more sensitive to temperature variation than those caused by single-event upsets. [ABSTRACT FROM PUBLISHER]

A 20.4 GHz VCO with a tuning range of 610 MHz (3%) was designed and fabricated in a 32 nm CMOS silicon-on-insulator technology. At 36 °C, the VCO achieves an output power of 0.1 dBm and a phase noise of −99 dBc/Hz at 1 MHz offset from the center frequency. TID experiments on the VCO operating at 36 °C, 75 °C, and 100 °C show degradation in frequency, output power, and phase noise. At 100 °C and 500 krad(SiO2), the VCO shows a worst-case degradation of 630 MHz, 4.3 dBm, and 6.1 dBc/Hz in center frequency, output power, and phase noise, respectively. At 36 °C and up to 500 krad(SiO2), the VCO can be retuned to operate at the required center frequency of 20.4 GHz. However, at 100 °C, the combined effects of temperature and TID result in specification failure. The system-level impact of TID-induced degradation on VCO performance is discussed using a phase-locked loop (PLL) as an example application. Measured performance corroborates previous predictions and highlights the importance of combined effects testing for advanced RF design characterization and qualification. [ABSTRACT FROM PUBLISHER]

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- V\textit {th} transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and V\textit {th} , while the low- V\textit {th} transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( V\textit {gs}=V\textit {dd} ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- V\textit {th} transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics. [ABSTRACT FROM PUBLISHER]

A persistent loss-of-lock error was experimentally observed in a 20 nm charge-pump phase-locked loop (PLL). Through circuit modeling and simulation, the observed error was attributed to a non-recoverable off-state leakage increase resulted from two-photon absorption (TPA) laser-induced damage. The laser-induced damage is consistent with results from 28 nm bulk transistors. [ABSTRACT FROM PUBLISHER]

Electrical stress and 10-keV x-ray irradiation and annealing responses are evaluated for HfO2-passivated black phosphorous (BP) MOSFETs with HfO2 gate dielectrics. Device characteristics are stable during constant gate-voltage stress up to at least ±1 V. Significant negative threshold shifts, mobility degradation, and increases in subthreshold swing occur during both positive and negative bias irradiation. Hole trapping in the HfO2 gate dielectric dominates the TID response in these passivated BP MOSFETs. Reversibility of electrical parameters and magnitude of low frequency noise is observed during switched-bias annealing after irradiation. The voltage dependence of the low-frequency noise suggests that the trap distribution of the defects contributing to the noise becomes more uniform in energy after the devices are irradiated and annealed. [ABSTRACT FROM PUBLISHER]

Synergetic effects of total-ionizing-dose irradiation on the single event upset (SEU) and single event transient (SET) performance of 40-nm sequential circuits are studied at doses up to 2 Mrad(SiO2). The impacts of input pattern and supply voltage are evaluated. An initial increase of SEU- and SET-induced soft error cross-section versus total dose is observed, followed by a decreasing trend at higher doses. The maximum increase of SEU- and SET-induced soft error cross-section occurs when the total-ionizing-dose is approximately 1.5 Mrad(SiO2) in the studied sequential circuit. The SET-induced soft error cross-section versus total dose increases at a faster speed than the SEU-induced soft error cross-section. [ABSTRACT FROM PUBLISHER]

A technique for enhancing the precision of voltage references in an ionizing radiation environment is presented. Radiation-induced mismatch is identified as a fundamental source of error in voltage reference topologies, and chopper offset cancellation is used to mitigate the effect. The efficacy of the proposed technique is demonstrated by irradiating test chips fabricated in a commercial 180-nm process. [ABSTRACT FROM PUBLISHER]

The total ionizing dose (TID) response of bulk FinFETs is investigated for various geometry variations, such as fin width, channel length, and fin pitch. The buildup of oxide-trapped charge in the shallow trench isolation turns on a parasitic transistor, leading to increased leakage current (higher IOFF.) The TID-induced degradation increases with decreasing fin width. Transistors with longer channels degrade less than those with shorter channels. Transistors with large fin pitch degrade more, compared to those with narrow fin pitch. TCAD simulations are used to analyze the buildup of trapped charge in the trench isolation oxide and its impact on the increase in leakage current. The strong influence of charge in the STI in narrow-fin transistors induces a parasitic leakage current path between the source and the drain, while in wide-fin devices, for the same amount of trapped charge in the isolation oxide, the subsurface leakage path is less effective. [ABSTRACT FROM PUBLISHER]

Single-event transient (SET) induced harmonic errors have been observed in digitally controlled ring oscillators (DCRO). Accumulated phase error is used to characterize harmonic errors in ring oscillator circuits. An analytical model for determining minimum and maximum SET transient duration capable of generating a harmonic is described. Simulation and TPA laser experimental results on a 40-nm DCRO are shown to confirm the assertion of the harmonic vulnerability window with respect to SET pulsewidth. Further more, fault injection experimental results on three RO designs built with discrete commercial off-the-shelf components are included to demonstrate the relationship between harmonic response and SET pulsewidth. [ABSTRACT FROM PUBLISHER]

The impacts of total ionizing dose (TID), temperature and RF stress on the DC and RF performance of a commercial 32 nm RF silicon-on-insulator CMOS technology are presented. Temperature dependence is the overwhelmingly dominant single factor affecting the DC and RF performance, with the combined effects of elevated temperature and TID showing the most pronounced degradation. The most significant effect due to TID is an increase in off-state leakage current. Key DC and RF parameters of this 32 nm RF process degrade less than those of an otherwise similar 45 nm RF SOI CMOS process. The implications of the combined TID and temperature response are discussed for low-power RF design. [ABSTRACT FROM PUBLISHER]

The total ionizing dose response of triple-well FinFETs is investigated for various bias conditions. Experimental results show that irradiation with the transistor in the OFF state with the drain terminal high is the worst-case bias configuration. TCAD simulations are used to analyze the buildup of trapped charge in the trench isolation oxide and its impact on the increase in leakage current and subthreshold-slope degradation. The electric field distribution along the STI/fin boundary exerts a strong influence on the trapped charge in the isolation oxide, which induces a parasitic leakage current path at total ionizing doses of less than 200 krad(SiO2). [ABSTRACT FROM PUBLISHER]

We have performed time-domain reflectometry (TDR) measurements on nMOSFETs before and after irradiation on time scales relevant to MOS radio-frequency response. The decrease in effective impedance of MOSFETs with ionizing radiation exposure is greater for transistors biased in the off-state (all pins grounded) during TDR measurement than for transistors biased in the on-state (V_G high and the other terminals grounded). The increased admittance after irradiation is observable primarily in the off-state measurement. The increases in admittance (decreases in effective impedance) with TID correlate closely with decreases in trans-resistance at 0 V. These decreases result from increases in radiation-induced oxide-trap charge and interface-trap charge in the gate and/or shallow-trench isolation oxides. [ABSTRACT FROM PUBLISHER]

This paper investigates total-ionizing dose effects on the electrical characteristics of HfO_2/Hf-based bipolar resistive-random-access-memory (RRAM) devices. 10-keV x-ray irradiation does not cause significant changes in resistance at levels up to 7 Mrad(SiO_2). Excess carriers generated by x-ray irradiation in the HfO_2 layer recombine or are trapped at defect sites in the HfO_2 layer or at interfaces between layers. They have no effect, however, on the conductive path of the RRAM devices. 1.8 MeV proton irradiation causes resistance degradation through simultaneous introduction of oxygen vacancies and displacement damage. TRIM simulations are used to explain the physical mechanisms of the radiation-induced damage. The devices are promising for radiation-hardened memory applications. [ABSTRACT FROM PUBLISHER]

Single-Event Transient (SET) pulse widths were obtained from the heavy-ion irradiation of inverters designed in 32 nm and 45 nm silicon-on-insulator (SOI). The effects of threshold voltage and body contact are shown to significantly impact the SET response of advanced SOI technologies. Also, the reverse cumulative distribution is extracted from the count distribution for several targets and is shown to be a useful aid in selecting the temporal filtering for radiation-hardened circuitry. [ABSTRACT FROM PUBLISHER]

The combined effects of TID, process corner, and temperature on the performance of high frequency RF circuits are presented. TID experiments at 25^\circC and 100^\circC on NMOSFETs and PMOSFETs fabricated in a commercial 45 nm technology show varied degradation in DC and RF performance. The combination of variation due to TID, process, and temperature causes the NMOSFET parameters to fall out of the pre-irradiation process/voltage/temperature (PVT) operating space. TID-aware compact models of MOSFETs are developed based on measured parametric degradation of the transistor behavior. The compact models are used to design a K-band LC voltage-controlled oscillator (VCO), operating at 22 GHz without any compensation circuitry. Circuit simulations show that a 500 krad(SiO2) dose on the VCO operating at 100^\circC and at the slow process corner can result in circuit failure for biases less than 500 mV. For higher biases, TID causes degradation in frequency, amplitude, and phase noise, causing inability of the VCO to meet the desired performance specifications. [ABSTRACT FROM PUBLISHER]

We have investigated total ionizing dose (TID) radiation effects in Al2O3-gated ultra-thin body In0.7Ga0.3 As MOSFETs. A non-monotonic dependence of the threshold voltage (Vth) on the X-ray radiation dose was observed and analyzed; the accompanying degradation in subthreshold swing (SS) likely is caused by non-uniform trapped charge in the near-interfacial Al2O3 rather than interface-trap generation. The off-current and gate breakdown voltage were independent of dose up to 6 Mrad(SiO2). Compared to the InP-free device, the device with an InP barrier is more vulnerable to TID effects in terms of Vth shift, SS, and mobility degradation. [ABSTRACT FROM PUBLISHER]