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For the time and frequency signals of Beidou satellites, a high-accuracy phase frequency detection technology based on phase group synchronization is proposed. Using the Beidou receiver and satellite signals as the frequency standard and the measured signals, respectively. The Beidou receiver and the satellite signals are sent to the phase coincidence detector of the different frequencies to generate a phase coincidence point pulse, which is sent to the different frequency phase detector as a control signal to generate the phase differences between the Beidou receiver and satellite signals, and then complete the high-accuracy phase synchronization between the Beidou receiver and satellite signals. Experimental results show that when the delay resolution reaches ps level, the phase synchronization accuracy of the system can reach 10 ps, which has the characteristics of small phase noise, low development cost, simple circuit structure, and high synchronization accuracy compared with the traditional phase synchronization technologies. Therefore, it would be widely used in satellite positioning, astrometry, precision navigation, aerospace, satellite launch, power transmission, communications, radar, and other high-tech fields. [ABSTRACT FROM AUTHOR]

Cosmic microwave background (CMB) experiments have deployed focal planes with O (10 4) transition edge sensor (TES) bolometers cooled to sub-Kelvin temperatures by multiplexing the readout of many TES channels onto a single pair of wires. Digital Frequency-domain Multiplexing (DfMux) is a multiplexing technique used in many CMB polarization experiments, such as the Simons Array, SPT-3 G, and EBEX. The DfMux system studied here uses LC filters with resonant frequencies ranging from 1.5 to 4.5 MHz connected to an array of TESs. Each detector has an amplitude-modulated carrier tone at the resonant frequency of its accompanying LC resonator. The signal is recovered via quadrature demodulation where the in-phase (I) component of the demodulated current is in phase with the complex admittance of the circuit and the quadrature (Q) component is orthogonal to I. Observed excess current noise in the Q component is consistent with fluctuations in the resonant frequency. This noise has been shown to be non-orthogonal to the phase of the detector's responsivity. We present a detailed analysis of the phase of responsivity of the TES and noise sources in our DfMux readout system. Further, we investigate how modifications to the TES operating resistance and bias frequency can affect the phase of noise relative to the phase of the detector responsivity, using data from Simons Array to evaluate our predictions. We find that both the phase of responsivity and phase of noise are functions of the two tuning parameters, which can be purposefully selected to maximize signal-to-noise (SNR) ratio. [ABSTRACT FROM AUTHOR]

This paper comprehensively reviews the evolution and latest advancement of ultra-low All-Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical monitoring devices. With CMOS technology, these transceivers provide efficiency and simplicity, which are essential in the medical industry. As the size and power needs of these devices decrease due to CMOS scaling, they become more suitable for small and low-energy applications. In addition, this review also provides an insight into the ADPLL applications, Digital Controlled Oscillator (DCO), and Phase Frequency Detectors. The review highlights notable differences in performance between time-to-digital converters (TDC) and TDC-less designs. TDC-less design, like Digital Phase Frequency Detectors (DPFD), offers improvements in phase noise, small size, fast phase and frequency acquisition, and power efficiency at the expense of resolution. Comparing LC-DCO and ring-DCO revealed that at high operating frequencies, the ring-DCO consumes more power but has a simpler design and a smaller circuit area than LC-DCO. Future research should focus on enhancing the performance of the ADPLL RF transceiver for biomedical devices, specifically by using a low-voltage supply and implementing DPFD to achieve low power consumption, compact design and fast locking. The significant challenges remain in maintaining low power consumption at higher frequencies with Ring-DCO design. Using the Verilog HDL for ADPLL design and implementation provides modularity, simulation, synthesis, and flexibility, which makes it an excellent alternative to designing RF transceivers in biomedical applications which are efficient and reliable. [ABSTRACT FROM AUTHOR]

In this work, a phase noise reduction architecture for standalone oscillators is presented. The oscillator phase is divided and a voltage is generated by a type-I phase detector, which is compared with an ideal voltage to change the phase of the oscillator. Analysis shows that the loop parameters aid in phase noise suppression. The design is done in CMOS 90 nm technology for a 1 GHz ring oscillator. Post-layout simulations show that phase noise suppression is about 13 dB at 100 MHz offset for a division ratio of 2. [ABSTRACT FROM AUTHOR]

We demonstrate coherent optical frequency dissemination over a distance of 972 km by cascading two spans where the phase noise is passively compensated for. Instead of employing a phase discriminator and a phase locking loop in the conventional active phase control scheme, the passive phase noise cancellation is realized by feeding double-trip beat-note frequency to the driver of the acoustic optical modulator at the local site. This passive scheme exhibits fine robustness and reliability, making it suitable for long-distance and noisy fiber links. An optical regeneration station is used in the link for signal amplification and cascaded transmission. The phase noise cancellation and transfer instability of the 972-km link is investigated, and transfer instability of 1.1 × 10−19 at 104 s is achieved. This work provides a promising method for realizing optical frequency distribution over thousands of kilometers by using fiber links. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246. [ABSTRACT FROM AUTHOR]

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit ( F o M j i t t e r ) ~−236 dB. [ABSTRACT FROM AUTHOR]

In this paper, we present the high-speed phase frequency detector where the phase characteristics are enhanced. This PFD has a simple structure where the dead zone is annihilated and blind zone is highly reduced. This PFD generates UP and DN signal only when it gets the distinct phase difference. With the reduction of the reset time, the proposed PFD function is in the order of 1.5 M H z − 4 G H z operating frequency. The design shows the improvement by completely eliminating the dead zone. However, the blind zone is minimised to 74.6 p s in the phase characteristics which improves the output phase noise as −132.9 d B c / H z at 1 M H z offset frequency. The power consumption is minimised upto 417.3 μ W @ 4 G H z operating frequency. The design is simulated in standard 0.18 \mum CMOS technology node with 1.8 V power supply. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL application such as Zigbee, Wifi, Bluetooth and 4 G communication. [ABSTRACT FROM AUTHOR]

This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS ( V DD , w p , and w n ) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters V DD , w p , and w n are likewise determined using this procedure to maximize the circuit's overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180 nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are − 1 5 9. 5 6 dBc/Hz, 9.83 μ W, and 10.21 GHz, respectively, and it occupies a chip area of 300.41 μ m 2 . The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59 μ s. [ABSTRACT FROM AUTHOR]

A low‐noise fully‐integrated charge‐pump phase‐locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low‐pass filter (LPF), a voltage‐controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class‐C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91–8.94 GHz. The minimum and maximum measured phase noise are −125 dBc/Hz and −116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50‐mW power consumption. [ABSTRACT FROM AUTHOR]

In phase frequency detector (PFD) phase characteristics, the presence of dead zone fails to turn on the charge pump (CP) of the phase locked loop (PLL). This degrades the phase noise in PLL. To overcome this drawback in PFD, a circuit to eliminate dead zone using pass transistor logic (PTL) and delay cells (DCs) is proposed in this paper. The proposed circuit has been implemented in UMC 0.18 μ m CMOS process and simulated in a cadence spectre environment. From the post layout simulation results, it is noted that for a phase difference of - π to + π , the PFD achieves 100% linearity and is free from the dead zone. The designed PFD consumes power of 28.8 μ W at an operating frequency of 100 MHz. The proposed PFD is also verified across process voltage temperature (PVT) variations for its linearity. The PFD is independent of duty cycle variations of its input clock signals. It occupies an area of 312.4 μ m 2 . [ABSTRACT FROM AUTHOR]

For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage‐controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase‐frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage‐controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed‐forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide‐by‐47 and divide‐by‐48) that lacks a few extra flip‐flops which save considerable power and improves the frequency difficulties of the multi‐band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1‐μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS‐based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability. [ABSTRACT FROM AUTHOR]

This paper proposed a 5.42~6.28 GHz type-II phase locked loop (PLL) for the sake of both loop filter switching capability and extensive programmability. An on-chip loop filter is used in conjunction with off-chip one to form a switching filter pair for diverse application scenarios. In order to strike a balance between dead-zone elimination and noise contribution minimization, a 3-bit programmable reset time ranging from 25 ps to 200 ps with a step of 25 ps is brought into PFD (phase frequency detector) design while CP (charge pump) current is programmable from 200 μA to 900 μA with a 100 μA/step digital control. Power management units (PMU) including bandgap and low dropout regulators (LDO) are integrated on-chip with resistor string trimming which effectively counteracts fabrication variations. In addition, a piecewise linear VCO with 3-bit control is designed with a fully digital 6-bit multi-modulus divider (MMD) chain cascaded. The proposed PLL is implemented in a 40-nm bulk CMOS process and the power consumption is 8 mA@1.2 V, in which around 5 mA@1.2 V is consumed by output buffers. The fabricated PLL chip achieves a frequency tuning range of 5.42~6.28 GHz, a phase noise ranging from −107.2~−110.4 dBc/Hz@1 MHz offset from carrier, a reference spur of lower than −70 dBc when on-chip active loop filter bandwidth is set to be around 500 KHz. Its FoM is approximately −176.98~−180.18 dBc/Hz while FoMT is approximately −180.32~−183.52 dBc/Hz@1 MHz offset from carrier. Its most specifications are comparable to or better than most existing literature. [ABSTRACT FROM AUTHOR]

The phase frequency detector/charge pump is a significant source to raise the in-band phase noise of the phase-locked loop (PLL). The proposed CMOS-based pass transistor phase frequency detector (PT-PFD) solves the cycle skipping issue by improving the blind zone which in turn improves the phase noise performance. At the same time, in order to further improve the performance of the PLL, charge pump is integrated with the proposed design. In this case, the reset time has been reduced and thus the proposed PFD/CP functions up to the frequency of 1.5 MHz – 4.2 GHz. In addition, the modified pass transistor PFD architecture contains an advantage of less number of transistor count which consumes low power, i.e., 317.37 μ W . The design is based on standard 0.18 μ m CMOS process technology with the supply voltage of 1.8 V. Moreover, the proposed design has completely eliminated the dead zone, and blind zone is minimized up to 44.23 ps which improves the phase noise to −133.8 dBc/Hz at 1 MHz offset frequency. The PFD/CP proposed herein just requires lower power consumption while producing less noise in charge pump phase-locked loop (CPLL) application. [ABSTRACT FROM AUTHOR]

A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit's robustness is tested over process, voltage and temperature fluctuations. The suggested PFD achieves a phase noise of − 1 5 9. 1 7 dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25 μ W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275 μ m2. The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc. [ABSTRACT FROM AUTHOR]

The sensitivity of future gravitational wave (GW) detectors, such as the Einstein Telescope (ET), is constrained by quantum noise across the entire frequency range (10 Hz–10 kHz) and by magnetic noise at low frequencies (a few Hz to around 100 Hz). This article examines optimizing mechanisms to achieve efficient squeezing for reducing quantum noise, and also highlights the need to mitigate magnetic noise, through ongoing strategies. [ABSTRACT FROM AUTHOR]

The demand for low-power wireline circuits has motivated extensive work on novel circuit solutions. This article describes a one-eighth-rate clock and data recovery (CDR) circuit and a demultiplexer (DMUX) for processing four-level pulse-amplitude modulation (PAM4) signals in receivers (RXs). Detecting both major and minor data transitions, the proposed architecture can achieve a wider loop bandwidth (BW), suppressing oscillator phase noise and improving the jitter tolerance. Fabricated in 28-nm CMOS technology, the prototype provides a jitter transfer BW of 160 MHz with a tolerance of 1 UI at 10 MHz. [ABSTRACT FROM AUTHOR]

This work presents an ultra-low jitter, direct $W$ -band phase-locked loop (PLL). Using the proposed power-gating injection-locked frequency multiplier (PG-ILFM)-based phase detector (PD) that can maintain a high phase-error-detection gain even at high frequencies above 100 GHz, this $W$ -band PLL can achieve a very low in-band phase noise. Due to this intrinsically low in-band phase noise, the bandwidth of the PLL can be extended so that it can suppress the poor phase noise of the $W$ -band voltage-controlled oscillator (VCO). The frequency-offset canceller (FOC) is also presented to remove the possible frequency offset between the main VCO of the PLL and the replica VCO of the PG-ILFM-based PD. Operating in the background, the FOC can ensure high phase-error-detection gain and wide loop bandwidth and, thus, the low-jitter performance of the PLL. The proposed PLL was fabricated in a 65-nm CMOS process, and it used a power of 22.5 mW and an area of 0.16 mm2. The rms jitter, integrated from 1 kHz to 300 MHz, was 82 fs at 102 GHz. It also achieved the FoMJIT of–248.2 dB, which is the best among the state-of-the-art $W$ -band frequency synthesizers. [ABSTRACT FROM AUTHOR]

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fsrms at 40.96 GHz and 122 fsrms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW. [ABSTRACT FROM AUTHOR]

This article presents a 12–14.5-GHz fractional- ${N}$ subsampling phase-locked loop (PLL). Due to the subsampling topology, the noise in the subsampling phase detector (SSPD) and the subsampling charge pump (SSCP) is not multiplied by the divider ratio, improving the in-band phase noise. The multiphase generation required for the fractional- ${N}$ operation is implemented by both the digital-to-time-converter (DTC) and the phase interpolator to reduce the total delay required by the DTC, thereby suppressing the DTC intrinsic jitter. The proposed phase interpolator completely cancels out the short-current path by redefining the phase relationship between the input and the reset signal, improving its linearity significantly. The class-C voltage-controlled oscillator (VCO) consumes only 3.2 mW at 13.76 GHz while achieving −106-dBc/Hz phase noise at a 1-MHz offset. Designed and fabricated in 40-nm CMOS technology, the PLL operating in fractional- ${N}$ mode consumes 10.2 mW of power from a 1-V supply. The rms jitter integrated from 1 kHz to 100 MHz is 111 fs, arriving at a figure of merit (FoM) of −249 dB. [ABSTRACT FROM AUTHOR]

5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2. [ABSTRACT FROM AUTHOR]

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer- $N$ phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a −75-dBc reference spur, −101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 kHz–100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB. [ABSTRACT FROM AUTHOR]

We demonstrate the coherent transfer of an ultrastable optical frequency reference over a 490 km noisy field fiber link. The fiber-induced phase noise power spectrum density per-unit-length at 1 Hz offset frequency can reach up to 510 rad2â‹...Hzâˆ'1â‹...kmâˆ'1, which is much higher than the fiber noise observed in previous reports. This extreme level of phase noise is mainly due to the fiber link laying underground along the highway. Appropriate phase-locked loop parameters are chosen to complete the active compensation of fiber noise by measuring the intensity fluctuation of additional phase noise and designing a homemade digital frequency division phase discriminator with a large phase detection range of 212 Ď€ rad. Finally, a noise suppression intensity of approximately 40 dB at 1 Hz is obtained, with fractional frequency instability of 1.1 Ă— 10âˆ'14 at 1 s averaging time, and 3.7 Ă— 10âˆ'19 at 10000 s. The transfer system will be used for remote atomic clock comparisons and optical frequency distribution over a long-distance communication network established in China. [ABSTRACT FROM AUTHOR]

In this work, a novel phase frequency detector (PFD) architecture using pass transistor logic is proposed. The circuit does not have a reset path, resulting in the elimination of blind zone and dead zone. The ϕ -V characteristics of the PFD were found to have better linearity across the range of − π to π due to the absence of blind and dead zones. The Taguchi and ANOVA statistical techniques were used to optimize the PFD. The optimized PFD exhibited a phase noise of −142.24 dBc/Hz, consumed 5.64 μ W of power and had a maximum operating frequency of 5.25 GHz, and a delay of 10.65 ps. Using this PFD, a GHz-range synthesizer was designed, and its performance characteristics were obtained from circuit simulations using CADENCE Virtuoso. The synthesizer had a power consumption of 4.25 mW at a supply of 1.8 V, achieved a lock time of 2. 95 μ s , and could generate frequencies ranging from 0.1 GHz to 4.75 GHz while occupying a chip area of 0.013 mm 2. Moreover, the work introduced a new figure of merit, FoM. The synthesizer has potential applications in various devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems. • The simple circuit of Phase Frequency Detector avoids the use of reset path to achieve zero dead zone and high operating frequency. • Pass transistor logic employed to the second stage of PFD which enhance the operating frequency and simplify the circuit. • Taguchi DoE and ANOVA optimization methodology have been used to find out the sizes of MOS transistors and supply voltage to achieve optimized results. • Optimized PFD has lower phase noise, low power dissipation, lesser delay and high maximum operating frequency thus beneficial for low power and high speed frequency synthesizer applications. • Significant high speed, low power dissipation, low THD and lesser chip area of Frequency synthesizer making it suitable for use in high-speed devices such as radio receivers and GPS systems. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated analog phase‐locked loop (PLL) fractional‐N frequency synthesizer for 5G wireless communication and Internet‐of‐Everything (IoE) applications. To demonstrate the effectiveness of this frequency synthesizer, we apply it to three wireless communication standards. Contrary to using Verilog or VHDL to implement the programmable frequency divider, we propose a new approach in the transistor level with a new divide‐by‐2/3 circuit, dynamic asynchronous resettable D and JK flip‐flops, and the OR & AND gates to customize the divider for low‐power, low‐jitter, and fast‐lock time applications. In addition, we have designed a new frequency phase detector (PFD) to overcome the dead region issue. An ultra‐low phase noise and low‐power voltage control oscillator (VCO) is exploited from our previous work with the flicker noise corner frequency around 10 kHz to achieve the lowest possible phase noise. The implementation is done in 180‐nm standard CMOS technology. It covers two frequency ranges including 2.4 to 2.48 GHz and 5 to 5.825 GHz for these wireless communication standards. According to simulations in the worst case, the lock time, rms‐jitter, in‐band fractional spur, power consumption, and jitter‐power figure‐of‐merit of the frequency synthesizer is 18 μs, 56 fs, −63 dBc, 4 mW, and −259, respectively. [ABSTRACT FROM AUTHOR]

This article proposes a phase-locked loop (PLL) based on the direct digital synthesis (DDS)/digital-to-analog converter (DAC) and the double-edge zero-crossing sampling phase detector (DS-PD) for frequency-modulated continuous-wave (FMCW) radar. Its DS-PD and frequency divider are combined to achieve refined time resolution while effectively expanding the phase lock range, thus eliminating the frequency-locked loop (FLL). The DDS/DAC is used to generate FMCW signals while achieving fast frequency hopping. A differential eight switching current unit is proposed to implement an ultrahigh-speed time-interleaved DAC. The 8.55–17.11-GHz PLL prototype, fabricated in 65-nm CMOS, consumes 10.11 mW with 0.29-mm2 active area, while the DDS/DAC consumes 12.0 mW with a 0.16-mm2 active area. The measured in-band phase noise (PN) at a 17.11-GHz output is −120.2 dBc/Hz at a 1-MHz offset with a root-mean-square (rms) jitter of 51.7 fs. The reference spur is <−51 dBc. Finally, a figure-of-merit (FoM) value of −255.7 dB is obtained. The prototype PLL effectively generates fast (500 MHz/ $3.6~\mu \text{s}$) and precise (105-kHzrms frequency error) triangular chirps for FMCW radar applications. [ABSTRACT FROM AUTHOR]

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- $\mu \text{W}$ RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW. [ABSTRACT FROM AUTHOR]

This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push–pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of −82.2 dBc, an integrated jitter of 64.9 fsrms (1 kHz to 40 MHz), and an in-band phase noise (PN) of −128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is −255 dB. The entire SS-PLL consumes 7.5 mW, with only $90~\mu \text{W}$ associated with the FLL. [ABSTRACT FROM AUTHOR]

In this article, a mixed–signal, 32-kHz reference-based 2.4-GHz fractional- ${N}$ over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional $1\times $ sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digital-to-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs’ construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm2, and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional- ${N}$ modes with the loop-bandwidth (BWloop) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a CMOS based precharged phase frequency detector (PPFD) with improved output characteristic for phase locked loop (PLL) has been proposed and analyzed. The proposed PFD minimizes the reset time to improve the output characteristics and works upto the frequency of 1.25 MHz–3.8 GHz. In addition, it has an advantage of precharged PFD which has low power consumption capability i.e., 285.77 μ w. The design is based on standard 0.18 μ m CMOS process technology with the supply voltage of 1.8 V and achieves phase noise of - 135.45 dBc/Hz at 1 MHz offset. Further, the proposed design has minimized the Blind zone to 63 ps and has completely eliminated the dead zone in the phase characteristics. This is required for low noise phase locked loop (PLL) application. [ABSTRACT FROM AUTHOR]

In this article, we develop the theory of a special type of optoelectronic phase-locked loop (PLL). The output signal of this type of PLL is in the electrical domain and its reference oscillator, typically a mode-locked laser, operates in the optical domain. The PLL uses a balanced optical microwave phase detector (BOMPD). In order to model the optoelectronic PLL, the nonlinear characteristic function and the gain of the BOMPD are derived analytically. Using the results of the phase detector analysis, the theory of an optoelectronic PLL using such a phase detector is developed. Based on the theoretical analysis, a broadband optoelectronic frequency synthesizer with a programmable frequency range from 2 to 20 GHz is designed and implemented. Phase noise measurements show that the optoelectronic PLL frequency synthesizer achieves an integrated rms-jitter (1 kHz–100 MHz) of less than 4 fs in the frequency range from 5 to 20 GHz with a typical value of 4 fs and a minimum of 3 fs. This is the first reported wideband PLL frequency synthesizer achieving sub-10-fs integrated rms-jitter (1 kHz–100 MHz) in the frequency range from 3 to 20 GHz. A comparison with best-in-class laboratory-grade frequency synthesizers in this frequency range shows that this synthesizer achieves lower phase noise than any electronic frequency synthesizer for offset frequencies larger than 2 kHz. [ABSTRACT FROM AUTHOR]

In this article, a fractional- $N$ reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor-based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be effectively suppressed with the high-gain setting for the RSPD when the loop is in lock. The linear range of RSPD can be programmed to cover the quantization error in a frac- $N$ mode without degrading the PLL in-band phase noise. To mitigate the nonlinearity of RSPD, the CDAC is implemented with a high-order cancellation scheme using only one capacitor array but multiple reference voltages. The prototype chip was fabricated in a 45-nm partially depleted silicon-on-insulator (PDSOI) CMOS process. The measurement showed an output frequency range covering 7.7–9.1 GHz with an integrated jitter (10 kHz–50 MHz) of 135 fs and an in-band fractional spur level of −55 dBc at an offset frequency of 50 kHz. The entire PLL consumes 4.5 mW and achieves an figure of merit (FoM) of −250.8 dB. [ABSTRACT FROM AUTHOR]

A 2.4-GHz area-efficient and fast-locking subharmonically injection-locked type-I phase-locked loop (SIL-TPLL) is presented. A timing-adjusted phase detector (TPD) is proposed to calibrate the injection timing. This TPD also reduces the settling time of the SIL-TPLL. The loop capacitance of the type-I PLL is tiny to save the area. This SIL-TPLL is fabricated in 45-nm CMOS technology. Its active area is 0.013 mm2. The power consumption is 5.6 mW at 2.4 GHz for a supply of 0.87 V. The integrated jitter of the SIL-TPLL over 1 kHz to 40 MHz is 0.91 ps. [ABSTRACT FROM AUTHOR]

This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quarter-rate operation. Fabricated in a 40-nm CMOS process, the prototype achieves a bit efficiency of 0.46 pJ/bit at 32-Gb/s input data rate. The measured jitter tolerance (JTOL) at the bit error rate (BER) of < 10−12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz. The measured integrated jitter of the 4-GHz recovered clock is 352.6 fs. [ABSTRACT FROM AUTHOR]

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This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6 GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18- μ m CMOS technology with supply voltage of 1.8 V. The output clocks with cycle-to-cycle jitter of 2.13 ps at 1.6 GHz. The phase noise of VCO is − 137 dBc/Hz at an offset of 100 MHz and total power consumed by the proposed PLL is 2.63 mW at 1.6 GHz. [ABSTRACT FROM AUTHOR]

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6 GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180 nm CMOS process with supply voltage of 1.8 V. The phase noise of VCO is − 1 3 7 dBc/Hz at an offset frequency of 100 MHz. The reference clock of 25 MHz synthesizes the output clock of 1.6 GHz with rms jitter of 0.642 ps. [ABSTRACT FROM AUTHOR]

A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection-locked frequency multipliers (ILFMs) and a sub-THz mixer for frequency extension. Enhanced third-harmonic and fourth-harmonic-extraction techniques are proposed for the ILFMs with different multiplication ratios. In addition, a frequency-tracking loop (FTL) with automatic frequency and amplitude calibration is embedded for the ILFMs. Finally, a distributed bias technique is employed to improve the linearity of the wideband magnetic-tuning sub-THz oscillator. Designed in a 65-nm CMOS process, the proposed prototype achieves an ultra-wide frequency tuning range from 61.2 to 100.8, 122.4 to 136.8, and 198.5 to 273.6 GHz with a phase noise at 1-MHz offset from −79.3 to −95.4 dBc/Hz and an integrated jitter from 124 to 159 fs over the tuning range. The synthesizer occupies a core area of 0.58 mm2 and measures an output power of −11 dBm at 211.4 GHz with 49.5 mW, corresponding to a dc-to-radio frequency (RF) efficiency of 0.16%, an FoM from −171.4 to −177.7 dBc/Hz, and ${\mathrm {FoM}}_{T}$ from −177 to −190.5 dBc/Hz. [ABSTRACT FROM AUTHOR]

In this article, a two-stage millimeter (mm)-wave frequency synthesizer with low in-band noise and robust locking reference-sampling techniques is presented. Using a two-stage scheme allows separately dealing with the low phase noise (PN) frequency synthesis in the first stage and the mm-wave frequency multiplication in the second stage, achieving the best overall power efficiency. In the first stage, a voltage domain reference-sampling phase detector (RSPD)-locked loop (RSPLL) is adopted to achieve both low PN and robust locking without additional frequency locking loop. A reference reshaping buffer is implemented to improve the phase detector gain and in-band PN. The reference rising/falling time is programmable to achieve optimal RSPLL performance even under external disturbances. The second stage employs an injection-locked voltage-controlled oscillator (ILVCO) for 4 $\times $ frequency multiplication. A low-power digital frequency tracking loop (FTL) detecting actual frequency errors is implemented in order to achieve wide operation range for the ILVCO while using a high ${Q}$ tank with low power. The prototype synthesizer was fabricated in a 45-nm partially depleted silicon on insulator (PDSOI) CMOS technology. The first stage 9-GHz RSPLL achieves 144-fs integrated jitter with 7.2-mW power consumption, achieving a figure of merit (FoM) of −248 dB and the overall mm-wave synthesizer achieves 251-fs integrated jitter with 20.6-mW power consumption at 35.84 GHz, achieving an FoM of −238.9 dB. [ABSTRACT FROM AUTHOR]

This paper explores a speed and power improved dead zone free, low gate count CMOS phase frequency detector with charge pump (PFD-CP) for clock and data recovery application. Implemented in 90 nm CMOS technology, the proposed circuit configuration estimates a layout area of 420.66 μm2 and burns a low power as small as 172.10 μW when simulated with 5 GHz frequency at a power supply of 1.2 V at Cadence Virtuoso platform. With the elimination of reset path available in conventional PFD, this architecture doesn't only become blind zone free, but it also offers a lower phase noise and output noise of − 142.46 dBc/Hz and − 131.145 dBc/Hz respectively at 1 MHz offset. We have also studied the performance metrics with skew and without skew at different extreme corners for schematic and post layout to manifest the variation awareness and robustness of the circuit. The scalability of the circuit arrangement is also endorsed at lower CMOS technology. [ABSTRACT FROM AUTHOR]

An accurate frequency synthesizer is essential in wireless communications, radar systems, and frequency metrology. However, open-loop signal sources exhibit severe frequency fluctuation and are vulnerable to supply-induced frequency drift, phase noise, power consumption. There is a demand for precise oscillation frequency with wide tuning range and low phase noise. This motivates the proposed synthesizer to achieve relatively lower in-band phase noise as well as good out-of-band phase noise through the use of digital amplitude control circuit. This paper presents a low power, low phase noise, and fast locking CMOS PLL frequency synthesizer. The frequency synthesizer is designed by using the 65nmCMOS technology. It can support LTE, GSM/EDGE application with the frequency ranged from 4.39 GHz to 5.71 GHz for the local oscillator in the RF front-end circuits. This paper achieves the faster locking with the lock check through controlling the phase detector and charge pump to enhance the locking speed of the proposed PLL. By implementing the proposed design, the locking speed can be enhanced along with minimum power consumption and phase noise. [ABSTRACT FROM AUTHOR]

This article analyzes the jitter-power tradeoff in multiplying delay-locked loops (MDLLs), which differs from the more typical phase-locked loop one, and identifies a design optimization criterion. The methodology is applied to a fractional- ${N}$ MDLL with a sub-sampling bang-bang phase detector and a novel digital-to-time converter (DTC) range-reduction technique, which limits the jitter added to the reference signal, at no additional power penalty. The prototype has been implemented in 65-nm CMOS and covers a 1.6-to-3.0-GHz tuning range, achieving an absolute rms jitter (integrated from 30 kHz to 30 MHz) of 397 fs at 2.5-mW power, with a corresponding jitter-power figure of merit of −244 dB. In-band fractional spurs are as low as −51.5 dB and the occupied core area is 0.0275 mm2. [ABSTRACT FROM AUTHOR]

In this brief, a multiplying delay-locked loop (MDLL) using a frequency calibrator (FC) and a voltage monitor (VM) is presented. This FC uses a delay-calibrated subsampling phase detector (SSPD) to reduce the frequency error. The VM is used to cover a wide frequency variation. This MDLL is fabricated in 40-nm CMOS technology. Its active area is 0.013 mm2, and the power consumption is 5.2 mW from a supply of 1 V. It exhibits a root-mean-square jitter of 229 fs at 2.4-GHz output and the reference spur of −54.3 dBc under a reference clock of 150 MHz. [ABSTRACT FROM AUTHOR]

A low power, low jitter high performance Phase Locked Loop (PLL) based on closed loop Phase Frequency Detector (PFD) and novel Gain-Boosting Charge Pump (GB-CP) technique are shown in this study. The proposed work for WiMAX application is simulated using Tanner 13 tool using a 0.18µm CMOS technology. The current starved VCO is used to improve the linearity and phase noise of PLL. In feedback loop master-slave divided-by-2 frequency divider circuit is used to achieve a maximum speed with minimum power dissipation. The simulation result shows that total power consumption is 3mW at 1.8V power supply at maximum frequency of 2.4 GHz and RMS jitter is 3ps. The locking time of proposed PLL is 300ns, designed PLL is much suitable for WiMAX application [ABSTRACT FROM AUTHOR]