Search

In this study, the recent advances and trends in chiplet lateral communications (bridges) will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of chiplet horizontal communications. Some recommendations will also be provided. [ABSTRACT FROM AUTHOR]

Reliability of the restriction of the use of certain hazardous substances in electrical and electronic equipment compliant products is investigated in this study. Emphasis is placed on the lead-free solder joint reliability. Solder is the electrical and mechanical 'glue' of electronics assemblies. Will lead-free solders provide the characteristics necessary to allow the world to depend on it in the future? This paper cannot answer this question; however, it will help all participants in the soldering world better understand what needs to be done in order to answer this question and plan for the future. [DOI: 10.1115/1.2229234]

An exact analysis is presented for the stresses and deflections of circular plates (glass windows) elastically restrained along its edge in a photonic device's housing subjected to the pressure and temperature loadings. Dimensionless curves and charts are also provided for engineering practice convenience. These charts show the interactions of the deflection, stress, temperature, pressure, linear spring constant, rotational spring constant, geometry of the glass windows, and the Young's modulus, Poisson's ratio, thermal coefficient of expansion, geometry, stress-optical coefficient, and birefringence of glass materials. The results presented herein should be useful for designing glass windows for shipping, storing, handling, functioning, and reliability.

In this study, a three-dimensional (3D) nonlinear stress analysis of the tin whisker initiation on a pure matte Sn-plated copper substrate is investigated. The structure is subjected to a compressive stress acting at the Sn layer which is generated by the spontaneous chemical reaction of the formation of the [Sn.sub.5.Cu.sub.6] layer. The Sn layer is assumed to be an elasto-plastic material. The results presented herein is useful in understanding why the compressive stress in the Sn layer can initiate a tin whisker near the weak spot of a SnOx layer.

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton's creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented. [DOI: 10.1115/1.1462626]

A new empirical equation for predicting the thermal-fatigue life of wafer level chip scale package (WLCSP) solder joints on printed circuit board (PCB) is presented. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the average strain energy density around the crack tip of different crack lengths in the corner solder joint is determined by a time-dependent non-linear fracture mechanics with finite element method. The solder is assumed to be a temperature-dependent elastic-plastic and a time-dependent creep material. [DOI: 10.1115/1.1462625]

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt percent Sn-3.5wt percent Ag and 100wt percent In. The 62wt percent Sn-36wt percent Pb-2wt percent Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP Solder joint reliability are investigated. [DOI: 10.1115/1.1400995]

In this study, the Df (dissipation factor or loss tangent) and Dk (dielectric constant or permittivity) of the low-loss dielectric material from three different vendors are measured by the Fabry–Perot open resonator (FPOR) technique. Emphasis is placed on the sample preparation, data collection, and the comparison with the data sheet values provided from vendors. A coplanar waveguide with ground (CPWG) test vehicle with one of these raw dielectric materials (vendor 1) is designed (through Polar and simulation) and fabricated. The impedance of the test vehicle is measured by TDR (time-domain reflectometer), and the effective Dk of the test vehicle is calculated by the real cross-section of the metal line width, spacing, and thickness of the test vehicle and a closed-form equation. In parallel, the insertion loss and return loss are measured with the VNA (vector network analyzer) of the test vehicle. Finally, the measurement and simulation results are correlated. Some recommendations on the low-loss dielectric materials of the Dk and Df are also provided. [ABSTRACT FROM AUTHOR]

In this study, a high-density organic hybrid substrate for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication, characterization, and reliability of the hybrid substrate supporting three chips. The hybrid substrate consists of a fine metal linewidth and spacing redistribution-layer (RDL)-substrate, an interconnect-layer substrate, and a high-density interconnect (HDI) substrate. The heterogeneous integration of three chips on the hybrid substrate is characterized by continuity test and reliability assessed by reflow test and drop test. A nonlinear finite element analysis is performed to show the state of stress and strain at the conductive-paste-filled vias of the interconnect-layer substrate and critical solder joints under a thermal cycling condition. [ABSTRACT FROM AUTHOR]

A thermally-enhanced plastic ball grid array package called new and useful ball grid array (NuBGA) has been developed. NuBGA is equipped with a metal heat spreader, fully laminated with single-core double-sided organic substrate, which covers the entire back-side of a chip. Added features of the NuBGA are the split-wrap-around or split-via-connection which conspire for superior electrical performance.

A variety of thermal, mechanical and vibrational conditions influence the solder joint reliability of flip chip and plastic ball grid array (PBGA) assemblies. Three-point bending and four-point twisting tests of flip chips and PBGA assemblies help in studying the effects of overload environmental stress factors on the mechanical responses of solder joints. Out-of-plane vibration experiments determine shipping environmental stress effects on the vibrational responses. Coffin-Manson, nonlinear finite element and fracture mechanics method can study the thermal fatigue behavior of solder joints.

A study presents the time history temperature and stress responses in electronic packages when subjected to an instantaneous and a harmonic heat source. Various charts and curves relate the variables, frequency, time, heat, temperature, stress, displacement, and material characteristics. They are useful for engineering practice, designing of packages, verification of finite element analysis methods for thermoelesticity, and data interpretation.

In this study, the heterogeneous integration of two chips on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the materials, design, process, fabrication, and reliability of the package. Drop test and results of the package are also provided. [ABSTRACT FROM AUTHOR]

An approximated closed-form integrated circuit (IC) yield formula based on a Gaussian defect density distribution for the compounder in Murphy's yield integral is presented. Also, a closed-form solution for the average number of faults (A[D.sub.0]) in an IC is obtained for a given IC yield (Y). Furthermore, based on the new IC yield formula a simple equation for determining the number of yielded chips in a wafer is given. Finally, the multichip module yield ([Y.sub.m]) and resultant shipped multichip module yield ([Y.sub.ms]) based on the new IC yield formula are provided.

An exact analysis is presented for the creep deformation of a thin-walled circular solder cylinder under the actions of bending and twisting moments. Dimensionless interaction curves and charts which relate the variables, interconnect geometry, solder material properties, bending moment, twisting moment, curvature rate, and twist rate are also provided for engineering practice convenience.

Analysis of creep possessing circular solder column bending in the presence of axial force reveals the tangent-modulus buckling loads and a formula for calculating the critical time to buckling. An approximation of the process indicates that plane sections prior to bending remain plane during bending. The results are obtained in the form of stress ratio and strain rate ratio.

An exact solution for a thermoelastic problem with constant temperature distribution over a rectangular region is used to analyze a chip on a semi-infinite substrate. Dimensionless charts are obtained for the temperature and stress distributions in the substrate. A sample application on the use these charts is also presented. The charts are useful in designing substrates and verifying the finite element analysis of thermoelasticity problems.

In this study, the recent advances and trends of chiplet design and heterogeneous integration packaging will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, lateral interconnects, and examples of chiplet design and heterogeneous integration packaging. Also, emphasis is placed on the fundamental and examples of hybrid bonding. [ABSTRACT FROM AUTHOR]

The panel-level redistribution-layer (RDL)-first fan-out packaging for hybrid substrate is studied. Emphasis is placed on the process, materials, design, and fabrication of: 1) heterogeneous integration of one large chip and one small chip with 50-μm pitch (minimum); 2) fine metal linewidth and spacing RDL-first substrate on a temporary panel carrier; 3) ordinary build-up package substrate on a panel; 4) hybrid substrate which is by soldering the RDL-first substrate on the build-up substrate; and 5) chips to hybrid substrate bonding and underfilling. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the two-chip package on the hybrid substrate that is performed by a nonlinear temperature- and time-dependent finite-element analysis. [ABSTRACT FROM AUTHOR]

In this study, the feasibility of mini-light-emitting diode (LED) RGB display fabricated by a chip-first fan-out panel-level packaging is investigated. Emphasis is placed on the design, materials, process, fabrication, and reliability of the mini-LED RGB display package on a printed circuit board (PCB). The mini-LEDs under consideration and their sizes are red (125 × 250 × 100 μm), green (130 × 270 × 100 μm), and blue (130 × 270 × 100 μm). The spacing among the RGB mini-LEDs is 80 μm, the pixel-to-pixel spacing is also ~ 80 μm, and the pixel pitch is 625 μm. The temporary glass panel for making the redistribution layers (RDLs) of the package is 515 × 510 × 1.1mm in size. To increase the SMT assembly yield on the PCB, the mini-LEDs are grouped into 4(2 × 2 pixels)-in-one surface mount device (SMD), that is, a total of 12 R, B, and G mini-LEDs. A PCB (132mm × 77mm) is designed and fabricated for the drop test of the mini-LED package. Thermal cycling of the mini-LED SMD PCB assembly is also performed by a nonlinear temperature- and time-dependent finite-element simulation. [ABSTRACT FROM AUTHOR]

In this study, the reliability of the solder joints of a sixside molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (25°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a printed circuit board. For comparison purpose, the one without six-side molded (ordinary) PLCSP is also subjected to the same test. The thermal cycling test results are plotted into a Weibull distribution, and the true Weibull slope and true characteristic life at 90% confidence are presented. The solder joint mean life ratio of these two cases and its confidence level are also determined. Furthermore, their solder joint failure location and failure mode are provided. Finally, a nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for these two cases and correlated with the thermal cycling test results. [ABSTRACT FROM AUTHOR]

In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (735 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 5153510-mm panel is investigated. Emphasis is placed on the thermal cycling test (25°C D 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results. [ABSTRACT FROM AUTHOR]

Accurate assays for hepatitis C virus (HCV) quantitation and genotyping are important for the management of HCV infection. In this study, we evaluated the performance of cobas HCV and cobas HCV GT assays (Roche) for HCV quantitation and genotyping on the cobas 4800 System. We compared the performance of the cobas HCV assays with another commercial system (Abbott m2000) using a panel of well-characterized patient samples and proficiency testing samples. The limit-of-detection of the cobas HCV assay in our center was higher (15 IU/mL) than the manufacturer claim (9.2 IU/mL). The assay showed high analytical specificity, accuracy, precision, and linearity. Performance was congruent with the RealTime HCV assay (Abbott). For genotyping, the cobas HCV GT assay only showed moderate agreement with the RealTime HCV Genotype II assay (kappa = 0.550). The cobas assay outperformed the RealTime assay for typing HCV genotypes 1b and 6 (p = 0.033). Our results confirm that the cobas 4800 System is a reliable platform for HCV quantitation and genotyping. The cobas HCV GT assay is a good choice for genotype 1b/6 endemic areas in east Asia, clearly outperforming the RealTime HCV Genotype II assay. [ABSTRACT FROM AUTHOR]

In this study, the design, materials, process, assembly, and reliability of a six-side molded panel-level chip-scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the redistribution layers (RDLs) of the PLCSP on a large temporary panel with multiple device wafers. Because all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Because all the processes/equipment are PCB processes/equipment (not semiconductor process/equipment), it is a very low-cost process. After the fabrication of RDLs, the wafers from the PCB panel were debonded. It is followed by solder ball mounting and fabricating the six-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the six-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and timedependent finite-element simulation. [ABSTRACT FROM AUTHOR]

In this article, the fan-out chip-last panel-level packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication, and simulation of thermomechanical reliability of a heterogeneous integration of one large chip (10 mm $\times 10$ mm) and two small chips (7 mm $\times 5$ mm) by a fan-out method with a redistribution-layer (RDL)-first substrate fabricated on a 515 mm $\times510$ mm panel. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the three-chip package on a printed circuit board (PCB) assembly that is performed by a nonlinear temperature- and time-dependent finite-element simulation. [ABSTRACT FROM AUTHOR]

In this study, a very high-throughput and low-cost packaging method for fabricating the fan-in chip-scale package is presented. Emphasis is placed on the utilization of the existing printed circuit board (PCB) panel carriers and the corresponding PCB equipment for making the redistribution-layers (RDLs), vias, under bump metallurgy (UBM), contact pads, solder mask, and surface finishing of the package. Since all the PCB panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. [ABSTRACT FROM AUTHOR]

In this investigation, the chip-last, redistribution-layer (RDL)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 3 10 mm2) and two small chips (7 3 5 mm2) by an FOPLPmethod on a 20320-mm2 RDL-first substrate fabricated on a 515 3 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided. [ABSTRACT FROM AUTHOR]

The recent advances and trends in heterogeneous integrations are presented in this study. Emphasis is placed on: (A) the definition of heterogeneous integrations, (B) the classifications of heterogeneous integrations such as heterogeneous integrations on (a) organic substrates, (b) silicon substrates (through-silicon via interposers), (c) silicon substrates (bridges), (d) fan-out RDL (redistribution-layer) substrates, and (e) ceramic substrates, and (C) the examples of heterogeneous integrations of chip-to-chip, chip-to-wafer, memory stacks, package-on-package, light-emitting diode, CMOS image sensors, microelectro- mechanical systems, vertical-cavity surface-emitting laser, and photodetector. The trends of heterogeneous integrations are also presented. [ABSTRACT FROM AUTHOR]

Solder joint reliability of flip chip on various thickness of printed circuit board with imperfect underfill is presented in this study. Emphasis is placed on the determination of the temperature-dependent stress and plastic strain at the corner solder joint with different crack (delamination) lengths. Also, the strain energy release rate and phase angle at the crack tip of the interface between the underfill and solder mask are obtained by fracture mechanics. [S1043-7398(00)01104-X]

A novel and reliable wafer level chip scale package (WLCSP) is investigated in this paper. It consists of a copper conductor layer and two low cost dielectric layers. The bump geometry consists of the eutectic solder, the copper core, and the under bump metallurgy. Nonlinear time-temperature-dependent finite element analyses are performed to determine the shear stress, shear creep strain, shear stress and shear creep strain hysteresis loops, and creep strain energy density of the corner solder joint. The thermal-fatigue life of the corner solder joint is then predicted by the averaged creep strain energy density range per cycle and a linear fatigue crack growth rate theory. The WLCSP solder bumps are also subjected to shear test. Finally, the WLCSP solder joints are subjected to both mechanical shear and thermal cycling tests. [S1043-7398(00)01004-5]

The popcorning effect of plastic ball grid array (PBGA) packages is analyzed using the method of fracture mechanics. The following three specific problems are studied: (1) crack initiation in the die attach of the package, (2) crack growth in the die attach, and (3) crack growth at the interface between the solder mask and copper. Two different methods (crack tip opening displacement and virtual crack closure technique) are used to determine the crack-tip parameters such as the strain energy release rate, stress intensity factors, and phase angle for different crack lengths and temperatures. [S1043-7398(00)00401-1]

In this paper, the warpages of a chip-first and die face-up fan-out wafer-level packaging (FOWLP) with a very large silicon chip (10 mm $\times \,\, 10$ mm $\times \,\, 0.15$ mm) and three redistributed layers are measured and characterized. Emphasis is placed on the measurement and 3-D finite-element simulation of the warpages during the FOWLP fabrication processes, especially for: 1) right after postmold cure; 2) right after backgrinding of the epoxy molding compound to expose the Cu-contact pads; and 3) the individual package (right after the solder ball mounting and dicing) versus surface mount technology reflow temperatures. The simulation results are compared to the measurement results. Some recommendations on controlling the warpages are provided. [ABSTRACT FROM AUTHOR]