299 results on '"Horiguchi, N."'
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2. Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K
3. Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
4. Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET
5. Ni(Pt) silicide with improved thermal stability for application in DRAM periphery and replacement metal gate devices
6. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks
7. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
8. Properties of ALD TaxNy films as a barrier to aluminum in work function metal stacks.
9. Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell
10. Electrical demonstration of thermally stable Ni silicides on Si 1−xC x epitaxial layers
11. A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier
12. A ligand for peroxisome proliferator activated receptor γ inhibits cell growth and induces apoptosis in human liver cancer cells. (Original Article)
13. Azelnidipine is a calcium blocker that attenuates liver fibrosis and may increase antioxidant defence
14. DIFFERENTIAL ROLE OF CELL-SPECIFIC STAT3 IN ALCOHOL-INDUCED LIVER INFLAMMATION: 010
15. Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability.
16. Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors.
17. Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation.
18. Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies.
19. On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI.
20. Low-Frequency Noise Assessment of Work Function Engineering Cap Layers in High-κ Gate Stacks.
21. Performance Comparison of ${n}$ –Type Si Nanowires, Nanosheets, and FinFETs by MC Device Simulation.
22. Middle-of-line plasma dry etch challenges for CFET integration.
23. Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond
24. PO-008 Accelerated DNA methylation in gastric mucosa adjacent to cancer after HELICOBACTER PYLORI eradication
25. Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations.
26. Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality.
27. Superior NBTI in High- $k$ SiGe Transistors?Part I: Experimental.
28. Superior NBTI in High-k SiGe Transistors–Part II: Theory.
29. Mapping of CMOS FET degradation in bias space-Application to dram peripheral devices.
30. Processing Technologies for Advanced Ge Devices.
31. Holisitic device exploration for 7nm node.
32. Experimental evidences and simulations of trap generation along a percolation path.
33. Low-frequency noise of advanced memory devices.
34. TCAD-based methodology for reliability assessment of nanoscaled MOSFETs.
35. I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.
36. Assessment of SiGe quantum well transistors for DRAM peripheral applications.
37. Impact of thermal budget on the low-frequency noise of DRAM peripheral nMOSFETs.
38. Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass.
39. Thermal budget impact on HKMG Al2O3 and La gate stacks for advanced DRAM periphery transistors.
40. Middle-of-line plasma dry etch challenges for buried power rail integration.
41. Kinetic Monte Carlo simulations for dopant diffusion and defects in Si and SiGe: Analysis of dopants in SiGe-channel Quantum Well.
42. Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors.
43. Self-aligned double patterning of 1× nm FinFETs; A new device integration through the challenging geometry.
44. Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.
45. Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.
46. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.
47. Scanning spreading resistance microscopy for carrier profiling beyond 32nm node.
48. Novel Approach to Conformal FINFET Extension Doping.
49. Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability.
50. Process options to enable (sub-)1e-9 Ohm.cm2 contact resistivity on Si devices.
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