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The X-ray free-electron laser (XFEL) at the Pohang Accelerator Laboratory (PAL), Pohang, South Korea, provides X-ray energies of up to 15 keV depending on the experimental purpose. Silicon-based devices have been used as diagnostic devices and detectors for X-rays in experimental stations. Considering recent domestic and international circumstances, developing silicon-based detectors in-house is necessary. We developed a silicon p-intrinsic-n (PIN) photodiode (PD) for X-ray detection, and its performance was investigated and compared with that of a commercial PD used in the PAL-XFEL. The PD was designed to be 1 cm $\times1$ cm in size, and it used the junction side for signal readout and the ohmic side for X-ray entrance. Considering the absorption length of 12-keV X-rays suitable for crystallography, a 500- $ {\mu }\text{m}$ -thick silicon wafer with a high resistivity was used for PD fabrication. It has a guard ring, an n+ edge field shaper, and an antireflection coating (ARC) and is available in four different types based on the metal structure of the junction and ohmic sides. We present here the electrical characteristics of the PDs. The depletion voltage at which the bulk of the PD is fully depleted was determined to be 119.7 ± 8.2 V from bulk capacitance measurements, and the operation voltage of the PD was set to 200 V. PDs with leakage currents less than 30 nA/cm2 at the operation voltage were chosen for performance measurements. The signal-to-noise ratio (SNR) with a Sr-90 radioactive source corresponding to the minimum ionizing particle (MIP) and the quantum efficiency (QE) for wavelengths of 300–1000 nm were measured. Beam tests were conducted at the PAL-XFEL using 600-, 900-, and 1200-eV X-rays where the responses to ultrahigh brightness and ultrashort X-ray pulses were checked. The energy resolutions were measured using gamma-ray radioactive sources, Am-241 (59.5 keV), and Ba-133 (31.0 and 81.0 keV). The differences in performance among the PD types are presented herein in terms of the electrical characteristics, SNR, QE, response to X-ray pulses, and energy resolutions. The results of the fabricated PDs were also compared with those of a commercial PD. [ABSTRACT FROM AUTHOR]

We report the fabrication of vertical metal–oxide–semiconductor (MOS) detectors with the highest energy resolution ever reported. The MOS detectors have been fabricated on 50- $\mu \text{m}$ -thick n-type 4H-SiC epitaxial layers by growing a silicon dioxide (SiO2) layer thermally prior to contact deposition. The MOS detectors exhibited leakage currents two orders of magnitude lower than that observed in a Schottky barrier detector (SBD) fabricated on similar 4H-SiC epilayers. The MOS detectors exhibited a much higher energy resolution of 0.4% compared to 0.8% observed in an SBD for 5486-keV alpha particles although both the devices showed a high charge collection efficiency (CCE) of 96% when exposed to the alpha particles. Capacitance mode deep-level transient spectroscopy (C-DLTS) revealed the presence of “lifetime killer” $\text{Z}_{\mathrm {1/2}}$ defects in similar concentrations in both the devices, and however, the corresponding capture cross section in the SBD has been observed to be one order of magnitude higher compared to the MOS detector, and instead of EH6/7 center seen in the SBD, the MOS device showed the presence of EH5 center. The higher resolution of the MOS device is attributed to the lower leakage current and difference in defect configurations observed between the two devices. The MOS detector showed a positive polarity C-DLTS peak with an activation energy of 1.22 eV, which is likely due to the nonnegligible impedance of the back contact because of the SiO2 layer. The present study opens the great potential of other wide bandgap semiconductor-based vertical MOS detectors, which can be fully depleted for high-resolution X-/ $\gamma $ -ray detection. [ABSTRACT FROM AUTHOR]

The radiation tolerance of isotopic enriched and natural silicon carbide junction barrier Schottky diodes are compared under heavy ion irradiation. Both types of devices experience leakage current degradation as well as single-event burnout events. The results were comparable, although the data may indicate a marginally lower thresholds for the isotopic enriched devices at lower linear energy transfer (LET). Slightly higher reverse bias threshold values for leakage current degradation were also observed compared to previously published work. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

This article studies the apparition and the fast annealing of a leakage current in p- and n-MOS transistors and structures. This leakage current is observed for total ionizing doses (TIDs) of 50 Mrad(SiO2) and above and anneals rapidly within the hours following the end of irradiation. An extensive set of specially designed and dedicated structures are used to study this phenomenon. In particular, the article presents the effects of the dose rate, the transistor type (n or p), the drain–source voltage, or the bias during annealing. Results show that the observed transient leakage current is an intensification followed by fast annealing of the generation current inside the drain and source depletion regions. It appears that this generation leakage current most likely originates from the creation of positive charges in the thick oxides of the devices, that is, the shallow trench isolation (STI) and the pre-metal dielectric (PMD), and it generally anneals at ambient temperature in less than 12 h after irradiation. [ABSTRACT FROM AUTHOR]

The leakage current degradation, single-event burnout (SEB), and single-event gate rupture (SEGR) behaviors induced by the heavy-ion irradiation in p-Channel and n-Channel power U-shaped metal–oxide–semiconductor field-effect transistors (UMOSFETs) are comparatively investigated in this article via experiments and simulations. The SEB and SEGR performances of a commercially available −100-V-rated p-Channel UMOSFET are tested under heavy-ion irradiation. The experimental results show that the sample devices can be prevented from the drain leakage current or gate leakage current degradation under the bias conditions of $V_{\mathrm {GS}} = -100$ V and $V_{\mathrm {GS}} = 0$. However, a severe gate leakage current degradation can occur at $V_{\mathrm {DS}} = -100$ V when $V_{\mathrm {GS}} \ge 5$ V. In addition, the SEB and SEGR characteristics of a 100-V-rated n-Channel UMOSFET are obtained by simulations. The simulation results indicate that a p-Channel UMOSFET can achieve much better robustness against heavy ions compared with an n-Channel UMOSFET. Further, the leakage current degradation and failure mechanisms induced by heavy-ion irradiation are investigated via simulations. Finally, an effective method, which enlarges the width and depth of the source contact trench, is introduced to enhance the SEB tolerance of an n-Channel UMOSFET. The simulation result shows that the SEB threshold voltage can represent an increase of 23.1% with the hardening method. [ABSTRACT FROM AUTHOR]

Radiation-induced leakage current degradations for SiC power MOSFETs are investigated by 181Ta ion irradiation. An ion flux-related leakage degradation is reported for the first time. It is manifested as a more significant leakage current under higher flux irradiation than that under low flux irradiation, even though the total fluence is the same. Emission microscope (EMMI) results show that more leakage paths are formed for high flux irradiation. The drain bias during irradiation is another key fact to affect the radiation-induced leakage degradation. The leakage only occurs when the drain bias is larger than 300 V for flux = 1000/cm $^{2}\cdot \text{s}$ irradiation. An interesting phenomenon is that although radiation-induced leakage is not observed at 200 V with ion flux of 1000/cm $^{2}\cdot \text{s}$ , leakage appears when the ion flux increases to 6000/cm $^{2}\cdot \text{s}$. A multi-ion interaction theory is proposed to explain the above phenomenon. The mechanisms of these phenomena are also proved by TCAD simulations. [ABSTRACT FROM AUTHOR]

Low-gain avalanche diode (LGAD) is the chosen technology for the ATLAS high-granularity timing detector (HGTD). According to previous studies, the acceptor removal effect due to the radiation and the single-event burnout (SEB) at high bias voltages are still a challenge for the LGAD. The Institute of High Energy Physics (IHEP), Beijing, China, cooperated with the Institute of Microelectronics (IME), Beijing, China, for the design and fabrication of the IHEP-IME LGAD sensors with shallow carbon and deep N++ layer to improve the radiation hardness of LGAD. After neutron irradiation up to $2.5 \times 10^{15}\,\,{\mathrm{ n}}_{\mathrm{ eq}}$ /cm2, the leakage current, the collected charge, and timing resolution of the three IHEP-IME sensors measured with a beta telescope setup meet the HGTD requirements ($< 125~\mu \text{A}$ /cm2, >4 fC, and <70 ps). The LGAD sensor with shallow carbon had the lowest operation voltage after irradiation and is very promising to avoid the SEB effect. A sensor with a deep N++ layer increased the breakdown voltage of the LGAD with a high dopant concentration, which could alleviate the problem of the early breakdown of radiation-hard LGAD before irradiation. [ABSTRACT FROM AUTHOR]

Leakage current of 1200-V 4H-SiC Schottky barrier diodes (SBDs) with different structures increased by various degrees after heavy-ion exposure. By taking ${I}$ – ${V}$ measurements in a range of 298 to 448 K, the voltage dependence of saturation current ($I_{0}$), barrier height ($\phi _{B0}$), and ideality factor ($n$) were obtained. The dependence of these parameters with temperature illustrates the Gaussian distribution of barrier height. The inhomogeneity of the Schottky barrier height (SBH) distribution was successfully described using a modified thermionic emission (TE) model with Gaussian distribution, and the average barrier height ($\bar {\phi }_{B0}$) was gained. The results show that the barrier height distribution of all SBDs remain unchanged after the irradiation which means heavy-ion exposure did not affect the Schottky barrier. [ABSTRACT FROM AUTHOR]

In this study, a circuit- and device-level design was developed to improve the radiation tolerance of an analog switch integrated circuit (IC), which was fabricated using a commercial 0.35- $\mu \text{m}$ bipolar–CMOS–DMOS (BCD) process. Both circuit- and layout-level approaches were used to improve the total ionizing dose (TID) tolerance of the IC. In the circuit-level approach, a level shift unit was used to reduce the amount of oxide traps. Under the layout-level approach, a ring gate and a doping ring were added to reduce the leakage current. Moreover, the optimum doping concentration of $P_{\mathrm {WELL}}$ and length of the $N_{+}$ drift zone were calculated for the n-MOSFET based on simulations to obtain the best device structure and improve the single-event burnout (SEB) tolerance. The radiation tolerance was tested experimentally. The results indicated that the newly designed 30-V high-voltage low-power analog switch chip had a TID tolerance >300 krad(Si) and a SEB tolerance >75 MeV cm2/mg, which are useful to improve the radiation-tolerant capability of high-voltage analog switches. [ABSTRACT FROM AUTHOR]

The anode-short metal–oxide–silicon (MOS)-controlled thyristor (AS-MCT) is the latest generation of MCT. Due to its MOS gating, high-current-rise rate, normally-OFF, and high blocking capabilities, the AS-MCT is an ideal switch for pulse discharge application. Previously, we show that the static behaviors of AS-MCT are susceptible to displacement damage (DD) as it contains bipolar structures. As a continuation of our previous work, this article reports the experimental results for the degradation of pulse discharge circuit (PDC) characteristics induced by the DD of its XND1 AS-MCT switch following fast neutron exposure up to $7.8\times {10}^{13}\,\,{\text {cm}}^{-2}$. Both the charging time and the peak surge current of the PDC decrease significantly once the neutron flux surpasses a critical value, $\sim {10}^{12}\,\,{\text {cm}}^{-2}$. From device and circuit physics perspectives, an analytical model based on equivalent leakage current resistance is proposed to describe the degradation of the two parameters, and then, this article suggests the mechanisms behind such degradations from the neutron exposure of AS-MCT switch. [ABSTRACT FROM AUTHOR]

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized under dynamic and static test conditions through changes in ring oscillator (RO) frequencies, leakage currents, and inverter delays. Results from total-dose exposures using the ARACOR X-ray machine showed that static conditions represented the worst case conditions. Higher operating frequencies resulted in increased leakage currents and inverter delays after irradiation. The rate of change for leakage current was inversely proportional to frequency during exposure. The rate of change for inverter delay was directly related to frequency during TID exposure. Overall, degradations in circuit-level parameters (logic gate delays and operating current) were less than 1% for TID exposures of 435 krad(SiO2). [ABSTRACT FROM AUTHOR]

Negative-bias-stress and total-ionizing-dose (TID) effects in deeply scaled Ge-gate-all-around (GAA) nanowire (NW) devices are characterized for different biasing conditions. Negative-bias-stress-induced degradation in Ge GAA device originates primarily from the interface- and border-trap generation. Devices stressed at high gate voltage show rapid initial degradation and quick saturation dominated by interface-trap generation. Radiation-induced OFF-state leakage current in Ge GAA NWs increases with dose due to enhanced band-to-band tunneling (BTBT) caused by charge trapping in the shallow trench isolation (STI). [ABSTRACT FROM AUTHOR]

An on-chip measurement circuit that was specifically designed to capture the high-speed transient characteristics of photocurrent is employed to measure total-ionizing-dose (TID)-induced leakage from 10 keV X-rays. This circuit uses a photocurrent-controlled oscillator (PCO) to produce an analog frequency, which provides linearity comparable to traditional, off-chip methods of TID measurement. The circuit was fabricated in a sub-50 nm, fully depleted silicon-on-insulator (FD-SOI) technology. TID-induced leakage currents were measured using the circuit and results were compared to off-chip direct measurements from identical transistor arrays. Additionally, potential in situ applications of this circuit in conjunction with a TID-compensating back-gate biasing technique are explored. [ABSTRACT FROM AUTHOR]

A method of analyzing ion-induced reverse leakage current in SiC power devices is described. The resulting methodology enables the estimation of the proportion of ion strikes that produce step increases in leakage current as well as distributions of sensitive die areas relative to leakage step magnitude. These results are compared across various bias and ion linear energy transfer combinations to isolate the influence of each variable. [ABSTRACT FROM AUTHOR]

This article studies the radiation effects on the junction leakage random telegraph signal (JL-RTS). Using arrays of transistors, a statistical study of the phenomenon in MOSFETs source p-n junctions is performed and the impact of the electric field, the type of irradiation, and the source design is investigated. It appears that although JL-RTS originates both from the displacement damage dose (DDD)- and total ionizing dose (TID)-induced defects, the latter is the dominant contribution in MOSFETs sources due to an electric field enhancement (EFE). This article then completes the study with ab initio molecular simulations to investigate the origin of the JL-RTS. The results advocate for the adoption of the structural fluctuation model over the state charge fluctuation model to describe the origin of the phenomenon. [ABSTRACT FROM AUTHOR]

We present the first results of a custom low-noise silicon photodiode detector designed for use with X-ray capillary optics. This system is intended to perform as a smaller, lighter, and low-powered alternative to currently existing X-ray telescope technologies. The detector has an active area with a diameter of 100 $\mu \text{m}$ , and its small size leads to a low capacitance of well under 1 pF and a leakage current of 1 pA or less at the depletion voltage. We tested the detector with both a discrete preamp and an ultralow-noise front-end application-specific integrated circuit (ASIC). The front-end ASIC, developed at Brookhaven National Laboratory, was designed for low-capacitance detectors but had not been previously tested with a detector. Here, we discuss the detector design, the experimental setup, and the resulting detector performance. Using radioactive laboratory sources, we measure a full-width at half-maximum (FWHM) of 211 ± 8 eV at 5.9 keV with the ASIC and are able to set the threshold as low as 0.6 keV. [ABSTRACT FROM AUTHOR]

This article presents the design and evaluation of the first cryogenic switched capacitor array (SCA)-based waveform digitizer (CryoSCA) for HPGe detectors for low-background physics experiments. The chip has integrated 16 channels and was fabricated using a 0.18- $\mu \text{m}$ CMOS process with modified BSIM3v3 model parameters at 77 K. Each channel employs two 32-cell sample blocks working in the ping–pong mode, a 256-cell storage array, 32 parallel Wilkinson-type ADCs with 12-bits dynamic range, and registers. The chip was fully evaluated and showed promising performance at 300 K and 77 K. The measured power consumption of each channel increased from 3.3 mW at 300 K to 3.6 mW at 77 K. The averaging integral nonlinearity (INL) over 1–V dynamic range was measured to be 0.3% and 0.2% at 300 K and 77 K, respectively. The static noise decreased from 0.8 mV at 300 K to 0.6 mV at 77 K. The leakage current decreased from 18.2 fA at 300 K to 2.2 fA at 77 K. [ABSTRACT FROM AUTHOR]

A GaN alpha-particle detector of p-i-n structure was fabricated on a sapphire substrate in this article. The intrinsic layer of the detector was isoelectronic Al-doped GaN with the thickness of $10~\mu \text{m}$. The leakage current of the detector remained below 10 pA when the reverse voltage increased from 0 to 40 V, which proved that it had a better crystal quality than the detector based on undoped i-GaN layer, of which the dark current was 10 nA at −40 V. The carrier concentration derived from the 1/ $C^{2}$ – $V$ curve was $4.96\times 10^{14}$ cm−3, so the i-GaN layer would be fully depleted at −48 V. With the remarkable improvement of electrical properties, the charge collection efficiency (CCE) of the full depleted detector in this article was as high as 99%, while the energy resolution was about 4%. These results reveal the excellent prospect of GaN-on-sapphire for cost-effective alpha-particle detectors. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized through changes in ring oscillator (RO) frequencies and current as a function of $V_{\mathrm {DD}}$ to model delay and power degradations in digital circuits. At the 7-nm node, tests show that gate delay decreased, and power consumption increased as TID increased. Percent increase in parameter degradations shows an inverse relationship with supply voltage, while percent increase in power consumption shows a direct relationship with supply voltage. Annealing at room temperature did not affect degradations. Circuit-level degradations for the 7-nm technology were less than 1% after TID exposure of 380 krad(SiO2). These TID exposure results will provide insight to designers about circuit-level parameters of interest concerning the 7-nm technology node. [ABSTRACT FROM AUTHOR]

Integrated circuits sensitive to both total ionizing dose (TID) and displacement damage (DD) effects can exhibit degradation profiles resulting from a combination of degradation mechanisms induced by both effects. This work presents circuit simulations based on experimental data to explain degradation mechanisms induced by combined TID and DD effects on a bipolar IC current source. First, the effect of the degradation of each internal transistor on the circuit’s response is evaluated by applying electrical parametric changes. Then simulations are performed from different degradation scenarios based on observed circuit behaviors to reproduce the different TID, DD, and combined TID–DD responses. These simulations show that a synergistic interaction between a current leakage induced by DD on a transistor located in the bandgap reference part with the gain degradation of a current mirror induced by both TID and DD appears to be responsible for the combined TID–DD response. It is also shown that the circuit degradation rate depends on the DDD/TID rate ratios encountered during the exposition. [ABSTRACT FROM AUTHOR]

This article investigates the total ionizing dose (TID) degradation mechanisms of 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs with several channel lengths are irradiated up to 1 Grad(SiO2) and then annealed for 24 h at 100 °C. Irradiated devices show significant degradation in transconductance and OFF-state leakage currents with slight subthreshold stretch-out and negligible threshold voltage shifts. At doses up to 10 Mrad(SiO2), the TID response is dominated by positive trapped charges in the shallow trench isolation (STI). At ultrahigh doses approaching 1 Grad(SiO2), dc static measurements suggest generation of trapped charge at the STI/Si interface and/or at the corner between the STI and the gate dielectric. The TID sensitivity depends on the bias condition and channel length. Halo implantations fortuitously increase the radiation tolerance of short-channel FinFETs due to the increased channel doping caused by the overlap of the source and the drain halos. The worst degradation is found when a high electric field is applied to the gate during irradiation. [ABSTRACT FROM AUTHOR]

This article investigates the effect of ultra-high total ionizing dose up to 450 Mrad(SiO2) on 180-nm MOSFETs for analog applications. In particular, it studies the influence of the transistor size, design, type, bias, and the annealing on radiation-induced degradation. It studies the radiation effects on three parameters: the drive current, the threshold shift, and the leakage current. First, it reveals radiation-induced short-channel effects (RISCEs), which were until now only observed on more advanced technology nodes, and highlights that its mechanism of apparition differs from these advanced nodes. Second, it highlights the importance of bias during irradiation, not only on the magnitude of these effects but also on the type of defects at their origin. In particular, it demonstrates that the bias during irradiation plays a major role in the n-MOS–p-MOS dissymmetry. Third, it points out the capacity of the ELT and the butterfly rad-hard designs to mitigate the radiation-induced narrow channel effect (RINCE), the LPT, and several other radiation-related issues. Finally, it shows that the 3.3-V designs, compared to the 1.8-V designs, present a larger sensibility to radiation due to their thicker gates, but that they could stay a better choice for analog applications up to 400 Mrad(SiO2), thanks to their larger voltage range. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes. [ABSTRACT FROM AUTHOR]

Total ionizing dose response of 14-nm bulk-Si FinFETs has been studied with a specially designed test chip. The radiation testing shows evidence of interface trap build-up on 14-nm Bulk FinFET technologies. These defects created in the isolation layer give rise to a new radiation-induced leakage path which might lead to a reliability issue in CMOS technologies at or below the 14-nm node. TCAD simulations are performed and an analytical model for TID-induced leakage current is presented to support analysis of the identified TID mechanism. TCAD simulation and analytical model results are consistent with the experimental data. [ABSTRACT FROM AUTHOR]

This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of ${n}$ MOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual ${n}$ MOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the drain leakage current. We introduce a semiempirical physics-based approach using only three parameters to model the parallel parasitic and total drain leakage current as a function of TID. Taking into account the gate independence of the drain leakage current at high TID levels, we model the lateral parasitic device as a gateless charge-controlled device by using the simplified charge-based Enz–Krummenaker–Vittoz (EKV) MOSFET model. This approach enables us to extract the equivalent density of trapped charges related to the shallow trench isolation oxides. The adopted simplified EKV MOSFET model indicates the weak inversion operation of the lateral parasitic devices. [ABSTRACT FROM AUTHOR]

A 12-bit 40kS/s successive approximation register analog-to-digital converter (ADC) designed with a dummy gate-assisted (DGA) n-MOSFET is presented for space applications requiring high resolution, low power consumption, and moderate conversion speed. Additionally, a custom-designed metal finger capacitor and a body-tied p-MOSFET protected by guard ring in a bootstrapping circuit were used to mitigate the performance degradation caused by radiation-induced leakage current. The designed ADC was fabricated in a commercial standard 0.35 \mu \mathrm m CMOS process. In order to evaluate its radiation hardness, the fabricated ADC was exposed to 60Co gamma rays with a dose of up to 300krad (Si). The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) were 67.9dB and 78.7dB, respectively. Although a small amount of degradation of the SNDR was observed after radiation exposure, it corresponds to only about a 0.1 effective-number-of-bit (ENOB) drop from the measured result of an unirradiated chip. [ABSTRACT FROM PUBLISHER]

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- V\textit {th} transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and V\textit {th} , while the low- V\textit {th} transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( V\textit {gs}=V\textit {dd} ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- V\textit {th} transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics. [ABSTRACT FROM PUBLISHER]

This paper studies the effects of neutron radiation on the electrical behaviour and leakage current mechanism of quantum dot-in-a-well (DWELL) semiconductor diodes with fluence ranging from 3 to 9 \times 10^13~\neutron/cm^2. After neutron irradiation, the forward bias and reverse bias leakage currents showed significant rise approximately of up to two orders of magnitude which is believed to be attributed to the presence of displacement damage induced traps. The ideality factor of the forward bias leakage current corresponding to all neutron fluence irradiations were found to be close to 2, suggesting that the forward bias current mechanism is largely due to trap-assisted generation-recombination (TAGR) of carriers. Subsequently, it is also observed that the capacitances reduced after irradiations which were further shown to be due to the deep carrier trapping effects and the Neutron Transmutation Doping effects (NTD). From the temperature dependence measurements, it is found that the reverse bias leakage current mechanisms of the irradiated samples are primarily attributed to two process; TAGR of carriers with emission from the traps assisted by the Frenkel-Poole (F-P). The traps due to both mechanisms were derived and shown to increase with neutron fluence. [ABSTRACT FROM AUTHOR]

The total ionizing dose response of Ge channel pFETs with raised Si0.55Ge0.45 source/drain is investigated under different radiation bias conditions. Threshold-voltage shifts and transconductance degradation are noticeable only for negative-bias (on state) irradiation, and are mainly due to negative bias-temperature instability (NBTI). Nonmonotonic leakage changes during irradiation are observed, which are attributed to the competition of radiation-induced field transistor leakage and S/D junction leakage. [ABSTRACT FROM PUBLISHER]

Flash memory is an essential part of systems used in harsh environments, experienced by both terrestrial and aerospace TID applications. This paper presents studies of COTS flash memory TID hardness. While there is substantial literature on flash memory TID response, this work focuses for the first time on 1.5 transistor per cell flash memory. The experimental results show hardness varying from about 100 krad(Si) to over 250 krad(Si) depending on the usage model. We explore the circuit and device aspects of the results, based on the extensive reliability literature for this flash memory type. Failure modes indicate both device damage and circuit marginalities. Sector erase failure limits, but read only operation allows TID exceeding 200 krad(Si). The failures are analyzed by type. [ABSTRACT FROM PUBLISHER]

The alpha spectroscopy performance and electric current stability of 4H-silicon carbide Schottky devices with 50~\mu \m epitaxial layer was examined at temperatures between 300 to 500 K at 50 K intervals. An activation energy of 5.98 \pm 0.64~\meV was extracted from temperature dependent resistivity measurements. The Schottky barrier height decreases from 1.33 eV at 300 K to 1.11 eV at 500 K and the ideality factor increases from 1.17 at 300 K to 1.79 at 500 K. The reverse bias leakage currents stabilizes faster at higher temperatures. The charge collection efficiency is above 90% for temperatures up to 500 K. Pulse height spectra collected for 24 hours at constant voltage and temperature show improvements with time within the first 8 hours and remained stable for the remainder of the acquisition time. The peak width of the alpha spectra reduces significantly with increasing temperature at applied bias voltages below 50 V, which indicates that leakage currents are not the limiting factor in those conditions even at 500 K in our set up. So far, the devices indicate reasonable stability for extended periods of operation and highlight possible applications in harsh radiation media. [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) response of bulk FinFETs is investigated for various geometry variations, such as fin width, channel length, and fin pitch. The buildup of oxide-trapped charge in the shallow trench isolation turns on a parasitic transistor, leading to increased leakage current (higher IOFF.) The TID-induced degradation increases with decreasing fin width. Transistors with longer channels degrade less than those with shorter channels. Transistors with large fin pitch degrade more, compared to those with narrow fin pitch. TCAD simulations are used to analyze the buildup of trapped charge in the trench isolation oxide and its impact on the increase in leakage current. The strong influence of charge in the STI in narrow-fin transistors induces a parasitic leakage current path between the source and the drain, while in wide-fin devices, for the same amount of trapped charge in the isolation oxide, the subsurface leakage path is less effective. [ABSTRACT FROM PUBLISHER]

We propose a TID effect hardening strategy for nanoscaled ultra-thin BOX and body SOI technologies. Experiments performed on NMOS and PMOS transistors demonstrate that TID effects can be mitigated by applying a dynamic back-bias technique. These data are used to calibrate the back-bias that has to be applied on UTSOI transistors to efficiently mitigate TID-induced effects. Elementary circuit cells made of inverters are then modeled using dedicated mixed TCAD calculations in order to validate the proof of concept of this hardening strategy at circuit level. Finally, results obtained on Ultra-Thin BOX devices typical of future FDSOI technologies show that the proposed hardening strategy efficiency increases with BOX thinning and then with technology downscaling. [ABSTRACT FROM PUBLISHER]

Silicon transistor test vehicles used in infrared detectors were exposed to total dose at cryogenic temperatures. We present the degradation of the leakage current and threshold voltage of different transistor topologies at different dose rates and temperatures. The results show that the degradation occurs in the lateral parts of the transistors. Moreover, a different degradation was observed at 83 and 108 K. The higher temperature corresponds to the higher degradation; this can be explained by a more efficient hole transport process at these temperature. Measurements during the warming process of the devices show that a competition exists between the hole transport and their annealing, suggesting that a worst case of degradation could be found between nitrogen and room temperature. [ABSTRACT FROM PUBLISHER]

Tunnel-Diode Body-Contact (TDBC) SOI MOSFETs utilize a shallow source and a deep drain to eliminate total-ionizing-dose induced back-channel leakage and to suppress floating body effects. In contrast, significant leakage current is observed in T-gate Body-Contact (TB) SOI nMOSFETs, as a result of trapped charge in the buried oxide. A subthreshold hump is observed in TDBC SOI nMOSFETs after irradiation. The charge trapped at the shallow trench isolation (STI) corner is the major reason for the post-irradiation hump in the current-voltage characteristics. Pocket p^ + implantation reduces the size of the subthreshold hump in short-channel TDBC devices. [ABSTRACT FROM PUBLISHER]

Lasers and photodiodes for high luminosity large Hadron collider (HL-LHC) data transmission applications were irradiated with a 1-Gy dose of ^60\Co gammas. No change was observed in the performance of the lasers tested, and an order of magnitude increase in the leakage current of the InGaAs photodiodes was measured. [ABSTRACT FROM AUTHOR]

Additional evidence is presented and discussed on the mechanism for the subthreshold leakage currents induced in power MOSFETs by single nucleon and ion interactions. The new evidence excludes microdose in gate oxides and instead points to microdose in field/edge oxides. [ABSTRACT FROM AUTHOR]

The total-ionizing-dose (TID) radiation tolerance of bandgap references in deep-submicron CMOS technology is generally limited by the radiation introduced leakage current in diodes. An analysis of this phenomenon is given in this paper, and a dynamic base leakage compensation (DBLC) technique is proposed to improve the radiation hardness of a bandgap reference built in a standard 0.13 \mum CMOS technology. A temperature coefficient of 15 ppm/^\circC from -40^\circC to 125^\circC is measured before irradiation. The voltage variation from 0^\circC to 100^\circC is only \pm1 mV for an output voltage of 600 mV. Gamma irradiation assessment proves that the bandgap reference is tolerant to a total ionizing dose of at least 4.5 MGy. The output reference voltage exhibits a variation of less than 3% during the entire experiment, when the chip is irradiated by gamma ray at a dose rate of 27 kGy/h. [ABSTRACT FROM PUBLISHER]

The effect of space radiation on the reliability of microelectromechanical systems (MEMS) devices is an important consideration for future upper atmosphere and space applications. MEMS capacitors with insulator materials of silicon nitride (\ Si3{\ {N}}4), silicon oxide (\ SiO2), and ultrananocrystalline diamond (UNCD) were selected for radiation and leakage current studies. Leakage current was used as a measure of insulator performance and reliability, and is suggested here as a method to detect charge trapping, which also affects reliability. UNCD capacitors were orders of magnitude leakier than \ Si3{\ {N}}4 and \ SiO2, with \ Si3{\ {N}}4 being leakier than \ SiO2. \ SiO2 devices exhibited unstable leakage current with accumulated electric field stress, and were not utilized in radiation studies. \ Si3{\ {N}}4 capacitors exhibited leakage current decay (with a time constant of 190 s) under constant voltage stress above 2 MV/cm due to charge injection from the electrodes and trapping in the insulator. \ Si3{\ {N}}4 and UNCD capacitors were more sensitive to ionizing gamma radiation than to displacement damage from fast neutrons. Both \ Si3{\ {N}}4 and UNCD devices survived total doses of radiation representative of 20–100 years in the Van Allen radiation belts with 4 mm Al equivalent shielding. Capacitor equivalent circuit and resistor capacitor (RC) circuit charging models are developed to explain leakage current behavior of \ Si3{\ {N}}4 capacitors subjected to constant voltage stress and/or irradiation. In situ monitoring of \ Si3{\ {N}}4 capacitors placed next to the nuclear reactor core did not yield any single event effects at electric field strength of 1 MV/cm with a fast neutron fluence of 2\times 10^12\ \ n/cm^2. \ Si3{\ {N}}4 MEMS capacitors appear best suited for upper atmosphere and space applications with their relatively low leakage current (low power consumption) and apparent radiation hardness. [ABSTRACT FROM PUBLISHER]

A self-adjusting resistor unit is described that stabilizes the bias voltage of a semiconductor detector, while always keeping the parallel thermal noise of the bias resistor significantly below the detector shot noise. The user is exempted from adjusting the bias resistor to the detector leakage current for achieving optimum operating conditions. Moreover, the unit avoids the drop of the operation voltage on the detector when the reverse current increases up to several orders of magnitude without any further intervention. The self-adjusting unit can lead to a significant extension of the time of operation of the detector under stable conditions. [ABSTRACT FROM PUBLISHER]

A dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout was evaluated to demonstrate its effectiveness at mitigating radiation-induced leakage currents in a conventional n-MOSFET. In the proposed DGA n-MOSFET layout, radiation-induced leakage currents are settled by isolating both the source and drain from the sidewall oxides using a p+ layer and dummy gates. Moreover, the dummy gates and dummy Metal-1 layers are expected to suppress the charge trapping in the sidewall oxides. The inherent structure of the DGA n-MOSFET supplements the drawbacks of the enclosed layout transistor, which is also proposed in order to improve radiation tolerance characteristics. The Vg-\rm Id simulation results of the DGA n-MOSFET layout demonstrated the effectiveness of eliminating such radiation-induced leakage current paths. Furthermore, the radiation exposure experimental results obtained with the fabricated DGA n-MOSFET layout also exhibited good performance with regard to the total ionizing dose tolerance. [ABSTRACT FROM PUBLISHER]

We present an Application Specific Integrated Circuit (ASIC) for high resolution X-ray spectrometers (XRS) in radiation harsh environment (such as Jovian system). The ASIC was designed to read out signals from low resistivity pixelated Silicon-Drift-Detectors (SDD) to ensure radiation hardness. The readout is done by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW and provides 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, pile-up rejection, and peak detection with analog memory. The readout is sparse and based on a custom low-power tri-stable low-voltage differential signaling digital interface. A unit of 64 SDD pixels, read out by four ASICs, covers an area of 12.8 cm^2, and dissipates less than 20 mW/cm^2. The ASICs were powered on and irradiated using a beam line with 203 MeV protons, to total doses ranging from 0.25 Mrad to 12 Mrad. Performance degradation due to radiation-induced leakage current was observed to peak around 2 Mrad dose. Critical contributors to the degradation were identified through simulation and measurements, and corresponding circuitry was thus modified to address the issues. Measurements on the radiation-resistant design have shown excellent radiation resistance at total doses ranging from 1 to 8 Mrad. [ABSTRACT FROM PUBLISHER]

This paper describes the fabrication and initial characterization of an ultra-thin silicon PIN detector using a new technique in silicon nanotechnology. In collaboration with the Nuclear Physics Division and the Lund Nano Lab at Lund University, we have developed and manufactured ultra thin \Delta E-detectors for spectroscopic applications. The fabrication process has been carried out using a double-polished silicon substrate n-type wafer and locally thinning by means of a 10:1 solution of 25% tetramethyl ammonium hydroxide (TMAH) with Isopropyl alcohol. More than 100 detectors of different thicknesses, down to 5 \mum with active areas ranging from 0.71 to 0.172 mm^2, have been fabricated. The main design considerations of our thin detectors were a very low leakage current below 12 nA and a low full depletion voltage at a reverse bias less than 1.5 V. Finally, most of our thin detectors offer an energy resolution (FWHM) as low as 31 keV for 5.487 MeV alpha particles from a ^241Am source. [ABSTRACT FROM PUBLISHER]

This paper presents an investigation of Total Ionizing Dose (TID) induced dark current sources in Pinned PhotoDiodes (PPD) CMOS Image Sensors based on pixel design variations. The influence of several layout parameters is studied. Only one parameter is changed at a time enabling the direct evaluation of its contribution to the observed device degradation. By this approach, the origin of radiation induced dark current in PPD is localized on the pixel layout. The PPD peripheral shallow trench isolation does not seem to play a role in the degradation. The PPD area and a transfer gate contribution independent of the pixel dimensions appear to be the main sources of the TID induced dark current increase. This study also demonstrates that applying a negative voltage on the transfer gate during integration strongly reduces the radiation induced dark current. [ABSTRACT FROM AUTHOR]

An analysis of charge pump design for improved radiation tolerance of phase locked loops is presented. Two radiation-hardened-by-design approaches are considered to mitigate the total ionizing dose damage of the circuit, and a thick-film SOI SiGe process technology has been used to reduce charge collection of single event strikes. The results show that a modified design approach to implement the charge pump using SiGe HBTs can provide advantages in radiation tolerance to improve tri-state leakage performance, particularly for missions expecting large accumulated doses. [ABSTRACT FROM PUBLISHER]

It was demonstrated that several kinds of permanent damage were introduced by heavy ions in AlGaN/GaN HEMTs similar to SiC devices. A new mode of damage attributable to the transistor structure was also identified in addition to the damage observed similarly in SiC devices. [ABSTRACT FROM PUBLISHER]

Neutron-induced charge collection data and computer simulations presented here show that the presence of high-Z materials, like tungsten, can increase the single event upset (SEU) and multiple cell upset (MCU)cross sections of high critical charge (Qcrit) devices exposed to the terrestrial neutron environment because of interactions with high energy (> 100~\ MeV) neutrons. Time-of-flight data and computer simulations presented here demonstrate that 14 MeV neutrons do not produce highly ionizing secondary particles. Thus, 14 MeV neutrons can only simulate the SEU response of 65 nm SRAM devices in the terrestrial neutron environment for devices with a Qcrit < 27~\rm fC, and can simulate the 2-bit MCU response to within a factor of two only for very low Qcrit devices, < 1.2~fC.Additionally, it is shown that 14 MeV neutrons cannot adequately simulate the 3 or more bit MCU response for typical 65 nm SRAM devices. [ABSTRACT FROM PUBLISHER]

The effects of 10-keV and 400-keV endpoint-energy bremsstrahlung x-rays have been studied using the Monte Carlo simulator, MRED, for MOS capacitors with HfO2 gate dielectrics and TiN and TaN metal gates. We compute the reduction in dose that occurs for 10-keV x-ray irradiation of thin HfO2 gate dielectrics sandwiched between the metal gate and the Si substrate. We quantify the effects of back-end-of-line metallization layers, including copper interconnects, W vias, and borophosphosilicate glass (BPSG) and SiO2 passivation layers for low and medium energy x-rays. For thick metallization stacks irradiated by 10-keV x-rays, dose enhancement or attenuation can occur, depending on material type and overlayer thicknesses. For similar stacks irradiated with 400-keV endpoint-energy bremsstrahlung x-rays, significant dose enhancement is observed. [ABSTRACT FROM PUBLISHER]