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During the last decade optical sensor technologies have attracted increased attention for various applications. Plasmon-based optical sensor concepts for the detection of refractive index changes that rely on propagating surface-plasmon polaritons at metal-dielectric interfaces or on localized plasmons in metallic nanostructures prove their potential for these application due to their fast detection speed, high specificity and sensitivities [1, 2]. Combining plasmonic structures directly with optoelectronic devices could enable a high level of integration, however, it represents a significant technological challenge to develop an on-chip solution for these concepts including the integration of sensor and detector components. Previous works demonstrated first approaches mainly for the integration of refractive index sensor components on wafer level [3, 4]. In [5] and [6] a proof-of-concept of a fully integrated on-chip solution with high sensitivities was presented, which can be easily combined with microfluidics [7] for potential applications in biosensing. In this concept, a nanohole array (NHA) was structured in a 100 nm thick aluminum layer on top of a vertical PIN germanium photodetector (GePD) with an intrinsic germanium sheet of 480 nm. This sensor concept relies on extraordinary optical transmission through the NHA [8]: Light transmission is only possible for narrow wavelength ranges determined by the NHA geometry which determine the transmission peaks at the resonance wavelength of the NHA. Thus, the NHA acts as a high quality wavelength filter. Due to the change in the refractive index, a material under test (MUT) contacting directly the surface of the NHA, provokes a shift of the wavelength maximum, which can be detected by measuring the photocurrent spectra of the GePD. While responsivities and sensitivities of (0 V) = 0.075 A/W and = 1200 nm/RIU could be attained in this proof-of-concept device [6, 7], the semiconductor device layers were deposited using molecular beam epitaxy (MBE). Furthermore the vertical PIN GePD was realized by a mesa procedure to enable large areas for top illuminated operations. These techniques are unsuitable for an industrial CMOS fabrication process with high throughput. Therefore, the development of a CMOS compatible technology process with low costs and high yields is an important step towards large-scale fabrication of this sensor concept. In this work we present the progress for the realization of a surface plasmon resonance (SPR) refractive index sensor in a 200 mm wafer Silicon based technology. One main challenge is the fabrication of a large area photodetector for top illuminated sensor devices. We developed a process, which is mainly based on the IHP electronic photonic integrated circuits (ePIC) technology [9]. This ePIC technology enables the production of waveguide coupled lateral PIN GePDs with high bandwidth and high responsivities [10]. However, these PDs are unsuitable for top illuminated applications because of their small germanium areas. Due to certain process conditions with respect to chemical mechanical polishing procedures there are limits for feasible large detector areas. Furthermore, large detector areas for lateral PIN GePDs would result in very low electric fields in the intrinsic zone where carriers are generated by photon absorption. Thus, very high voltages for reversed bias are necessary for sufficient carrier drifts. For the first time we have developed a modern detector design concept which is compatible to the IHP ePIC technology. This concept allows the realization of large area detectors of 1600µm² (40µm x 40µm) with optimized optical responsivities for top illuminated applications. The detector consists of several parallel connected lateral PIN GePDs. We designed different variations and varied Ge width and distance between neighboring GePDs in order to investigate process limits. The p- and n-doped regions were defined by dopant implantation using a photo resist mask. We used a finger-like design as implantation masks to enable one contact area for each p-doped and each n-doped region (Fig. 1). This contacting approach differs from the standard GePD offered in the IHP ePIC technology. We analyzed I-V characteristics in dependence of detector design and contacting scheme (Fig. 2). In addition, process adjustments for the optimization of the germanium quality were investigated to reduce dark currents and to improve optical responsivities (Fig.3). Titanium nitride (TiN) is very promising metallic alloy with respect to thickness homogeneity and low surface roughness. Therefore we used titanium nitride which was deposited by a sputtering process to develop plasmonic active NHA layers. Various process development runs were done to evaluate the NHA performance. Ellipsometry and atomic force microscope measurements were performed to characterize the quality of the TiN layer (Fig.4). Figure 1

In this paper, the development of a BiCMOS embedded TSV technology for mm-wave/sub-THz applications is demonstrated. Annular-type TSVs enable low loss TSV transitions up to 300 GHz. Back-to-back TSV transitions are fabricated and characterized from 220 to 325 GHz providing a low insertion loss of 0.83 and 0.94 dB at 240 and 300 GHz. Results show that BiCMOS embedded TSVs are very good candidates to provide RF transitions for mm-wave/sub-THz packaging and 2.5/3D heterogeneous integration solutions.

We present an SOI-waveguide coupled germanium photodiode with very high OE -3 dB bandwidth of ≥110 GHz at reverse bias of 2 V. This performance is achieved by a novel construction in that the germanium is sandwiched in between two in-situ doped silicon regions. This fabrication approach allows for avoiding ion-implantation into the germanium, which is certainly beneficial for the bandwidth as minority carrier diffusion effects are strongly suppressed. A responsivity of >0.6 A/W at 1550 nm (-2 V) is achieved, while the dark current of this device yields to about 300 nA (-2 V). To our knowledge, this is the most advanced germanium photo detector in terms of bandwidth combined with state-of-the-art responsivity as well as moderate dark currents. We demonstrate that the novel photodiodes can be fabricated with high yield.

In this paper, the latest developments of high performance SiGe BiCMOS technologies with additional WLP technology modules are demonstrated. The combination of HBTs with fmax values beyond 700 GHz together with WLP technology modules such as interposer, Through-Silicon Vias (TSVs) and wafer bonding techniques are explained. Both silicon interposer substrates with embedded TSVs together with a novel Al-Al wafer bonding integration technique are realized to provide a high performance and low-cost FOWLP platform for 3D heterogeneous integration.

International audience; In this work, the optimization of TSVs for SIWs embedded in a high-resistive silicon interposer is demonstrated. EM simulations are performed to analyze and optimize important TSV design parameters enabling silicon interposer technologies with low-loss SIWs working at mm-wave/THz frequencies. A silicon interposer using high resistive silicon and TSVs is fabricated and SIWs are characterized working from 110-170 GHz with very low attenuation of ~0.5 dB/mm.

Through Silicon Via (TSV) technology is a key in 3D integration of circuits by the creation of interconnects using vias, which go through the full silicon wafer. Typically, a highly-selective Bosch Si etch process is used. It is characterized by a high etch rate at a high aspect ratio, whereby scallops on the sidewalls are generated. In this work, square via arrays with dimensions from 3 to 50 μm and up to 300 μm depth were fabricated and analyzed by spectroscopic reflectometry. The reflectometric data are compared to simulations by a novel theoretical approach. In order to simulate the reflectance spectra of TSV arrays, a combination of 2D and 3D rigorous coupled wave analysis was applied. Besides the via depth, the sidewall angle and the corner radius of the bottom profile were considered in the model. The general requirements on spectral resolution in TSV metrology are discussed.Through Silicon Via (TSV) technology is a key in 3D integration of circuits by the creation of interconnects using vias, which go through the full silicon wafer. Typically, a highly-selective Bosch Si etch process is used. It is characterized by a high etch rate at a high aspect ratio, whereby scallops on the sidewalls are generated. In this work, square via arrays with dimensions from 3 to 50 μm and up to 300 μm depth were fabricated and analyzed by spectroscopic reflectometry. The reflectometric data are compared to simulations by a novel theoretical approach. In order to simulate the reflectance spectra of TSV arrays, a combination of 2D and 3D rigorous coupled wave analysis was applied. Besides the via depth, the sidewall angle and the corner radius of the bottom profile were considered in the model. The general requirements on spectral resolution in TSV metrology are discussed.

In this work, the development of a Through-Silicon Via process module for multi-project wafer SiGe BiCMOS and silicon interposer is demonstrated. The TSV technology based on a via-middle approach is optimized to provide TSV process and design flexibility which is required for a multi-project wafer service. Different passive and active TSV-based components like a low-noise amplifier, RF interposer transmission lines and substrate-integrated waveguides are fabricated. The TSV process module enables a wide range of promising new applications by adding additional functionalities to conventional BiCMOS and interposer substrate technologies.

The development of a Through-Silicon Via process module within a high performance SiGe BiCMOS technology is demonstrated. The TSV technology module including both the TSV fabrication process itself, the temporary wafer bonding for BiCMOS thin wafer handling and the thin wafer backside processing is developed on 8-inch wafer level and the optimization of the different process steps are explained. This process module is fully compatible with the qualified SiGe BiCMOS technology environment which enables very uniform and reliable TSV backside fabrication adding new functionalities into IHPs high performance SiGe BiCMOS technologies applicable for thin wafer applications and 3D heterogeneous integration.

In this work, the development of engineered silicon substrates for a novel via-middle TSV integration concept is demonstrated. These substrates include 3D buried etch-stop layers which provide both an ideal vertical and lateral etch-stop for TSV trench etching thus enabling the simultaneous realization of different size of TSVs on the same silicon substrate. Beside standard BiCMOS and TSV fabrication steps, only a low-temperature fusion bonding process is applied and the integration concept is realized without adding an additional mask to the established BiCMOS via-middle TSV technology. As a result, the developed technique is very promising to realize different dimensions of TSVs on the same substrate for future smart system applications.

In this paper, a fully BiCMOS integrated microfluidic technology platform for Lab-on Chip (LoC) applications is presented. Fusion bonding and adhesive bonding techniques are applied to realize a 3-wafer-stack integration. A glass wafer is used on top of the BiCMOS wafer and the Si channel wafer to enable simultaneous optical and electrical measurements. An alignment accuracy of less than 1 µm between BiCMOS and channel wafer is achieved while having channel heights between 30 and 100 µm. All the microfluidic process integration steps are kept below 300 °C. The microfluidic inlet and the outlet are positioned on the backside of the wafer stack to provide both the optical inspection and the electrical measurements from the wafer's front side. The developed wafer level integration technique provides high throughput solutions for emerging chemical and biological LoC applications.

Through Silicon Via (TSV) technology is a key feature of new 3D integration of circuits by creation of interconnections using vias, which go through the silicon wafer. Typically, the highly-selective Bosch Si etch process, characterized by a high etch rate and high aspect ratio and forming of scallops on the sidewalls is used. As presented in this paper, we have developed an experimental setup and a respective evaluation algorithm for the control and monitoring of very high aspect ratio TSV profiles by spectroscopic reflectometry. For this purpose square via arrays with lateral dimension from 3 to 10 μm were fabricated by a Bosch etch process and analyzed by our setup. By exploiting interference and diffraction effects of waves reflected from the top and bottom surfaces as well as from the side walls of the TSV patterns, the measurements provided etch depths, CD values and scallop periods. The results were compared with data obtained by a commercial wafer metrology tool. Aspect ratios of up to 35:1 were safely evaluable by our setup.

An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an optimized vertical profile, an additional decrease of the base and emitter resistance which is made possible by combining millisecond annealing with a low-temperature backend, and from lateral device scaling.

The demand for the high-density integrated memories is growing along with the scaling of the transistor technology nodes. To fabricate the reliable devices in advanced technologies, optimization of several process steps is necessary [1]. The capacitor, which is commonly a MIM (Metal-Insulator-Metal) module finds its application as a basic storage device in memories, filters, voltage limiters etc. The MIM module is also considered as an integral part of memory technologies such as DRAM, FeRAM, and RRAM. The MIM modules should demonstrate reliable operation through better performance and efficiency. And, it is realized through the parameters related to MIM module such as, low leakage current, less variability with respect to capacitance, high quality factor Q, lower defect density, low parasitic capacitance and many others [2]. Reactive-ion-etching plays a very important role in BEOL integration of MIM devices. The MIM module is created by dry etching through the MIM stack. Related to RRAM (Resistive Random Access Memory) applications the MIM stack consists of an additional buffer layer such as Ti or Hf [3]. These layers are easily oxidizable and the etching step could oxidize them from the sidewalls. Also, the residuals of the metal if remain on the sidewall could lead to leaky devices. Hence, an etch process which is not well optimized could damage the devices and in turn pose a threat to their functionality and reliability [4]. An improved MIM stack etch process is beneficial to reduce the above-mentioned damages. Several techniques were used in the past to cover the MIM devices with dielectric materials like SiO2 and SiN, which protects the devices from further process steps involved in the fabrication procedure [5]. In this work we demonstrate the effect of the improved etch process with a combination of SiNO spacers and encapsulation techniques for TiN/Ti/HfO2/TiN stacks. This stack is most popularly used in RRAM and, in this work, it is integrated into the BEOL of the 250 nm CMOS technology at IHP. To test the performance of the devices, the MIM stack was fabricated in three different approaches. In the first approach, photoresist is used as a mask to etch the MIM stack, the second one uses TiN hard mask and the third one uses TiN hard mask etch in addition to creation of SiNO spacers after the TiN/Ti etch. The encapsulation of MIM modules with SiNO is implemented in all the three approaches mentioned above. Special device structures with the TiN/Ti/HfO2/TiN stack are fabricated to test the variability of the MIM parameters on the entire wafer. Additionally, the switching operation was tested by means of DC voltage sweeps on the MIM RRAM devices which includes, forming, reset and set steps followed by 50 cycles of reset and set processes. The devices associated with the improved fabrication process steps exhibited less variability in terms of leakage current, capacitance and Q-factor values along the entire wafer. This reduction in the variability of the parameters corresponding to the MIM devices could be used for emerging applications. References G.S. Kar, A.Fantini, Y.Y. Chen, V. Paraschiv, B. Govorenau, H. Hody, N. Jossart, H.Tielens, S. Brus, O. Richard, T. Vandeweyer, D.J. Wouters, L. Altimime, M. Jurczak, i n Symposium on VLSI Technology (VLSIT), 2012 IEEE, pp. 157-158 E. Pérez, A. Grossi, C. Zambelli, M. K. Mahadevaiah, P. Olivo, and Ch. Wenger, in MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), 2018 IEEE, pp. 1-3 E. Pérez, M. K. Mahadevaiah, C. Zambelli, P. Olivo, and Ch. Wenger, Solid-State Electronics, (2019) V. B. Naik, J. H. Lim, K. Yamane, D. Zeng, H. Yang, N. Thiyagarajah, J. Kwon, N. L. Chung, R. Chao, T. Ling, K. Lee, in International Reliability Physics Symposium (IRPS), 2019 IEEE, pp. 2C-2 Y.S. Chen, H.Y. Lee, P.S. Chen, P.Y. Gu, W.H. Liu, W.S. Chen, Y.Y. Hsu, C.H. Tsai, F. Chen, M.J. Tsai, and C. Lien, Electron Device Letters, Vol. 32, Issue: 3, pp 390-392 (2011)

The high-frequency performance of a novel SiGe heterojunction bipolar transistor (HBT) module with monocrystalline base link is investigated in an industrial 0.13- $\mu \text{m}$ BiCMOS environment. The main feature of this new HBT module is a significant reduction of the external base resistance as shown here by direct comparison with a conventional double-poly-silicon technology. Peak $f_{\mathrm { {T}}}/f_{\mathrm { {max}}}$ values of 300/500 GHz are achieved. A minimum current-mode logic ring oscillator gate delay of 1.8 ps and a record operation frequency for a SiGe static frequency divider of 161 GHz are demonstrated.

Through-silicon via (TSV) technology is a key feature for 3D circuit integration. TSVs are formed by etching a vertical via and filling them with a conductive material for creation of interconnections which go through the silicon or silicon-on-insulator (SOI) wafer. The Bosch etch process on Deep Reactive Ion Etching (DRIE) is commonly used for this purpose. The etch profile defined by the critical dimensions (CDs) at the top and at the bottom, by the depth and by the scallop size on the sidewall needs to be monitored and well controlled. In this work a nondestructive 3D metrology of deeply-etched structures with an aspect ratio of more than 10 and patterns with lateral dimensions from 2 to 7 μm in SOI wafer is proposed. Spectroscopic reflectometry in the spectral range of 250-800 nm using a production metrology tool was applied. The depth determinations based on different algorithms are compared. The Pearson correlation coefficient between measured and calculated reflection is suggested as the most appropriate method. A simple method for top CD evaluation is proposed by the measurement of reflection and using the polynomial approximation of reflection versus TSV filling coefficient which is determined as ratio of CD to pitch. The 3D RCWA simulations confirm this dependence.

Different MEMS process techniques have been integrated to 0.25 µm BiCMOS process for embedded system applications. Back-End-Off-Line (BEOL) integration technique was developed using standard metallization layers of BiCMOS process with additional MEMS process steps. As an example, an RF-MEMS capacitive switch was realized using BEOL embedded MEMS module. Back-side substrate etch method was developed as another MEMS integration technique. This technique is demonstrated by several high-Q passive components which can prevent from substrate losses and on-chip antennas/sensors for multi-GHz applications. Lastly, thick copper metallization with low-k BCB dielectric material was developed and processed on top of BiCMOS BEOL. It provides 2 additional thick copper metallization layers and allows realizing high-Q passives and on-chip THz resonators. Several design examples realized by using developed MEMS modules and processing techniques were also analyzed.

The formation of a Through Silicon Via (TSV) includes a deep Si trench etching and the formation of an insulating layer along the high-aspect-ratio trench and the filling of a conductive material into the via hole. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling of the signal to the silicon. The importance of the oxide thickness on the via wall isolation can be verified using electromagnetic field simulators. To satisfy the needs on the Silicon dioxide deposition, a sub-atmospheric chemical vapor deposition (SA-CVD) process has been developed to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides excellent step coverage of the 100 microm depth silicon trenches with the high aspect ratio of 20 and more. The developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key factor for the performance of TSVs for mm-wave 3D packaging.

SiGe p-n-p heterojunction bipolar transistors (HBTs) are presented with f T /f max values of 175 GHz/265 GHz and a minimum current mode logic ring oscillator gate delay of 3.65 ps. The devices are fabricated in an experimental p-n-p 0.25-μm BiCMOS process environment adopting the transistor design of an advanced n-p-n HBT module. The improved RF performance compared with previously reported p-n-p HBTs was enabled by low-temperature disilane-based epitaxial processes, careful base-profile engineering, the realization of low-ohmic collector and emitter layers, and by avoiding thermal treatments higher than 650 °C between base epitaxy and final RTP.

A 0.13 μm SiGe BiCMOS technology for millimeter-wave applications is presented. This technology features high-speed HBTs with peak transit frequencies fT of 240 GHz, maximum oscillation frequencies fmax of 330 GHz, and breakdown voltages BVCEO of 1.7 V along with high-voltage HBTs (fT = 50 GHz,fmax = 130 GHz, BVCEO = 3.7 V) integrated in a dual gate oxide RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators with fundamental-mode oscillation frequencies above 200 GHz are demonstrated.

The process of epitaxial SiGe layers are getting attractive as they offer a variety of advanced microelectronics devices compatible with silicon processing technology [1-3]. The large research effort of the last decade has focused on the growth of high quality strained SiGe layers. In particular, SiGe superlattice containing high Ge concentration is demanded in order to improve performances of the devices. Recently, IHP has achieved a significant breakthrough in SiGe/Si MQW processing technology [4]. The developed high quality of superlattice of SiGe/Si MQW structure containing 50% Ge has been successfully processed (Fig. 1) and presented as a potential thermistor material with its high performance for uncooled microbolometer applications [5]. The prototype of thermistor device with 50% Ge in SiGe wells exhibited an outstanding TCR of -5.5 %/K and a K1/f value of 3.4 × 10-15 for 200 µm× 200 µm pixel size, respectively, showing a concurrent achievement of a very high TCR and a low 1/f noise performance. One of the main challenge of SiGe/Si MQW structures is the high resistance values including high Ge concentration makes it difficult to integrate as a detector material in a complete microbolometer device. Large pixel resistances cause not only high noises and hence lower sensitivity but also a challenge to design and maximize the performance of the ROICs [6, 7]. A method to optimize and tune the resistance of the detector material in microbolometers is in-situ doping of quantum well layers in order to enhance the combined detector and ROIC performance. In [8], Boron (B) doping level in SiGe quantum wells are optimized in order to keep the pixel resistance of the thermistor in acceptable values for an ROIC design. B doping of SiGe MQWs is used for the resistance tuning of the detector. The main challenge of the method is simultaneous achievement of enough doping in the SiGe region of the MQWs while keeping the barrier intrinsic silicons non-doped. The initial pixel resistance of 3 period of SiGe/Si MQWs with 50% Ge concentration of 21 MΩ is reduced 210 kΩ for 25 × 25 µm2 pixel size by the optimization of in-situ B doping level in SiGe layers of the MQW stack [8]. The optimized B doping density of ~1 × 1018 cm-3 in SiGe wells did not cause any significant change in the TCR value whereas the 1/f noise performance is even enhanced due to the in-situ doping process. All the aforementioned results shows the successful demonstration of intrinsic thermistor based on SiGe/Si MQWs including 50% Ge with an acceptable pixel resistances. Although the successful demonstration of SiGe MQWs has been performed for high performance microbolometer applications, a full integration of the high performance SiGe/Si MQW based detector into a standard CMOS process is still challenging. SiGe/Si MQW process requires higher temperatures than the temperature budget of the post processing of CMOS process. Therefore, the transfer of the optimized detector structure to a CMOS/BiCMOS wafer needs a special layer transfer process (i.e. wafer bonding). More critically, due to the vertical working principle mechanism of the detector device, there is a challenge for full integration of the optimized detector structure into standard BiCMOS process because the suspended detector device needs to be contacted by both sides In this work, the recent progress on SiGe/Si type high performance detector structures will be presented. The process optimization of the detector by means of high TCR, low 1/f noise and appropriate resistance will be detailed. The method of integrating the developed SiGe/Si MQW structures into a 130 nm BiCMOS process will be provided. The integration method is based on the oxide-oxide fusion bonding of ROIC and detector wafer followed by post processing of the bonded wafer stack. The details of thermal conductance optimization of the microbolometer together with the mechanical stress optimization, required for the suspended detector device, will also be given. Finally, the low-pressure hermetic packaging of the microbolometer structure will also be proposed. Figure 1

This paper describes the technology development activities within the European funding project DOTSEVEN done by Infineon and IHP. After half of the project duration Infineon has developed a 130 nm SiGe BiCMOS technology with f T of 250 GHz and f max of 370 GHz. State-of-the-art MMIC performance is demonstrated by a 77 GHz automotive radar transmitter. The suitability of IHP´s advanced SiGe HBT module with epitaxial base link for future industrial BiCMOS platforms is demonstrated by integrating it in Infineon's 130 nm process resulting in an f max of 500 GHz, 1.8 ps gate delay and a record 161 GHz static frequency divider. IHP has achieved an f max of 570 GHz for the first time using an HBT concept with non-selective epitaxial base deposition and an elevated extrinsic base.

This paper presents a process technology for cost-effective integration of low-power flash memories into a [email protected], high performance SiGe:C RF-BiCMOS process. Only four additional lithographic steps are used on top of the baseline BiCMOS process, leading to in total 23 mask levels for the BiCMOS/embedded flash process. Uniform-channel Fowler-Nordheim programmable and erasable stacked-gate cells, suitable for medium density (~Mbit) memories, are demonstrated. Peripheral high-voltage transistors, with >10V breakdown voltage, are integrated without additional mask steps on top of the flash cell integration. The flash memory integration is modular and has negligible impact on the original CMOS and HBT device parameters.

Driven by new applications such as BiCMOS embedded RF-MEMS, high-Q passives, Si-based microfluidics for bio sensing and InP-Si BiCMOS heterointegration [1-4], accurate alignment between back and front side is highly desired. In this paper, we present an advanced back to front side alignment technique and implementation of it into the back side processing module of IHP’s 0.25/0.13 μm high performance SiGe:C BiCMOS technology. Using the Nikon i-line Stepper NSR-SF150, a new infrared alignment system has been introduced. The developed technique enables a high resolution and accurate lithography on the back side of the BiCMOS-processed Si wafers for additional backside processing, such as backside routing metallization. In comparison to previous work [5] with overlay values of 500 nm and the requirement of two-step lithography, the new approach provides significant improvement in the overlay accuracy with overlay values of 200 nm and a significant increase of the fabrication throughput by eliminating the need of the two-step lithography. The new non-contact alignment procedure allows a direct back to front side alignment using any front side alignment mark (Fig. 2), which generated a signal by reflecting the IR light beam. Followed by a measurement of the misalignment between both front to back side overlay marks (Fig. 3) using EVG®NT40 automated measurement system, a final lithography process with wafer interfield corrections is applied to obtain a minimum overlay of 200 nm. For the specific application of deep Si etching using Bosch process, the etch profile angle deviation across the wafer (tilting) has to be considered as well. From experimental data, an etch profile angle deviation of 8 μm across the wafer has been measured (Fig. 7). The overlay error caused by tilting was corrected by optimization and adjustment of the stepper offset parameters. All measurements of back to front side misalignment were performed with the EVG®40NT automated measurement system whereas the deep etch tilting errors were measured with an optical microscope using special vernier scales embedded in the backend-of-line metallization layer (Fig 4 and Fig. 5) of the IHP’s 0.25/0.13 μm SiGe:C BiCMOS technology. By applying the proposed method of back to front side alignment using infrared illumination alignment, the accuracy of backside fabrication processes like deep Si etching can be significantly improved. The developed technique is very promising to shrink the dimensions by minimizing the back to front side misalignment to improve the device performance of backside integrated components and technologies.

We review the development status of device integration in photonic BiCMOS technology. Basic photonic device performance and results of a first fully-integrated technology learning cycle shall be presented.

In this paper we demonstrate the modeling and optimization of BiCMOS embedded high aspect ratio through-silicon vias (TSV) for RF-grounding applications. The inductance and the resistance of the TSV are analyzed with respect to TSV design parameters and process effects such as sidewall-tilting and void formation. RF measurement results with extracted inductance and resistance of 24 pH and 86 mΩ for a single TSV are in very good agreement with the simulation results. Based on the simulated and measured results, RLC-lumped-element models are developed considering the aforementioned process characteristics to provide realistic models for Process-Design-Kit (PDK) implementation.

The research on millimeter-wave circuits is driven by applications such as radar imaging and wideband communications. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power, determined by the physical properties of silicon. For SiGe devices with transit frequencies of 180 GHz a breakdown voltage BVCEO of 2.0 V can be measured. The increase in breakdown voltage means always a decrease in transit frequency. On the other hand, silicon is the leading material of modern semiconductor technology. It offers a high level of integration density and yield. SiGe-HBT device speed has increased to hundreds of gigahertz, however limited in output power compared to III-V semiconductor devices. Thus, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs. Our approach combines a 3” InP-DHBT transferred-substrate process [1] with a SiGe-BiCMOS process [2]. At first, silicon and InP wafers are processed separately. The silicon wafer runs through the complete production process with front-end and back-end in a 0.25 µm BiCMOS process with a five metal layers aluminum/tungsten back-end using silicon dioxide as interlayer dielectric and an additional tungsten local interconnect. The back-end-process was specially adapted for the following wafer bond process by planarization of the topmost metal (TM2) level. The InP wafer has a semi-completed front-end and one metal level of gold and benzocyclobutene (BCB) as the dielectric. At this stage the front-to-front bond process is performed (see Fig. 1 a). The ground metallization (Gd) of the InP wafer is embedded in BCB to achieve a surface step height of less than 100 nm. Prior to wafer bonding both wafers are spin coated with BCB. After a BCB curing process the two wafers are aligned and bonded. After the bond process the InP substrate is etched by HCl to expose the InP-DHBT structures (see Fig. 1 a). The vias between the InP and SiGe-BiCMOS structures are formed by inductively coupled plasma (ICP) reactive ion etching (RIE) dry etching through the BCB using SF6. Then they are electrically connected using a gold electroplating process (see Fig. 1 b). To demonstrate the capabilities of the heterointegration scheme an integrated signal source at 164 GHz was designed and fabricated [3]. It is an example of the different combinations of BiCMOS and InP circuit building blocks. It is shown in Fig. 2. The source consists of a fundamental voltage-controlled oscillator (VCO) in BiCMOS technology (left side in Fig. 2) which is interconnected by an optimized high frequency via transition to a doubler-amplifier combination in InP technology (right side of Fig. 2). Recently, the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the impact on the BiCMOS devices is rather small. The forward Gummel plot of a SiGe-HBT before and after hetero integration is shown in Fig. 3. There is a slight increase of the base current at low emitter-base voltages caused by leakage currents due to electrostatic discharges in etching processes in the post bonding procedure. But these changes are marginal. Nevertheless, options to remove these effects are being discussed, such as moderate anneal sequences (the post-fabrication temperature is limited to below 250°C due to the presence of BCB) and modifications to the post-waferbonding plasma etch recipes. References [1] T. Kraemer, M. Rudolph, F.J. Schmueckle, J. Wuerfl, and G. Traenkle, IEEE Transactions on Electron Devices, 56 (9), (2009), pp. 1897 – 1903 [2] H. Rücker, B. Heinemann, and A. Fox, Proc. Silicon Monolithic Integrated Circuits on RF Systems (SiRF 2012), 133 (2012) [3] T. Jensen, T. Al-Sawaf, M. Lisker, S. Glisic, M. Elkhouly, T. Kraemer, I. Ostermay, C. Meliani, B. Tillack, V. Krozer, and W. Heinrich, EuMIC (2013), pp. 244-247

In this paper, modeling and characterization of BiCMOS embedded microfluidic platform for biosensing applications is presented. The novel process integration scheme with two bonded wafers provides microchannels, accessing to the inlets and the outlets as well as the mm-wave sensor easily. The developed microfluidic platform provides very flexible size of microchannels in BiCMOS chip and it is able to bring the fluid very close to the sensor. A fully integrated 120 GHz dielectric sensor has been used for the demonstration of the platform. The high reproducibility, micron size, high throughput and low-cost process make the presented BiCMOS integrated microfluidic channels as a key platform for bio and THz sensing applications.

A monolithically integrated 25Gbps receiver is shown as a demonstrator for a novel photonic BiCMOS process which allows for dense co-integration of 200GHz bipolar transistors and CMOS devices with waveguides, couplers, and Ge photodiodes.

The external surface of a hydrothermally treated H-ZSM-5 zeolite was studied with XPS and x-ray Auger electron spectroscopy. It was established that Al removed from tetrahedral framework positions migrated into the outermost layers and produced an Al enrichment. In order to get information on the acidic properties of the outermost layers and of extra-framework Al (EFAl), we investigated the XPS N 1s level of adsorbed ammonia. Two different Bronsted acid sites with N 1s binding energies of 402.3±0.5 and 401.2±0.2 eV, respectively, were found in the untreated H-ZSM-5 zeolite. A third acid site (398.8±0.3 eV) appeared after water vapour treatment, which is probably also a Bronsted acid site. The modified Auger parameter α′ was used for identification of the chemical state of EFAl. The removed Al maintained the tetrahedral coordination, was non-acidic, uncharged, partly soluble in concentrated acetic acid and able to block part of the acid sites. A comparison of acidity between the surface and bulk phase (temperature-programmed desorption results) clearly showed that Al is heterogeneously distributed in the framework. A large part of Al on the surface is not in a framework position and is blocked by EFAl. © 1997 by John Wiley & Sons, Ltd.

We present high-efficiency fiber-to-chip grating couplers with a coupling loss of about - 1.5dB only, whose structure and fabrication flow facilitate an easy integration in a high-performance, photonic BiCMOS process.

We present a novel double-polysilicon (DP) HBT technology with a SiGe:C base fabricated by selective epitaxial growth (SEG), in which the external base is formed by in-situ doped epitaxy completely after the internal base. This approach aims to achieve a lower parasitic base resistance compared to our previously reported DP-SEG technology [8], while keeping a low capacitive lateral base link arrangement. We demonstrate f T /f max of 310GHz/480GHz, as well as a CML gate delay of 1.9ps, achieving the lowest value reported so far.

A SiGe HBT technology featuring f T /f max /BV CEO =300GHz/500GHz/1.6V and a minimum CML ring oscillator gate delay of 2.0 ps is presented. The speed-improvement compared to our previous SiGe HBT generations originates from lateral device scaling, a reduced thermal budget, and changes of the emitter and base composition, of the salicide resistance as well as of the low-doped collector formation.

We demonstrate a novel back-side processed, back to front self-aligned BiCMOS embedded RF-MEMS switch for the 90 to 140GHz frequency band. The switch integration is very simple, adding only one mask step to the underlying high-performance BiCMOS process. Moreover, it offers low cost, wafer level packaging. The insertion loss of the switch is less than 0.5dB up to 140GHz, and isolation is better than 15dB in the frequency range of 90 to 140GHz. The switch-on time is measured as 10µs. No performance degradation was observed after 5 billion cold switching cycles demonstrating the high reliability of the switch. An on-chip charge-pump (CP) circuit is realized using enhanced PMOS transistor to excite the switch with an output voltage of up to 50V and a rise time of 2µs.

A 0.13 µm SiGe BiCMOS technology for millimeter wave applications is presented. This technology features high-speed HBTs (f T =240 GHz, f max =330 GHz, BV CEO =1.7 V) along with high-voltage HBTs (f T =50 GHz, f max =130 GHz, BV CEO =3.7 V) integrated in a dual-gate, triple-well RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators for frequencies above 200 GHz are demonstrated.

We present a double-polysilicon SiGe:C HBT module showing a CML ring oscillator (RO) gate delay tau of 2.5 ps, and fT/ fmax/BVCEo values of 300 GHz/350 GHz/1.85V. A key new feature of the HBT module is a connection of the extrinsic and intrinsic base regions by lateral epitaxial overgrowth. This facilitates simultaneously a very low base resistance and a reduced base-collector capacitance. In addition, the RF performance is enhanced for devices rotated by 45deg with respect to the standard orientation due to favorable epitaxial growth behavior.

The application of Double Exposure Lithography (DEL) would enlarge the capability of 248 nm exposure technique to smaller pitch. We will use the DEL for the integration of critical layers for dedicated applications requiring resolution enhancement into 0.13 μm BiCMOS technology. In this paper we present the overlay precision and the focus difference of 1st and 2nd exposure as critical parameters of the DEL for k1 ≤ 0.3 lithography (100 nm half pitch) with binary masks (BIM). The realization of excellent overlay (OVL) accuracy is a main key of double exposure and double patterning techniques. We show the DEL requires primarily a good mask registration, when the wafer stays in the scanner for both exposures without alignment between 1st and 2nd exposure. The exposure tool overlay error is more a practical limit for double patterning lithography (DPL). Hence we prefer the DEL for the resolution enhancement, especially if we use the KrF high NA lithography tool for 130 nm generation. Experimental and simulated results show that the critical dimension uniformity (CDU) depends strongly on the overlay precision. The DEL results show CDU is not only affected by the OVL but also by an optical proximity effect of 1st and 2nd exposure and the mask registration. The CD uniformity of DEL demands a low focus difference between 1st and 2nd exposure and therefore requires a good focus repeatability of the exposure tool. The Depth of Focus (DOF) of 490 nm at stable CD of lines was achieved for DEL. If we change the focus of one of the exposures the CD-focus performance of spaces was reduced with simultaneous line position changing. CDU vs. focus difference between 1st and 2nd exposure demands a focus repeatability

This paper presents a process technology for cost-effective integration of low-power flash-memories into a 0.25 /spl mu/m, high performance RF-BiCMOS process. Only 4 additional lithographic mask steps are used on top of the baseline BiCMOS process, leading to an in total 23 mask-level embedded flash BiCMOS process. Fowler-Nordheim-programmed stacked-gate and split-gate cells, suitable for medium density (Mbit) memories with programming times in the /spl mu/s-range and an endurance of >10/sup 5/ cycles are demonstrated. Peripheral high-voltage transistors with >10 V breakdown voltage are integrated without additional mask steps on top of the flash cell integration.

A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance. A ring oscillator delay of 3.6 ps per stage was achieved. To our knowledge, this is the shortest gate delay reported to date for a SiGe technology. The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 1.9 V at an drawn emitter size of 0.175/spl times/0.84 /spl mu/m/sup 2/. The high-speed HBT module has been integrated in a 0.25 /spl mu/m CMOS platform.

We demonstrate an extremely simple, flexible, and hence low-cost SiGe:C BiCMOS process with ample performance for the majority of high volume applications. This technology offers three HBT devices with f/sub T//BV/sub CEO/ values of 28 GHz/67 GHz/7.5 V; 52 GHz/98 GHz/3.8 V; and 75 GHz/ 90 GHz/2.4 V by adding only one mask to the underlying CMOS process.

Demonstrates a novel HBT-before-CMOS integration scheme to integrate SiGe:C HBTs with a 130 nm gate length CMOS frontend. This scheme entirely eliminates the impact of the HBT thermal steps on CMOS characteristics, opening the way for easy, modular integration of high-performance HBTs into highly scaled CMOS technologies. C doping of the SiGe layer prevents the degradation of HBT parameters by critical CMOS thermal steps. This is demonstrated for SiGe:C HBTs with f/sub T//f/sub max/ values of 80/90 GHz fabricated in the HBT-before-CMOS scheme and in a benchmark HBT-only process.

The progressive scaling in semiconductor technology allows for advanced miniaturization of intelligent systems like implantable biosensors for low-molecular weight analytes. A most relevant application would be the monitoring of glucose in diabetic patients, since no commercial solution is available yet for the continuous and drift-free monitoring of blood sugar levels. We report on a biosensor chip that operates via the binding competition of glucose and dextran to concanavalin A. The sensor is prepared as a fully embedded micro-electromechanical system and operates at GHz frequencies. Glucose concentrations derive from the assay viscosity as determined by the deflection of a 50 nm TiN actuator beam excited by quasi-electrostatic attraction. The GHz detection scheme does not rely on the resonant oscillation of the actuator and safely operates in fluidic environments. This property favorably combines with additional characteristics—(i) measurement times of less than a second, (ii) usage of biocompatible TiN for bio-milieu exposed parts, and (iii) small volume of less than 1 mm3—to qualify the sensor chip as key component in a continuous glucose monitor for the interstitial tissue.

A new scheme for the integration of high-performance HBTs with thin-film SOI CMOS is demonstrated. The thickness incompatibility problem of thin-body SOI CMOS and high-performance SiGe HBTs is solved by forming HBTs on silicon islands in the BOX. Low-resistance collector wells are realized by ion implantation into the SOI substrate. SiGe:C HBTs with f/sub T//f/sub max/ values of 220 GHz/230 GHz and a BV/sub CEO/ of 2.0 V and fully-depleted CMOS transistors with 90 nm gate length are fabricated on SOI wafers with 30 nm Si thickness.