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Design Optimization of Through-Silicon Vias for Substrate-Integrated Waveguides embedded in High-Resistive Silicon Interposer
- Source :
- 20th Electronics Packaging Technology Conference (EPTC 2018), 20th Electronics Packaging Technology Conference (EPTC 2018), Dec 2018, Singapore, Singapore
- Publication Year :
- 2018
- Publisher :
- HAL CCSD, 2018.
-
Abstract
- International audience; In this work, the optimization of TSVs for SIWs embedded in a high-resistive silicon interposer is demonstrated. EM simulations are performed to analyze and optimize important TSV design parameters enabling silicon interposer technologies with low-loss SIWs working at mm-wave/THz frequencies. A silicon interposer using high resistive silicon and TSVs is fabricated and SIWs are characterized working from 110-170 GHz with very low attenuation of ~0.5 dB/mm.
- Subjects :
- Materials science
Silicon
Terahertz radiation
dielectric loss
chemistry.chemical_element
metals
02 engineering and technology
Substrate (electronics)
cutoff frequency
Silicon interposer
0202 electrical engineering, electronic engineering, information engineering
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
substrates
Resistive touchscreen
business.industry
Attenuation
silicon
020206 networking & telecommunications
Cutoff frequency
chemistry
PACS 85.42
Optoelectronics
Dielectric loss
conductivity
business
through-silicon vias
Subjects
Details
- Language :
- English
- Database :
- OpenAIRE
- Journal :
- 20th Electronics Packaging Technology Conference (EPTC 2018), 20th Electronics Packaging Technology Conference (EPTC 2018), Dec 2018, Singapore, Singapore
- Accession number :
- edsair.doi.dedup.....07b129ff0ab8eb85312c5f8eed943c94