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In order to develop lightweight and high angular resolution x-ray mirrors, we have investigated hot plastic deformation of 4 in. silicon (111) wafers. A sample wafer was deformed using hemispherical dies with a curvature radius of 1000 mm. The measured radius of the deformed wafer was 1030 mm, suggesting that further conditioning is indispensable for better shaping. For the first time to our knowledge, x-ray reflection on a deformed wafer was detected at A1 [K.sub.a] 1.49keV. An estimated surface roughness of OCIS codes: 340.7470, 350.1260, 170.3890.

The quasi-steady-state photoconductance method is generalized for determining the bulk minority-carrier lifetime of the material at each carrier density while describing the effective carrier density accurately. The results are interpreted in order to predict the potential for each wafer to yield a solar cell with the specified efficiency for the production line.

The penetration of plasma into the wafer-focus ring gap of a capacitatively coupled discharge is examined. It is shown that the penetration of plasma into the gap and under the wafer level has increased as the size of the gap approaches and exceeds the Debye length in the vicinity of the gap.

Commercial hard-drive products utilizing perpendicular magnetic recording technology have recently been announced and introduced. In this paper, we review key magnetic materials characteristics and wafer process attributes in fabricating perpendicular write heads. It becomes increasingly important for write-head materials to possess not only high magnetic moment, but also optimal coercivity, remanence, anisotropy Hk, magnctostriction, and stress in order to meet head performance and reliability requirements. Advanced materials and film architectures discussed in this paper resulted in a significantly improved performance margin, including reduced pole erasure; hence enabling higher recording densities. Novel wafer-processing techniques are required for fabrication of 3-D pole features with controlled shape, and with critical dimensions of less than 150 nm. The advance in wafer process has been driven by rapidly decreasing trackwidth, as well as by the evolving head architecture from unshielded rectangular pole to shielded trapezoidal pole. Index Terms--High moment materials, lamination, perpendicular recording, perpendicular write head, pole erasure, wafer fabrication.

The detection of process problems and parameter drift at an early stage is crucial to successful semiconductor manufacture. The defect patterns on the wafer can act as an important source of information for quality engineers allowing them to isolate production problems. Traditionally, defect recognition is performed by quality engineers using a scanning electron microscope. This manual approach is not only expensive and time consuming but also it leads to high misidentification levels. In this paper, an automatic approach consisting of a spatial filter, a classification module and an estimation module is proposed to validate both real and simulated data. Experimental results show that three types of typical defect patterns: (i) a linear scratch; (ii) a circular ring; and (iii) an elliptical zone can be successfully extracted and classified. A Gaussian EM algorithm is used to estimate the elliptic and linear patterns, and a spherical-shell algorithm is used to estimate ring patterns. Furthermore, both convex and nonconvex defect patterns can be simultaneously recognized via a hybrid clustering method. The proposed method has the potential to be applied to other industries., 1. Introduction The manufacture of integrated circuits is a complex and costly process that involves hundreds of steps and requires the monitoring of many process parameters throughout the production process. [...]

We present a finite-element-based analysis to determine if there are potential reliability concerns due to thermally induced stresses in interwafer copper via structures in three-dimensional (3-D) ICs when benzocyclobutene (BCB) is used as the dielectric adhesive to bond wafers. We first partially validate our approach by comparing computed results against two types of experimental data from planar ICs: 1) volume-averaged thermal stresses measured by X-ray diffraction in an array of parallel Cu lines passivated with TEOS and 2) studies of failures induced by thermal cycling via chain structures embedded in SiLK or SiCOH. In the volume-averaged thermal stress study, predicted stress slopes (d[sigma]/dT) agree well with other modeling results. Our computed stress slopes agree reasonably well with experimental data along the Cu line direction and normal to the Cu lines surface, but we underestimate the stress slope across the Cu line. In the case of via chains, computed von Mises stresses agree with the results of thermal cycle experiments; we predict failure when SiLK is used as a dielectric and predict no failure when SiCOH is used as the dielectric. The approach is then employed to study thermal stresses in interwafer Cu vias in 3-D IC structures bonded with BCB. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing BCB thickness. We conclude that there is a concern regarding the stability of interwafer Cu vias. Guidelines for design parameter values are estimated, e.g., interwafer via size, pitch, and BCB thickness. For 2.6-/[micro]m-thick BCB, computations indicate that via size should be larger than 3 [micro]m at a pitch of 10 [micro]m to avoid plastic yield of Cu vias. Index Terms--Benzocyclobutene (BCB), Cu, interwafer vias, low-k dielectronics, thermo-mechanical stresses, three-dimensional (3-D) ICs.

Plasma interactions with chamber components and wafers in semiconductor manufacturing processes have been monitored with a fault detection technique. Not only can this diagnostic technique monitor the wafer and process chamber components qualities, but it also has potential in saving tremendous amounts of manufacturing costs and improving equipment productivity. We have discovered that the abnormality in certain plasma processing parameters detected in the early stages of a manufacturing line can have a strong correlation with the product yield. Possible reasons for the observed correlations are explained. Index Terms--Automatic process control (APC), correlation co-efficients, plasma, reactive-ion etch (RIE), [V.sub.pp], yield.

As semiconductor devices continue to get smaller, and thus the size of yield-limiting particles decreases, a need has arisen for detecting smaller particles on silicon surfaces. The current minimum detectable diameter of wafer-surface particle-detection systems employing 488-nm wavelength [Ar.sup.+] gas lasers widely used in semiconductor production lines is, under optimized conditions, 50-60 nm on bulk-silicon surfaces. The sensitivity for SOI wafers, however, is considerably lower than this level due not only to the additional optical reflections from Si/Si[O.sub.2]/Si interfaces within the SOI stack but also to the undesirable light scattering at the rough interfaces. The challenges in meeting the requirement to detect smaller particles specified in the ITRS will be presented. Using a 266-nm solid-state laser, we have developed for semiconductor manufacturing a high sensitivity system capable of detecting particles as small as 30 and 40 nm on unpatterned bulk-silicon wafers and SOI wafers, respectively. Our technique of single-wafer spin cleaning with repetitive use of ozonated water and dilute HF cleaning of silicon wafers can reduce surface microroughness, thus reducing background noise in this system, and providing higher particle-detection sensitivity than conventional RCA cleaning. Defect classification using this system integrated with a review scanning electron microscope will also be discussed. Index Terms--Laser applications, optical scattering, particle measurements, particle sources, silicon on insulator (SOI), SIMOX, surface contamination.

The aging and detergent washing effects in hexadecanethiol (HDT)-coated (001) and (100) GaAs wafers are investigated. The strong increase of the photoluminescence (PL) signal after detergent washing of (001) GaAs has suggested that this treatment is effective in removal of some of the non-adiative recombination centers (NRRC).

A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Packed bed microchannel reactors were fabricated using silicon DRIE, followed by wafer bonding. The reactor bed was subsequently filled with catalyst particles. Thermal control is achieved through on-chip resistive heaters, whereby methanol steam reforming reactions were studied over a temperature range from 180-300[degrees]C. Three simulations of varying complexity, including three-dimensional (3-D) quasi-3-D, and 1-D models, were developed. Comparison of the models with experimental results shows good agreement over a range of operating conditions. We found that Amphlett's kinetics for methanol reforming provided accurate results, and that for our operating conditions the reforming reaction could be modeled without mass transport considerations. The 1-D model provided a rapid analytical tool to assess the performance of the microreactor. Use of such computationally efficient design tools provides an effective means to analyze the performance of microreactor designs prior to fabrication and test. Hence, reformer geometry, catalyst loading, and operating parameters can be optimized to afford the desired hydrogen output and conversion. Concepts for insulating the reactor while maintaining small overall size are further analyzed. [1362] Index Terms--Heat transfer, methanol reforming, microreactor.

A novel beam-supported AIN resonator device was fabricated from thin film AIN directly supported on a (100) silicon wafer with no intervening metal electrode so as to maximize the crystalline quality of the AIN material. The suspended membrane design uses thin beams to support, as well as electricity connect, the resonator and has been fabricated using both thin film processing and bulk silicon micromachining.

The thickness and surface roughness of the native oxide on undoped and P-doped single crystal silicon and polycrystalline silicon (polysilicon) were measured after exposure to aqueous hydrofluoric acid (HF) in the presence of localized metallization of sputtered Au or Pd. Both P-doping and the presence of metallization led to an increase in the thickness of the native surface oxide and an increased surface roughness after HF exposure. An external positive (negative) potential during HF immersion increased (decreased) the rate of what is clearly electrochemical i.e., anodic corrosion. The presence of the sputtered metallization promoted anodic corrosion, particularly in HF and particularly for P-doped silicon. Porous silicon can be formed under these conditions, due to dissolution of the anodically produced surface oxide. Subsequent oxidation of the porous silicon can lead to thick surface oxide layers. [1354] Index Terms--Anodic oxidation, electrochemical, galvanic, porous Si.

Polycrystalline silicon carbide tensile microspecimens 3.1 mm long were produced by deep reactive ion etching of wafers on the order of 150 [micro]m thick. The gage sections, which were nominally 200 [micro]m wide, were either straight, slightly curved, or contained double notches in order to vary the size of the highly stressed region. The fracture stresses of 190 specimens from three process runs were measured in a novel test setup. The average local fracture strengths for the last run were: straight 0.38 [+ or -] 0.13 GPa, curved 0.47 [+ or -] 0.15 GPa, notched 0.78 [+ or -] 0.28 GPa. The corresponding Weibull characteristic strengths were, 0.42 GPa, 0.53 GPa, and 0.88 GPa with respective moduli 3.3, 3.4, and 3.1. These results show a clear increase in the strength of the material as the size of the highly stressed region decreases. Fractographic analyzes showed failures initiating from the bottoms of side grooves left by the etching process. The grains of the material were quite heterogeneous, varying from a few microns in size to columnar grains through the entire specimen thickness. The curved specimens were used as the base for predicting the probability of failure of the other two shapes. While the Weibull approach was quite accurate for the straight shape, it over-predicted the strengths of the notched specimens. Given the microstructure of the material relative to the size of the specimen, a continuum analysis is questionable. [1410] Index Terms--Fracture strength, microspecimens, microstructure, silicon carbide, size effect, tensile tests, Weibull statistics.

In this paper, a multilayered on-chip power distribution network consisting of two million passive elements has been modeled using the finite-difference time-domain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating multilayered power grids. In addition, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers, and rise times have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise. Also, a method has been presented for analyzing package and board planes. Based on the methods presented, the interaction between chip and package has been discussed for capturing the resonant behavior that is otherwise absent when each section of the system is analyzed separately. Index Terms--Chip--package interaction, circuit finite-difference time-domain (FDTD), decoupling capacitor, large chips, on-chip power distribution, power supply noise, wafer level package.

An investigation of the surface morphology of Langmuir monolayers of a series of C(sub n)F(sub 2n+1)C(sub m)H(sub 2m+1) (FnHm) molecular diblocks after transfer in silicon wafers is presented. Langmuir monolayers of semifluorinated alkanes FnHm consist of surface hemimicelles rather than of classical, laterally featureless monolayers.

This paper presents an assessment of four die-strength testing configurations using finite element analysis. The simulation indicates that ring-on-ring configuration is the best because it generates a uniform stress field on a large die surface area. The four-point-bend configuration ranks second and the three-point-bend configuration is third. The pin-on-ring configuration is the worst because the stress gradient is severe in the central region. To minimize uncertainty in the loading positions, it is advised that loading rings or bars with small radii be used. [DOI: 10.1115/1.1869510]

Simulations are performed to investigate the measurement accuracy of the electronic transport properties of silicon wafers by means of photocarrier radiometry by fitting frequency-scan data to a rigorous model via a multi-parameter fitting process. It was observed that for long lifetime wafers, the determination of diffusion is favorable with uncertainty and for short time wafers lifetime and diffusion coefficients could be determined with uncertainties.

Dark conductivity of silicon wafers has been measured as a function of doping levels, sample's geometry, and under gamma irradiation conditions. It has been shown that measurements of samples conductivity under different operating conditions can be used as an efficient method for material quality evaluation. In addition, gamma irradiation gives future information on Si-wafer quality, where it can effectively influence the material properties. The induced change in conductivity is discussed following the mathematical difference of conductivity modulation mode. Using this model conductivity measurements could be considered as a good and simple technique for determining the silicon quality and for further development in silicon processing. Keywords: Silicon photovoltaics, Conductivity measurement: Dark conductivity and modulation: Gamma irradiation effects

A novel method is presented for preparing ultraflat noble metal surfaces in situ under ultrahigh vacuum from thin metal films that are deposited through physical vapor deposition on commercially available silicon substrates. The resulting scanning-tunneling microscopy data suggest that under the surface preparation conditions examined, template-stripped platinum surfaces are predominantly [111] textured with a surface roughness equivalent to or better than a single-crystal Pt(111) surface.

A report on a planar poly(acrylic acid) (PAA) brush as a new kind of materials coating showing a variable protein resistance that can be controlled by the ionic strength of the protein solution is presented. With the help of neutron reflectometry it was found that a silicon wafer covered with a PAA brush strongly binds bovine serum albumin (BSA) under electrostatic repulsion.

Photomodulated thermoreflectance measurements between 300 and 650 K on phosphorus implanted and annealed silicon wafers are reported. The change of the photothermal amplitude and phase as a function of temperature is discussed.

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. A bearing depth of ~1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with thickness of the water layer at the interface responsible for hydrogen bonds that link the mating wafers.

An analytical model for dishing and step height reduction in chemical mechanical planarization (CMP) is presented. The model is based on the assumption that at the feature scale, high areas on the wafer experience higher pressure than low areas. A Prestonian material removal model is assumed. The model delineates how dishing and step height reduction depend on slurry properties (selectivity and Preston's constants), pad characteristics (stiffness and bending ability), polishing conditions (pressure, relative velocity and overpolishing) and wafer surface geometry (linewidth, pitch and pattern density). Model predictions are in good agreement with existing experimental observations. The present model facilitates understanding of the CMP process at the feature scale. Based on the proposed model, design avenues for decreasing dishing and increasing the speed of step height reduction may be explored through modification of appropriate parameters for slurry, pad and polishing conditions. The proposed model may also be used as a design tool for pattern layout to optimize the performance of the CMP process. Index Terms--CMP, dishing, step height reduction.

Recently, a comprehensive model has been developed by Luo and Dornfeld ('Material removal mechanism in chemical mechanical polishing: theory and modeling,' IEEE Trans. Semiconduct. Manufact., vol. 14, pp. 112-133, May 2001) to explain the material removal mechanism in chemical mechanical planarization (CMP). Based on the model, the abrasive size distribution influences the material removal from two aspects, one, the number of active abrasives, and the other, the size of the active abrasives. In this paper, experimental evidence supporting this view of abrasive size effects is discussed. A detailed model of wafer-abrasive-pad contact is developed to explain how and where abrasive size distributions come into the comprehensive material removal model. A material removal rate formulation as a function of abrasive size distribution is proposed and verified. In the future, the application of the model to the CMP process optimization, for example, improving the nonuniformity, or obtaining minimum surface scratching and preferred material removal rate by changing abrasive size distribution, may be attempted. Index Terms--Active abrasive number and size, chemical mechanical planarization, modeling.

This paper outlines the defect reduction measures performed during the development of a 130-nm Cu dual-damascene process. The test methodology, using short-loop test structures, included defect tracing, overlaying defect data and electrical measurement data, physical analyses based on these results, and analyses of defect size distribution. While the defect size distributions for large-scale integration processes are considered to depend on [x.sup.-k], the distribution for the Cu dual-damascene process is found to be different and is instead characterized by a cumulative distribution described by the composition of several Lorentzian functions. Using these procedures, defect densities were successfully reduced by 50% in half the time taken previously and without the need for actual products. Index Terms--Inspection, metallization, testing, wiring.

The authors propose a new accurate yield prediction method for system-LSI embedded memories to improve the productivity of chips. Their new method is based on the failure-related yield prediction method in which failure bits in memory are tested to see whether they are repairable or not by using built-in redundancies. The important concept of the new method is called 'repairable matrix' (RM). In RM, r[m.sub.ij] = 1 means that i row redundancy sets and j column redundancy sets are needed for repair, where r[m.sub.ij] is an element of the matrix. Here, RM can indicate all the candidate combinations of the number of row and column redundancy sets for repair. The new yield prediction method using RM solves two problems, 'asymmetric repair' and 'link set.' These have a significant effect on accurate yield prediction but have not yet been approached by conventional analytical methods. The calculation of yield by the new method is demonstrated in two kinds of advanced memory devices that have different design rules, failure situations, and redundancy designs. The calculated results are consistent with the actual yield. On average, the difference in accuracy between the new method and conventional analytical methods is about 5%. Index Terms--Embedded memory, failure, redundancy, semiconductor manufacturing, yield prediction.

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 x [10.sup.18] c[m.sup.-3] and the sheet resistance of 13 nm and 700 [ohm]/s. for As and 14 nm and 770 [ohm]/sq for B[F.sub.2] with junction leakage lower than 1 x [10.sup.-16] A//[micro][m.sup.2] at 1.5 V were successfully obtained without wafer slip and warpage problems. Index Terms--Activation, crack, flash !amp annealing (FLA), junction leakage, low resistance, MOSFETs, preamorphization, slip, stress, ultrashallow junction.

The reduction of chemical usage in semiconductor manufacturing has been a topic of wide discussion over the past several years. The aim of this study is to optimize plasma efficiency as chemical reactions by using the Taguchi method. In short, the function of plasma is to serve as an etchant that reacts with films. The results of the reaction are discharged. The main point of optimization was to use a main etchant to increase the amount of desirable main reaction and to decrease the amount of unreacted gas in order to keep the undesirable side reaction to a minimum. We found chemical vapor deposition cleaning conditions that improve plasma efficiency up to 200%, perfluorocompounds (PFC) gas usage to one-third, and PFC gas emission to 25%. We also found nitride etching conditions that improve plasma efficiency up to 350%, S[F.sub.6] usage to 25%, S[F.sub.6] emission to 22%, and selectivity to oxide up to 145% over the previous conditions. Index Terms--Chemical vapor deposition, environmental factors, etching, plasma diagnostics.

New methods for monitoring via and line voiding in metal interconnect structures are described. A focused laser beam injects heat into a structure such as a line or via chain, which may have width considerably smaller than the spot size. Conduction of heat, and therefore temperature under the spot, is a function of via or line integrity. Probing the temperature using laser reflection provides a direct nondestructive measure of via continuity or line voiding. Index Terms--Copper interconnect, damascene copper, via, void.

The authors have developed a new process as an alternative to sulfuric peroxide mixture (SPM) cleaning of Si wafers. This process, vapor ozone strip (VOS), uses ozone and vaporized water, significantly reducing any effect on environment, health and safety. The process is more effective than ozone water immersion, because high concentration ozone gas and high temperature water can be used simultaneously. Also, the process uses the highly reactive OH(*) radical species. The VOS process is able to strip photoresist at a higher rate than other techniques using ozone. Ion implanted photoresist and etched photoresist can be stripped. VOS has demonstrated equivalent performance to SPM in electrical reliability testing. Index Terms--Ozone, photoresist removal, wafer cleaning.

A novel heating technique, electromagnetic induction heating (EMIH), uses electromagnetic radiation, ranging in frequency from a few megahertz to tens of gigahertz, to volumetrically heat silicon above 1000 [degrees]C in only a few seconds. Typical power requirements fall between 900 to 1300 W for silicon wafers 75 to 100 mm in diameter. This technique has successfully produced direct silicon wafer-to-wafer bonds without the use of an intermediate glue layer. Infrared images indicate void free bonds that could not be delaminated with knife-edge tests. In addition, four pairs of stacked wafers were bonded simultaneously in 5 min, demonstrating the potential for multiwafer bonds and high-throughput batch processing. [690] Index Terms--Bonding, electromagnetic, radiation, silicon.

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt percent Sn-3.5wt percent Ag and 100wt percent In. The 62wt percent Sn-36wt percent Pb-2wt percent Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP Solder joint reliability are investigated. [DOI: 10.1115/1.1400995]

Mechanical holding systems of a wafer might cause serious problems in the semiconductor industry. Electrostatic wafer handling might be one of the possible solutions for such problems. We have investigated an attractive force on a silicon wafer by using an electrostatic chuck which consists of interdigitated electrodes and a dielectric thin film. Electrostatic attractive force increases as the applied voltage increases, and with a thinner dielectric layer. With the narrower width and spacing of interdigitated electrodes, the stronger electrostatic force is obtained. When 1-mm width and spacing interdigitated electrodes and 50-[micro]m-thick polymer film are used, the strongest force obtained was about 17 N in the vertical direction at 3.5 kV, for a 4-in silicon wafer. When dc high voltage is used, some residual force remains, even after the applied voltage is removed. This was overcome by using variable-frequency ac high voltage. Index Terms--Dielectric thin film, electrostatic chuck, electrostatic force, holding system for silicon wafer, interdigitated electrodes system.

A DNA array detection method is reported in which the binding of oligonucleotides functionalized with gold nanoparticles leads to conductivity changes associated with target-probe binding events. The binding events localize gold nanoparticles in an electrode gap; silver deposition facilitated by these nanoparticles bridges the gap and leads to readily measurable conductivity changes. An unusual salt concentration-dependent hybridization behavior associated with these nanoparticle probes was exploited to achieve selectivity without a thermal-stringency wash. Using this method, we have detected target DNA at concentrations as tow as 500 femtomolar with a point mutation selectivity factor of ~ 100,000:1., A major challenge in the area of DNA detection (1) is the development of methods that do not rely on polymerase chain reaction (PCR) or comparable target-amplification systems that require [...]

Electron device modeling is a challenging task at millimeter-wave frequencies. In particular, conventional approaches based on lumped equivalent circuits become inappropriate to describe complex distributed and coupling effects, which may strongly affect the transistor performance. In this paper, an empirical distributed FET model is adopted that can be identified on the basis of conventional S-parameter measurements and electromagnetic simulations of the device layout. The consistency of the proposed approach is confirmed by robust scaling properties, which enable millimeter-wave small-signal S-parameters to be predicted as a function of the device periphery and number of gate fingers. Moreover, it is shown how the model identified on the basis of standard S-parameter measurements up to 50 GHz can be efficiently exploited in order to obtain reasonably accurate small-signal prediction up to 110 GHz. Extensive experimental validation is presented for 0.2-[micro]m pseudomorphic high electron-mobility transistors devices. Index Terms--Computer-aided engineering, electromagnetic simulation, global modeling, millimeter-wave FETs, MODFET, semiconductor device modeling.

An accurate deembedding technique for on-wafer measurements of an active device's S-parameter is presented in this paper. This deembedding technique accounts in a systematic way for effect of all parasitic elements surrounding the device. These parasitic elements are modeled as a four-port network. Closed-form equations are derived for deembedding purposes of this four-port network. The proposed deembedding technique was used to extract small-signal model parameters of a 2 x 25 [micro]m emitter GaInP/GaAs heterojunction bipolar transistor device, and excellent agreement between measured and model-simulated S-parameter was obtained up to 30 GHz. Index Terms--Device characterization, four-port network, microwave on-wafer measurements, S-parameter deembedding.

A method is described for synthesizing a floated carbon nanotube (CNT) bridge on a silicon wafer patterned by a conventional photolithography process. The bamboo-shaped CNTs grow laterally to the substrate by a SiO(sub 2) vertical growth barrier and connect two nickel-catalyst lines and the diameter of CNT bridges depends on the thickness of the nickel-catalyst layer and the length, linearity and density of which can be controlled by adjusting the synthetic process parameters.

Research describing the electrical characteristics of boron doped silicon wafers is presented. In particular the effects of laser annealing are investigated.

Iron-boron pairs were studied in p-type silicon and cross sections of the acceptor level were taken using injection-level dependent lifetime measurements.

Research describing the removal of particles from the surfaces of silicon wafers is presented. In particular the use of intense laser pulses to induce airborne plasma shockwaves is investigated.

Research describing the effects of irradiation on the diffusion of boron in delta-doped silicon is presented. In addition the presence of antimony and its effect on boron diffusion is investigated.

Research describing the sheet resistance of InP layers during proton irradiation is presented. The thermal stability of the formed isolation during annealing is also investigated.

Research describing inductively coupled plasma etching is presented. In particular Indium Phoshide (InP)-based nanostructures are investigated for etching techniques using N2/H2 plasmas.

Research describing photoscanning techniques using semiconducting quantum interference devices is presented. The use of such devices for nondestructive evaluation of photovoltaic systems is analysed.

Research describing the residual strain on Raman shifts and Hall effects in thin bonded silicon-on-insulator wafers is presented. The lattice strain is measured as a function of temperature and duration of the heat treatment.

Research describing deformation fields in epitaxial layer stacks is presented. Comparisons are studied by crystal diffractometry of wafer bonding to various different templates.

Small-angle neutron scattering was applied to measure the dimension and quality of 150nm lines on single crystal silicon wafers, nondestructively and quantitatively.

Iron density in boron-doped silicon wafers was determined using the pulsed MOS capacitor generation lifetime technique.

Research describing the properties of niobium-based thin films is presented. In particular the dependence of silicon wafer films on total sputtering pressure during reactive magnetron sputtering is investigated.