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This paper discusses time-dependent dielectric breakdown (TDDB) in n-FETs with HfSiON gate stacks under various stress conditions. It was found that the slope of Weibull distribution of Tbd, Weibull β, changes with stress conditions, namely, DC stress, unipolar AC stress and bipolar AC stresses. On the other hand, the time evolution component of stress-induced leakage current (SILC) was not changed by these stresses. These experimental results indicate that the modulation of electron trapping/de-trapping and hole trapping/de-trapping by stress condition changes the defect size in high-k gate dielectrics. Therefore, the control of injected carrier and the characteristics of trapping can provide the steep Weibull distribution of Tbd, leading to long-term reliability in scaled CMOS devices with high-k gate stacks.

The Time Dependent Dielectric Breakdown mechanisms of n/p-FETs having high-k gate dielectrics have been studied through the Weibull distribution. From the thickness dependence of Weibull beta, it is found that the breakdown in n-FETs and p-FETs is mostly determined by the breakdown of high-k layer and interfacial layer (I.L.), respectively. Furthermore, Weibull beta in p-FETs is found to be independent of the injected carrier ratio (Jhole/Jelectron) while those in n-FETs strongly depend on this ratio. Improvement of Weibull beta through the control of the injected carrier ratio together with metal gate application leads to extremely longer lifetime in n-FETs. Improvement of average Tbd through the control of hydrogen concentration in high-k leads to longer life time also in p-FETs.

Electrical properties of thin high-k dielectric films are influenced (or even governed) by the presence of macroscopic, microscopic and atomic-size defects. For most applications, a structurally perfect dielectric material with moderate parameters would have sufficiently low leakage and sufficiently long lifetime. But defects open new paths for carrier transport, increasing the currents by orders of magnitude, causing instabilities due to charge trapping, and promoting the formation of defects responsible for electrical breakdown events and for the failure of the film. We discuss how currents flow across the gate stack and how damage is created in the material. We also illustrate the contemporary basic knowledge on hazardous defects (including certain impurities) in high-k dielectrics using the example of a family of materials based on Pr oxides. As an example of the influence of stoichiometry on the electrical pa-rameters of the dielectric, we analyze the effect of nitrogen incorporation into ultrathin Hf silicate films.

Chemical bonding features in metal (TiN or Ru)/HfSiON gate stacks and electrical potential changes due to dipoles at the metal/dielectric interfaces have been studied by back-side x-ray photoemission measurements of the samples after wet-chemical removal of Si substrate. The photoemission threshold of the metal gate measured through the ultrathin dielectric layer confirms that the potential change of the gate metals, which is nearly equivalent to the difference in the flat-band voltage shift between capacitors with SiO2 and HfSiON, is caused by electron transfer from the HfSiON layer to the metal gate near the interface. From the recovery in the gate potential induced by oxygen incorporation into HfSiON, oxygen vacancies in the HfSiON layer are likely to be possible origin of the gate potential change. Also, from the experimental fact that the gate potential change becomes significant with decreasing thickness of the interfacial SiO2 layer below 3.5nm in Ru/HfSiON/SiO2 gate stacks, it is suggested that the generation of oxygen vacancies in HfSiON caused by oxidation reaction of Si substrate through ultrathin SiO2 layer plays an important role on the electron transfer near the Ru/HfSiON interface.

Vacancy-type defects in MOSFET structures fabricated with high-k (HfSiON) gate dielectrics were studied by monogenetic positron beams. An expansion of open volumes in HfSiON fabricated on Si substrates using atomic layer deposition technique was observed with increasing nitrogen concentration. This fact was discussed in terms of a role of nitrogen in Hf-related oxide using results obtained by first-principles calculation and XPS. MOSFETs fabricated by F-channel implantation technique were also characterized. The major defect species which causes the Vth shift of MOSFETs was identified as vacancy-fluorine complexes (such as V3F2) locate in channel regions of Si substrates. The preset work suggests that positron annihilation can be used to detect microscopic defects in MOSFETs, and it is a useful tool for determining process parameters for MOSFET fabrications with high-k gate dielectrics.

Ionicity has been raised as an important factor in discussing defect formation in Hf-based oxides. It has been elucidated from our first-principles calculations, that the stability of defects is dominated by Coulomb interactions between charged defects and surrounding ions. For instance, the formation energy of positively charged oxygen vacancies (VO+2) is markedly decreased when they are coupled with substitutional N atoms at O sites, as the nominal charges of N3- are negatively greater than those of the oxygen ions O2-. Our computational results have further revealed that the ionic character of Hf causes generation of a low-lying Si dangling bond level in Si doped HfSiOx. These results suggest that one must take into account the ionicity of the Hf-based compounds, which possess totally different properties from the conventional gate insulator SiO2 in terms of defect formation.

Leakage current characteristics with significantly reduced dispersion were achieved for HfSiON gate dielectric film by selecting TiN gate electrode with low reactivity, compared to the conventional poly-Si gate. The breakdown lifetime and its characteristic homogeneity were also enormously improved. With intensive study on these electrical characteristics, it was concluded that the concentration of oxygen vacancy was significantly reduced, giving rise to the homogeneity improvement. Moreover, we have shown an explanation for the dielectric breakdown in terms of oxygen transport in the Hf-based dielectric film.

We have studied depth profiling of the chemical composition, bonding features and defect states in 2 nm-thick HfSiO"xN"y (Hf/(Hf+Si)=~43%) films with N content of ~13 at.% before and after post-deposition annealing (PDA) at 1050 ^oC in O"2 and N"2 ambience by using high-resolution x-ray photoelectron spectroscopy (XPS) and total photoelectron yield spectroscopy (PYS) in combination with oxide thinning by a dilute HF solution. NO"x and Hf-N"x (x=2, 3) bonding units existing in the sample before PDA were effectively eliminated or reduced by PDA and Si-N and Hf-N bonds were the main N bonding features after PDA. We found the formation of a region with a low Si content and a residue of Hf-N"2 bonding units in the HfSiO"xN"y film by O"2-PDA in comparison to N"2-PDA. The PYS measurements revealed a high density of filled defect states in such a Si-deficient region with a large number of Hf-N"2 bonds.

High-dielectric constant (high-k) gate materials, such as HfSiOx and HfAlOx, fabricated by atomic-layer-deposition techniques were characterized using monoenergetic positron beams. Measurements of the Doppler broadening spectra of annihilation radiation and the lifetime spectra of positrons indicated that positrons annihilated from the trapped state by open volumes that exist intrinsically in amorphous structures of the films. The size distributions of the open volumes and the local atomic configurations around such volumes can be discussed using positron annihilation parameters, and they were found to correlate with the electrical properties of the films. We confirmed that the positron annihilation is useful technique to characterize the matrix structure of amorphous high-k materials, and can be used to determine process parameters for the fabrication of high-k gate dielectrics. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The effect of gate metal film stress on the performance of gate-last metal–oxide–semiconductor field-effect transistors (MOSFETs) with a W/TiN/SiO2 gate stack was investigated. The channel strain induced by the electrode film was controlled by the W film stress. The W film stress was determined by the deposition method and film thickness. The compressive and tensile stresses of the electrode film enhance nFET and pFET performances, respectively. The enhancements of the performances are introduced not only by the stress of the film on the channel but also by the stress of the film on the side in the groove of the gate-last MOSEFTs. Metal electrode stress can be a further controlling factor in the performance of scaled devices.

The correlation between conduction and lifetime in HfSiON films has been characterized with reference to the inhomogeneous distribution of defects. The electrical effects that are induced by the nitrogen have been also investigated. The temperature dependence of the leakage current revealed that the inclusion of nitrogen atoms transformed the defect levels, leading to a reduction in leakage current and improved breakdown lifetime. Moreover, it was also found that nitridation leads to a suppression of the dispersion of defects. The characteristics of oxygen vacancies were demonstrated in terms of nitridation effects.

Silicon dangling bonds (Si-DBs) in HfSiOx have been studied using first-principles calculations. Interestingly, our computational result revealed that the Si-DB-related gap state in HfSiOx locates in a much lower energy region than that in SiOx. This is because Hf atoms enhance the ionic character of the HfSiOx film, which in turn induces a positive charge at the Si site. We consider that the low-lying Si-DB level, which is now very near the N 2p state, contributes to the formation of strong Si–N bonds in HfSiON. The lower shift of the Si-DB level upon cation metal inclusion can be useful information not only for improving the electric properties of high-k gate stacks but also for developing prominent silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile memories where controllability of the charge trap level is a crucial issue.

The interfacial reaction of a TiN/HfSiON/SiO2 gate stack in high-temperature annealing was investigated from the viewpoint of the redistribution of the elements of gate stack materials. Oxygen incorporation enhanced the redistribution of the elements not only of the dielectric film of HfSiON/SiO2 but also of the gate electrode film of TiN. Oxygen incorporation in high-temperature annealing enhances the partial release of Hf, N, and Si from HfSiON or the disassembly of the HfSiON film, which leads to an increase in the equivalent-oxide thickness (EOT). The EOT increase can be determined by the combination of the decrease in the HfSiON film caused by the Hf and N release from HfSiON and the increase in the interfacial layer created by the oxidation of the Si substrate surface by the penetrating oxygen. It is also found that Ti diffused from the TiN into the interfacial layer through the HfSiON/SiO2. The suppression of oxygen incorporation is a key technique in the high-temperature annealing of metal/high-k gate stacks.

In order to improve the NBTI of pMOSFETs with ultra-thin HfSiON gate dielectrics, a novel plasma nitridation process has been developed. Inclusion of hydrogen in the plasma nitridation ambient brings about an increased NBTI lifetime of about half an order of magnitude. The improvement is due to the suppression of bulk hole traps, presumably originating from the Hf-N bond. Hydrogen in the plasma ambient is thought to prevent the formation of additional Hf-N bonds during post- nitridation annealing.

Changes in optical thickness and equivalent oxide thickness (EOT) during postdeposition annealing (PDA) and postnitridation annealing (PNA) were investigated to fabricate sub-1-nm-EOT nitrided hafnium silicate (HfSiON) gate dielectrics. In spite of optical thickness reductions by PDA, none of the PDA conditions could reduce the EOT and bring about the merit in leakage current reduction. On the other hand, high-temperature PNA without oxygen was found to be effective for reducing both optical thickness and EOT. Furthermore, leakage current reduction ratio and effective mobility were improved by applying high-temperature PNA. Consequently, the fabrication of 0.81-nm-EOT HfSiON gate dielectrics with a gate leakage current of 0.74 A/cm2 at 0.7 V and an electron mobility of 235 cm2/(V s) at 0.8 MV/cm (76% of SiO2) has been realized.

We present in-depth profiling of chemical bonding features and defect state density in ultrathin HfSiOxNy (Hf/(Hf+Si)=~43%) films with average nitrogen contents up to ~18at.% by using x-ray photoelectron spectroscopy (XPS) and total photoelectron yield spectroscopy (PYS) in combination with oxide thinning in a dilute HF solution. The films were prepared on pre-cleaned Si(100) by an atomic layer chemical vapor deposition (ALCVD) method and followed by plasma nitridation. By annealing at 1050°C in N2 ambience, Si-N bonding units in the films are increased as a result of thermal decomposition of Hf-Nx(x=2 and 3) units and the interfacial oxidation accompanied with nitrogen incorporation is caused. For the annealed samples, Hf ions coordinated with two N atoms are distributed with a profile peaked around 1nm from the top surface. Also, from the depth profiles of chemical compositions, which were determined from the change in the intensity at each thinning step, we found that the oxygen content becomes its minimum around ~1.2nm from the surface while the nitrogen content becomes its maximum within ~1.5nm from the surface. The result suggests that the surface re-oxidation is promoted coincidentally with the diffusion of N atoms generated by thermal decomposition of the Hf-Nx units during the N2- annealing. The photoelectron yield from filled defect states in the dielectric stacks was increased in the early stages of oxide thinning and then decreased with further progressive thinning. The depth profile of the defect states, which was derived from the change in the yield, shows that the defect state density becomes its maximum in the near-surface region where oxygen deficiency becomes significant. It is likely that the imbalance in chemical coordination between anions and cations is responsible for the defect generation.

We have investigated the reaction mechanism of the nitridation process based on first principles calculations and experimental results. We found that oxidation-resistant Si3N4 film can be formed by uniformly arranging 3-fold coordinated N atoms into Si sub-surface layer, and we successfully incorporated O atoms into the SiN/Si interface with minimum disruption of SiN structures. We have realized a high-quality ultra-thin gate SiON film with an equivalent oxide thickness of 0.7 nm and a leakage current of 95 A/cm2, 1/10 or less than that of traditional SiON films. Mobility is not reduced to less than 89% of an ideal SiO2 film.

Insulators with high dielectric constants (so-called high-k) have been intensively investigated for the replacement of SiO2 gate dielectric of MOS transistors for high-speed ULSIs in near future. The characterization results of the Hf-silicate gate dielectric, especially in terms of its structural transformation during high temperature annealing, are presented. Phase separation and micro-crystallization in Hf-silicates were evaluated using XPS, TEM, and XRD. Impurity diffusion through the dielectric was also examined using the backside SIMS of the p+-poly-Si/Hf-silicate/Si-substrate system. It has also been revealed that such thermal stability problems for Hf-silicates can be solved with nitrogen incorporation in the film using the physical analyses outlined above. [DOI: 10.1380/ejssnt.2003.116]

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

Time Dependent Dielectric Breakdown (TDDB) in p-FETs with HfSiON/SiO 2 gate stacks under negative bias stress has been studied. It is shown that the shape parameter of Weibull distribution of T bd , β, is very small value independent of gate electrode materials. This small β seems to arise from the interface layer (I.L.) breakdown. Further experimental result reveals the existence of additional interface layer degradation mechanisms due to hydrogen in HfSiON. The reduction of hydrogen amount in high-k dielectrics leads to the longer-term reliability in metal-gate /high-k gate stacks.

The slope parameter of Weibull plot of Tbd, β, strongly depends on gate electrode material for metalgate/HfSiON gate stacks in n-FETs. Furthermore β of Tbd under bipolar stress is larger than that under DC stress. From these results, it is found that the balance of injected carriers is strongly related to β in terms of the origin of large β for metal-gate/high-k.

We investigated bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB) in TaCx/HfSiON MOSFETs in terms of the effects of TaCx metal gate electrode, using various Ta composition and TaCx thickness. We find a dual nature of TaCx metal gate electrode effects on the reliability. The gate electrode has both positive and negative influence on BTI and TDDB. Though various TaCx layers were deposited on the same HfSiON layer, high composition of Ta in the TaCx layer and thick TaCx layer improve BTI and mobility, while they deteriorate time to breakdown (Tbd) because of the effects of metal gate induced defects.

Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (DeltaVt), both of which are induced by interface dipole modulation at high-k/SiO2 interface, is investigated. Three types of dipole modulation are examined; Al addition, La addition, and changing quality of interfacial SiO2 layer. Extrinsic scattering components due to increases of interface state and surface roughness are extracted and separated. It is found that RCS due to interface dipole modulation by Al addition increases with increasing DeltaVt, while that by La addition is constant, independent of DeltaVt. Inevitability of additional scattering for DeltaVt is discussed based on two different models for dipole formation mechanisms.

We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaCx composition, fixed charge free TaCx/HfSiON device is successfully fabricated. Also, we have demonstrated that the strain effect in deeply scaled devices can be enhanced by eliminating the fixed charges in HfSiON, for the first time. Utilizing Stress Memorization Technique (SMT) and strained Contact Etch Stop Layer (CESL), Lg = 35 nm high performance TaCx/HfSiON devices is achieved.

Apparent difference of the dielectric breakdown behavior between high-k stack and the conventional SiO2 is investigated by the temperature dependence of TDDB lifetime. It is clarified that the temperature dependence of TDDB lifetime in high-k stack can be described by two parameters, which is identical to the case of conventional SiO2.

We propose a feasible integration scheme for dual FUSI/HfSiON CMOS with low work function metal pile-up to nMOSFET. A newly developed post phase change process to Ni3Si and composition-dependent diffusivity of Al realize simplified integration of 4.3 eV/4.8 eV. Moreover, direct WF lowering of Pt2Si with metal pile-up realizes 4.3 eV/4.9 eV.

We have realized a 0.9nm-EOT TaSix/HfSiON gate stack that exhibits the high electron mobility of 264 cm2/Vs @ 0.8MV/cm (86% of thermal SiO2), even after spike annealing at 1000degC. This was achieved by using thermally-stable HfSiON gate dielectrics with plasma nitridation, in which interfacial layer growth due to recoiled oxygen had been successfully suppressed

The breakdown behaviors of ultra-thin HfSiON gate dielectrics have been investigated to provide a clear determination of time to breakdown Tbd. Abrupt jumps in gate leakage current Ig under negative stress voltage were readily observed by using small area devices, even in sub-0.9-nm EOT HfSiON. In the case of positive bias stress, an abrupt jump in Ig under stress voltage was hardly observed. Rather than observing gate leakage current Ig, we could determine the Tbd by the abrupt jump in substrate current Isub in carrier separation measurement using nMOSFETs. By using this method, the initial breakdown event could be sensitively detected and Tbd under the both biases can be handled with the Weibull distribution. Therefore conventional procedures for gate area conversion and failure rate extrapolation are expected to be valid, even for the ultra-thin HfSiON gate dielectrics.

To improve NBTI of pMOSFETs for hp-65nm technology node and beyond, low temperature catalytic CVD (Cat-CVD) formed SiN was applied to liner film in PMD and gate-sidewall formed. We found that N-H bond in the cat-CVD SiN is enough stable to affect the NBTI while the amount of Si-H bond needed to be reduced, which can be achieved by higher catalyst temperature. The liner and sidewall application improved the NBTI lifetime of two and one orders of magnitude respectively comparing a low temperature LP-CVD SiN using hexa-chloride-disilane (HCD).

In this paper, the effect of the MIGS and the poly-Si process on the Vfb shift was carefully examined and clarified. We conclude that these factors are not correlated with the shift. We found that lowering the Htf (Hf+Si) (Hf-ratio) in HfSiON below 10% leads to the significant suppression of this shift in both NMOS and PMOS. We also demonstrated that the insertion of ultra-thin cap layers into the poly-Si/HfSiON results in Vfb improvement with 0.1 nm EOT expense. We proposed that the sophisticated tailoring of Hf in the dielectric could be a practical solution for the Vfb improvement.

A comparative study of plasma and thermal nitridation of HfSiO was performed systematically. We found that over 15 atom% of nitrogen is necessary to obtain sufficient thermal stability and blocking of boron diffusion in a conventional polycrystalline Si gate CMOS process regardless of the nitridation method. However, we demonstrated, for the first time, that plasma nitridation has a great advantage for obtaining thinner equivalent oxide thickness, lower gate leakage current (J/sub g//J/sub g/SiO/sub 2/=1E-4 @ V/sub g/=V/sub fb/-1 V) and higher carrier mobility (/spl mu//sub eff///spl mu//sub eff/SiO/sub 2/=0.85 @ E/sub eff/=0.8 MV/cm for electron, /spl mu//sub eff///spl mu//sub eff/SiO/sub 2/=0.9 @ E/sub eff/=0.5 MV/cm for hole) due to nitridation of HfSiO film without nitridation of Si substrate, compared with thermal nitridation.

Fabrication process of HfSiON gate dielectrics by plasma oxidation of CVD Hf silicate followed by plasma nitridation was developed. Thanks to the high quality ultrathin interfacial layer formed by internal plasma oxidation, electron mobility of 240 cm/sup 2//Vs@0.8 MV/cm (85% of SiO/sub 2/) and hole mobility of 73 cm/sup 2//Vs@0.5 MV/cm (93% of SiON) were successfully achieved. The developed process will be promising for the production of low power CMOS devices in the near future.

We achieved 0.73 nm EOT, 88 A/cm/sup 2/ J/sub g/, and 92% G/sub m/ of that for SiO/sub 2/ by just oxidation of SiN films. In addition, we achieved further improvement of EOT-J/sub g/ characteristics by re-nitridation process with minimum degradation of G/sub m/. EOT of 0.70 nm and J/sub g/ as 95 A/cm/sup 2/ is realized with superior suppression of boron penetration (/spl Delta/V/sub th/=0.04 V).

The effects of the nitrogen in the HfSiON gate dielectric on the electrical and thermal properties of the dielectric were investigated. It is clearly demonstrated that nitrogen enhances the dielectric constant of silicates. High dielectric constants of the HfSiON are maintained and boron penetration is substantially suppressed in the HfSiON during high temperature annealing. These properties are ascribed to the homogeneity of the bond structure in the film containing nitrogen through high temperature annealing.

We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (0.7 V). By using this technology, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with mid-gap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V).

A conformable formation process of ultra-thin Ta/sub 2/O/sub 5/ gate dielectrics, which is applicable to 50 nm damascene gate MOSFETs, was developed. Assisted by H/sub 2/O, perfect conformability was successfully realized even in the narrow gate groove (50 nm), while maintaining a low gate leakage. An excellent device performance of S-factor 72 mV/decade was obtained in 90 nm MOSFET with amorphous Ta/sub 2/O/sub 5/ gate dielectrics of T/sub eff/ 1.6 nm.