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Improvement of threshold voltage deviation in damascene metal gate transistors

Authors :
Tomohiro Saito
K. Suguro
Tsuyoshi Shibata
Seiji Inumiya
Tsunetoshi Arikado
K. Matsuo
Kazuaki Nakajima
Y. Tsunashima
Atsushi Yagishita
Source :
IEEE Transactions on Electron Devices. 48:1604-1611
Publication Year :
2001
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2001.

Abstract

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

Details

ISSN :
00189383
Volume :
48
Database :
OpenAIRE
Journal :
IEEE Transactions on Electron Devices
Accession number :
edsair.doi...........ed30dcc86008ac567f9b8c7ef24f81f3
Full Text :
https://doi.org/10.1109/16.936569