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An 8-18 GHz receiver implemented in silicon-germanium (SiGe) BiCMOS technology is presented. The receiver is designed to enable built-in test (BIT) and consists of a low noise amplifier (LNA), an image-reject mixer, on-chip, automatic gain control (AGC), ring oscillator (RO) sources (used to provide test signals of a predefined amplitude), and digital-to-analog converters (DACs), used for DC bias control of the blocks. The voltage and current biases of both the LNA and the mixer circuit blocks are used as tuning knobs for radio frequency (RF) performance metrics to mitigate the negative effects of total ionizing dose (TID) radiation damage present in extreme environments such as space. Samples of the receiver die were exposed to 10 keV X-rays at 1, 3, and 6 Mrad( SiO2) doses. The BIT system was able to mitigate for TID damage in most cases, with improvements in the key RF metrics of gain, output third-order intercept point (OIP3), and noise figure (NF). The receiver was fabricated in an 0.18 μm SiGe BiCMOS process technology with a peak fT of 150 GHz and nominally consumes 241-243 mA from a 4 V supply.

Electronics in space-based systems are in the process of a paradigm shift moving from centralized, heavily shielded, temperature-controlled warm boxes to distributed, minimally shielded sensing and control nodes. SiGe BiCMOS technology is one of the enablers of this move with its ability to withstand extremely wide variations in temperature and high radiation doses. This article has presented two SiGe BiCMOS wireline transceivers designed to be a part of the new system perspective by creating a means of control and communication across vehicle-wide buses. Both the RS-485 and ISO 11898 transceivers have been shown to work robustly from 90 K to 390 K, with consistent rise/fall times, propagation delays, and output amplitudes. Additionally, the ISO 11898 transceiver is TID tolerant to 2 Mrad, and the transmitter is hardened to single-event effects.

We present a wideband, low noise amplifier (LNA) implemented in a Silicon-Germanium Heterojunction Bipolar Transistor (SiGe HBT) technology. This SiGe LNA covers a frequency range of 8-16 GHz and achieves a peak gain of 17.5 dB at nominal bias and a peak OIP3 of 15.8 dBm at 10 GHz at nominal bias. The noise figure (NF) of the LNA is 4.5-8.1 dB across band, and it nominally consumes 4 mA from a 4 V supply. Samples were irradiated with 63.3 MeV protons to proton-equivalent doses ranging from 200 krad(Si) to 2 Mrad(Si). This LNA incorporates bias control “tuning-knobs” to enable bias tuning to mitigate for RF performance loss due to total dose exposure and process variation in performance metrics. The effectiveness of the tuning “knobs” to compensate for lost post-irradiated performance was investigated. It was found that the LNA performance can be restored with the use of the tuning knobs with a performance tuning algorithm.

A wideband (6-20 GHz) Silicon-Germanium (SiGe) adaptive image-reject mixer with an intermediate frequency (IF) of 1.8 GHz is presented. The mixer can be “self-healed” to deliver consistent performance by nullifying the effects of process variations, environmental changes, or aging. Various performance metrics of the mixer can also be adapted to different specifications across multiple frequency bands. A conversion gain greater than 15 dB, an image rejection ratio (IRR) exceeding 35 dB, and an output 1-dB compression point greater than 10 dBm, were obtained in measurement. An automated self-healing procedure is developed and shown to be effective for improving the measured performance of the mixer. The mixer was fabricated in a 150 GHz peak fT, 200 nm SiGe BiCMOS process technology and consumes 215 mA of current operating off a 4 V rail.

We have presented the architecture, simulation, packaging, and over-temperature and radiation testing of a complex, 16-channel, extreme environment capable, SiGe Remote Electronics Unit containing the Remote Sensor Interface ASIC that can serve a wide variety of space-relevant needs as designed. These include future missions to the Moon and Mars, with the additional potential to operate in other hostile environments, including lunar craters and around the Jovian moon, Europa. We have expanded on the previous introduction of the RSI to show the validity of the chip design and performance over an almost 250 K temperature range, down to 100 K, under 100 krad TID radiation exposure, with SEL immunity and operability in a high-flux SET environment.

We have described the modeling, circuit design, system integration, and measurement of a Remote Sensor Interface (Figure 20) that took place over a span of 5 years and 8 fabrication cycles. It was conceived as part of the Multi-Chip Module (MCM) shown in Figure 21, which also includes a digital control chip for clocking, programming, and read-out. Further work beyond the scope of this was performed to validate the RSI for the extreme environmental conditions of a lunar mission, and individual blocks are presently.

We investigate a novel implementation of junction isolation to harden a 200 GHz SiGe:C HBT technology without deep trench isolation against single event effects. The inclusion of isolation is shown to have no effect on the dc or ac performance of the nominal device, and likewise does not reduce the HBTs inherent tolerance to TID radiation exposure on the order of a Mrad. A 69% reduction in total integrated charge collection across a slice through the center of the device was achieved. In addition, a 26% reduction in collected charge is reported for strikes to the center of the emitter. 3-D NanoTCAD simulations are performed on RHBD and control device models yielding a good match to measured results for strikes from the emitter center to 8 ?m away. This result represents one of the most effective transistor layout-level RHBD approaches demonstrated to date in SiGe.

Silicon-germanium heterojunction bipolar transistor (SiGe HBT) heavy ion-induced current transients are measured using Sandia National Laboratories' microbeam and high- and low-energy broadbeam sources at the Grand Acce?le?rateur National d'Ions Lourds, Caen, France, and the University of Jyva?skyla?, Finland. The data were captured using a custom broadband IC package and real-time digital phosphor oscilloscopes with at least 16 GHz of analog bandwidth. These data provide detailed insight into the effects of ion strike location, range, and LET.

We investigate the single-event transient (SET) response of bandgap voltage references (BGRs) implemented in SiGe BiCMOS technology through heavy ion microbeam experiments. The SiGe BGR circuit is used to provide the input reference voltage to a voltage regulator. SiGe HBTs in the BGR circuit are struck with 36-MeV oxygen ions, and the subsequent transient responses are captured at the output of the regulator. Sensitive devices responsible for generating transients with large peak magnitudes (more than 5% of the dc output voltage) are identified. To determine the effectiveness of a transistor-layout-based radiation hardened by design (RHBD) technique with respect to immunity to SETs at the circuit level, the BGR circuit implemented with HBTs surrounded by an alternate reverse-biased pn junction (n-ring RHBD) is also bombarded with oxygen ions, and subsequent SETs are captured. Experimental results indicate that the number of events causing transients with peak magnitude more than 5% above the dc level have been reduced in the RHBD version; however, with the inclusion of the n-ring RHBD, new locations for the occurrence of transients (albeit with smaller peak magnitude) are created. Transients at the transistor-level are also independently captured and are presented. It is demonstrated that while the transients are short at the transistor level (ns duration), relatively long transients are obtained at the circuit level (hundreds of nanoseconds). In addition, the impact of the SET response of the BGR on the performance of an ultra-high-speed 3-bit SiGe analog-to-digital converter (ADC) is investigated through simulation. It is shown that ion-induced transients in the reference voltage could eventually lead to data corruption at the output of the ADC.

Microbeam measurements and TCAD simulations are used to examine the effects of ion angle of incidence on the charge collected from events occurring in a Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT). The results identify the geometrically driven charge-collection mechanisms that dominate the low LET broad beam SEU response. The deep trench isolation that surrounds the transistor significantly modulates the charge transport and, therefore, the charge collected by the collector. A new way of estimating critical charge, , for upset in SiGe HBT circuits is proposed based on TCAD simulation results and measured broadbeam data.

We investigate the effects of both X-ray and proton irradiation on a novel 200 GHz/90 GHz (npn/pnp) complementary SiGe:C HBT technology. The DC forward mode total dose tolerance of the pnp HBTs is shown to exceed that of the npn HBTs by a significant margin after being subjected to both 63-MeV proton and 10-keV X-ray sources, while the AC characteristics of both devices exhibit no degradation up to X-ray doses as high as 1.8 Mrad(SiO2). Pre- and post-irradiation results from a current feedback operational amplifier implemented in this technology and irradiated up to a dose of 1.8 Mrad(SiO2) are presented, showing no degradation in performance metrics under two low current density bias configurations.

Proton and X-ray irradiation effects are investigated in 0.35 m conventional, annular, and ringed-source radiation-hardening-by-design (RHBD) CMOS devices. Transistors were irradiated with protons at both 300 K and 77 K. Radiation-induced oxide trapped charges in the shallow trench isolation (STI) oxide deplete the p-substrate and effectively shunt the source and drain, inducing off-state leakage. Without the STI, RHBD nFETs exhibit no radiation-induced off-state shunt leakage currents for devices irradiated at both 300 K and 77 K. Conventional 0.35 mum pFETs were not degraded by proton irradiation, since the leakage path cannot be formed in the n-well. A simple CMOS logic inverter shows no degradation in output voltage after proton irradiation for all tested temperature and bias conditions. More advanced 130 nm node nFETs show less TID sensitivity to STI leakage due possibly to the smaller physical STI volume and/or additional doping located on the STI sidewall.

The radiation tolerance of strained Si/SiGe n-MODFETs is investigated, using 10 keV X-rays, 63 MeV high energy protons, and 4 MeV low energy protons. The effects of radiation exposure on two major device design parameters (LSD and LG) in T-gate Si/SiGe n-MODFETs devices are examined. A strong dependence on source-drain spacing is observed for both the DC and RF characteristics. A drift-diffusion TCAD framework is used for 2-D device simulations. We believe that the low energy protons damage the SiGe/strained-Si/SiGe lattice, leading to partial strain relaxation. The conduction band-offset (CBO) of the strained SiGe/Si heterojunction is lowered leading to higher gate current leakage. The presence of radiation-induced bulk traps in the unrelaxed SiGe layers on the device behavior is also investigated.

A comprehensive investigation of the performance dependencies of irradiated SiGe precision voltage reference circuits on (1) total ionizing dose (TID), (2) circuit topology, and (3) radiation source is presented. Two different bandgap voltage references were designed using a first-generation (50-GHz) SiGe BiCMOS technology platform, and subsequently exposed to X-rays at doses of 1080 krad(SiO2) and 5400 krad(SiO2). The degradation in circuit performance following X-ray irradiation depends on both the TID level and the chosen circuit topology. Measurement results show that large TID levels can significantly shift the magnitude of the output voltage. Explanations for the observed shifts are provided by utilizing detailed analyses of the two circuit topologies and considering device-to-circuit interactions. The primary factor responsible for the difference in the circuit response before and after irradiation can be attributed to the excess base leakage current in the SiGe HBT. To investigate the impact of radiation source, the circuit topology showing the worst-case degradation from the X-ray experiment was independently exposed to 63-MeV protons at the same effective TID level. A clear source dependence in the circuit response was observed, and possible origins of this behavior are identified.

We present an investigation of the observed variations in the total dose tolerance of the emitter-base spacer and shallow trench isolation oxides in a commercial 200 GHz SiGe HBT technology. Proton, gamma, and X-ray irradiations at varying dose rates are found to produce drastically different degradation signatures at the various oxide interfaces. Extraction and analysis of the radiation-induced excess base current, as well as low-frequency noise, are used to probe the underlying physical mechanisms. Two-dimensional calibrated device simulations are employed to correlate the observed results to the spatial distributions of carrier recombination in forward- and inverse-mode operation for both pre- and post-irradiation levels. Possible explanations of our observations are offered and the implications for hardness assurance testing are discussed

The off-state drain current leakage characteristics of 130 nm CMOS technology are investigated using x-ray irradiation and operating temperature as variables. Radiation-induced interface traps in the gate oxide to gate-drain overlap region strongly enhance the off-state leakage as a function of gate bias. Due to the thin gate oxide in these 130 nm devices, we find that drain-edge direct tunneling is more plausible than conventional gate-induced-drain-leakage in explaining the observed increase in drain leakage. Radiation-induced traps in the shallow trench isolation oxide create parasitic channels in the p-well and produce another source of off-state drain leakage with increasing total dose. The drain current increase from both the gate overlap region and the shallow trench edge are enhanced with increasing total dose and suppressed by cooling

The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates

We compare, for the first time, the effects of 63 MeV protons on 1st generation and 3rd generation SiGe HBTs irradiated at both liquid nitrogen temperature (77 K) and at room temperature (300 K). The 1st generation SiGe HBTs irradiated at 77 K show less degradation than when irradiated at 300 K. Conversely, the 3rd generation SiGe HBTs exhibits an opposite trend, and the devices irradiated at 77 K show enhanced degradation compared to those irradiated at 300 K. The emitter-base spacer regions for these two SiGe technologies are fundamentally different in construction, and apparently are responsible for the observed differences in temperature-dependent radiation response. At practical circuit biases, both SiGe technology generations show only minimal degradation for both at 77 K and 300 K exposure, to Mrad dose levels, and are thus potentially useful for electronics applications requiring simultaneous cryogenic temperature operation and significant total dose radiation exposure

Delayed charge collection from ionizing events outside the deep trench can increase the SEU cross section in deep trench isolation technologies. Microbeam test data and device simulations demonstrate how this adverse effect can be mitigated through substrate engineering techniques. The addition of a heavily doped p-type charge-blocking buried layer in the substrate can reduce the delayed charge collection from events that occur outside the deep trench isolation by almost an order of magnitude, implying an approximately comparable reduction in the SEU cross section

We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.

An integrated wideband (6–20 GHz) image-reject mixer and test signal source for "self-healing" of image-rejection ratio (IRR) is demonstrated for the first time. The mixer can be adapted to deliver consistent performance over process variations, environmental changes, and/or aging effects. An IRR of over 36 dB is obtained in measurement for a wide range of IF frequencies. The healing is achieved by means of an automated procedure controlled by MATLAB algorithms. The test signal source consists of an on-die wideband differential ring oscillator with an amplitude-control mechanism to provide a 20 dB range of adjustable power at the input of the mixer. The circuits were fabricated in a commercially-available 180 nm SiGe BiCMOS platform.

This paper describes the design and testing of two cold-capable SiGe BiCMOS wireline transceivers targeted for applications in distributed electronics systems in space-based vehicles. Space-based electronic systems face extremely wide temperature ranges and hazardous radiation that can cause unpredicted behavior in sensitive circuitry. The most common mitigation procedure involves extensive shielding and temperature control in “electronics vaults.” Unfortunately, this practice comes with a high cost in weight, power, and volume. Recently, there has been a paradigm shift that advocates moving away from these centralized solutions and towards distributed electronic systems. The transceivers presented in this work were designed to be a part of a larger system created to demonstrate that SiGe BiCMOS technology was a viable candidate for implementing extreme environment electronics. Both the RS-485 transceiver and ISO 11898 transmitter will be shown to work robustly up to 20 Mbps and in measurement from 90 K to 390 K, with consistent rise/fall times, propagation delays, and output amplitudes. This work adds a piece to the distributed electronics puzzle by enabling robust communication throughout space-based systems with minimal temperature control.

We present an ultra-wideband, Low Noise Amplifier (LNA) implemented in a Silicon-Germanium Heterojunction Bipolar Transistor (SiGe HBT) technology. This SiGe LNA covers a frequency range of 8–18 GHz and achieves a peak gain of 15.6 dB at nominal bias and a nominal OIP3 of 3 dBm at 13 GHz. The Noise Figure (NF) of the LNA is 3.6–7.9 dB across band, and it consumes 7 mA from a 3.3 V supply. This LNA incorporates bias control knobs for circuit ‘self-healing’ to compensate for process-induced (or other) variations in performance metrics. Process variations are detected using a companion source measure unit (SMU) test circuit that gathers DC device information to determine the healing to be applied.

An integrated wideband amplitude-locked test signal source for “self-healing” and built-in-self-test (BIST) of multiband mixed-signal system-on-a-chip solutions is demonstrated. To the authors' knowledge, this work achieves the widest reported tuning range per unit die area compared to the state-of-the-art. The signal generator spans frequencies ranging from X to K band while occupying only 0.329 mm2 of core die area. The oscillator core is based on a differential ring topology to achieve wide tuning capability. The amplitude-locked loop consists of a variable gain amplifier (VGA), a low power peak detector, and an opamp that doubles as a loop filter. The circuits were fabricated in a commercially-available 180 nm SiGe BiCMOS platform.

A wideband (6–20 GHz) SiGe adaptive image reject mixer with an IF bandwidth of more than 1.8 GHz is presented. The mixer can be “self-healed” to deliver consistent performance across band by nullifying the effects of process variations, environmental changes or aging and can be adapted to different specifications. A conversion gain greater than 15 dB, an image rejection ratio (IRR) exceeding 35 dB and an output 1-dB compression point greater than 10 dBm were obtained in measurement. An automated self-healing procedure is shown to be effective for improving the measured performance of the mixer. The mixer was fabricated in a 150 GHz peak f T 200 nm SiGe BiCMOS process and consumes 215 mA of current operating off a 4 V rail.

We investigate the efficacy of mitigating radiation-based single event effects (SEE) within circuits incorporating SiGe heterojunction bipolar transistors (HBTs) built with an N-Ring, a transistor-level layout-based radiation hardened by design (RHBD) technique. Previous work of single-device ion-beam induced charge collection (IBICC) studies has demonstrated significant reductions in peak collector charge collection and sensitive area for charge collection; however, few circuit studies using this technique have been performed. Transient studies performed with Sandia National Laboratory's (SNL) 36 MeV 16O microbeam on voltage references built with N-Ring SiGe HBTs have shown mixed results, with reductions in the number of large voltage disruptions in addition to new sensitive areas of low-level output voltage disturbances. Similar discrepancies between device-level IBICC results and circuit measurements are found for the case of digital shift registers implemented with N-Ring SiGe HBTs irradiated in a broadbeam environment at Texas A&M's Cyclotron Institute. The error cross-section curve of the N-Ring based register is found to be larger at larger ion LETs than the standard SiGe register, which is clearly counter-intuitive. We have worked to resolve the discrepancy between the measured circuit results and the device-level IBICC measurements, by re-measuring single-device N-Ring SiGe HBTs using a time-resolved ion beam induced charge (TRIBIC) set-up that allows direct capture of nodal transients. Coupling these measurements with full 3-D TCAD simulations provides complete insight into the origin of transient currents in an N-Ring SiGe HBT. The detailed structure of these transients and their bias dependencies are discussed, together with the ramifications for the design of space-borne analog and digital circuits using SiGe HBTs.

This paper describes the design, implementation, and characterization of a monolithic charge amplification channel for use as a piezoelectric sensor front-end in extreme environment applications. 12The design leverages a 50 GHz peak-f T SiGe BiCMOS technology platform to achieve functionality across a wide-temperature range from −180°C to 120°C. As part of a much larger remote electronics unit, the channel is specified to amplify piezoelectric transducer signals with frequencies up to 5 kHz and amplitudes as low as 200 pC. Intended for use in lunar surface systems, the application requires the capability to absorb up to 100 krad(SiO 2 ) of total ionizing dose (consistent with a typical lunar mission cycle) and be hardened against latch-up effects that cause system failure in a heavy ion radiation environment. Preliminary characterization of the channel shows the desired integration of an AC current input, programmable gain, and effective filtering at three distinct cutoff frequencies.

Device-level current transients are induced by injecting carriers using two-photon absorption from a subbandgap pulsed laser and recorded using wideband transmission and measurement equipment. These transients exhibit three distinct temporal trends that depend on laser pulse energy as well as the transverse and vertical charge generation location. The nature of the current transient is controlled by both the behavior of the subcollector-substrate junction and isolation biasing. However, substrate potential modulation, due to deformation of the subcollector-substrate depletion region, is the dominant mechanism affecting transient characteristics.

The authors reported the floating body effects in 90nm partially-depleted, strained-silicon CMOS on SOI devices operating down to cryogenic temperatures. These devices also exhibit immunity to X-ray and proton irradiation without process hardening (Appaswamy et al, 2006) and thus are potentially suitable for space applications. One-to-one comparisons are made to conventional unstrained CMOS on SOI devices from the same 90 nm technology node

The effects of 63 MeV proton irradiation on 90 nm strained silicon CMOS on insulator is examined for the first time. The devices show no observable degradation in DC performance up to an equivalent total dose of 600 krad(Si). The performance of the strained pFETs is identical to unstrained pFETs and demonstrates the immunity of strain to displacement damage. There is no significant enhancement observed in back channel leakage for the maximum dose. Passive exposure to 2 Mrad(Si) using 4 MeV protons doesn't induce any significant performance degradation.

0C (43K) in the polar shadows), makes operation of the electronics sub-systems on the surface of the Moon exceptionally difficult, but is nonetheless required for the envisioned complex suite of electronics systems used in sensing, actuation, and control of robotic systems. Such applications are typically fairly low frequency in nature (e.g., < 100 MHz), hence not requiring the most aggressively scaled CMOS technology; however, a full suite of mixed-signal circuit building blocks, and reliable operation of those circuits across extremely large variations in temperature (e.g., +120 to -230C) is needed. Adequate device reliability must clearly be achieved to accomplish this task. CMOS device degradation due to hot carriers effect (HCE) is known to be considerably worse at low temperatures [2]. Device lifetime data at cryogenic temperatures, and a solid understanding of the corresponding degradation mechanisms, are thus critical in this context of space electronics, and are addressed in this work. The Si CMOS devices investigated here are from an advanced 0.5µm SiGe BiCMOS technology, with a fixed channel width of 10.0 µm, and effective gate lengths ranging from 0.35 µm (minimum geometry), to 5.0 µm. The devices were characterized on a custom cryogenic probe system from 300K down to 43 K (-230 0 C). For brevity we will focus on the nFET data, since it represents the worst case in this technology. Fig. 1 and 2 shows typical I-V characteristics for the CMOS devices at different temperatures. The current drive capability increases significantly for the same bias conditions, as the temperature decreases. The nFET lifetime was inferred using stress-induced changes to the ID-VG characteristics. The lifetime τ is defined here as the inferred stress time for which a certain parameter of the ID-VG characteristics has shifted by a predefined amount (e.g., 10% degradation of gm). A typical lifetime assessment analysis using the ID-VG characteristics for a 1.0 µm nFET are shown in Fig. 3 and Fig. 4. The slope of 0.6 for the linear fitting in Fig. 4 suggests that interface state generation is responsible for the observed device degradation at the maximum substrate current (VG ≈ ½ VD); while that of 0.3 for the maximum gate current bias condition (VG = VD) suggests that oxide trapped charge dominates [3]. For the nFETs operating at 300K, the worst case bias condition for hot carrier degradation is known to be under maximum substrate current bias. There has been speculation that the worst case bias conditions for hot carrier degradation can, however, be a function of temperature [4]. It can be verified from Fig. 4 that for this technology, maximum substrate current is indeed the worst bias condition, at least down to 82K, and hence was the condition used here for device lifetime evaluation. The substrate current is comprised of the generated hot carriers, and is thus a good monitoring parameter for HCE in practical measurements. Fig. 5 and Fig. 6 show the effects of temperature and gate length on substrate current, respectively. It can be seen from Fig. 5 that the maximum substrate current under the same bias condition increases by 3x as temperature decreases from 300K to 43K; while Fig. 6 suggests that the maximum substrate current increases by more than 10x as L shrinks from 1.0 µm to 0.35 µm, and becomes negligible as L increases to 5.0 µm. This suggests that HCE is impacted more by device geometry than by the temperature. Fig. 7 shows the inferred lifetime at different drain bias’ at different temperatures. As seen in Fig. 7, τ decreases by ~10x as the temperature is reduced from 300K to 82K. Furthermore, τ differs by more than 100x between the 1.0 µm and 0.35/5 µm transistors, and hence the longer-channel devices are preferred for cryogenic applications of this technology Assuming fast interface trap generation dominates the HCE degradation, plotting τID versus ISUB/ID on a log-log scale should yield a straight line behavior [5]. The critical electron energy for generating an interface trap is calculated to be 3.9 eV from the slop of the line. Both the slope and the critical energy from Fig. 8 correlate well with literature data (2.9 and 3.7 eV in [5]), suggesting that interface state generation is the dominant limiting reliability factor at low temperatures.