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The traditional Thevenin equivalent Modular Multilevel Converter (MMC) model has poor versatility for the two working conditions of pre-charging and DC-side faults. In this paper, an improved Thevenin equivalent MMC model considering pre-charge conditions and DC side fault conditions is proposed. The model divides the pre-charging condition into a Controllable charging stage and an Uncontrollable charging stage. The DC-side fault condition is divided into the pre-blocking and post-blocking conditions of the converter. The circuit characteristics are analyzed, and the equivalent model topology is comprehensively improved to make it suitable for full-condition simulation, and a control strategy suitable for the equivalent model is proposed. The detailed model and the proposed improved equivalent model were built in PSCAD/EMTDC for comparison and analysis. The simulation results shows that the improved equivalent model can be applied to various working conditions, and the versatility of the traditional Thevenin equivalent model is improved.

This brief proposes a highly-integrated 3-phase ( $3\boldsymbol{\Phi }$ ) 4:1 resonant switched-capacitor (ReSC) converter with parasitic capacitor soft charging for Internet-of-Things devices, reducing the current stress at the point of load. Both the $3\boldsymbol{\Phi }$ resonant operation and the parasitic loss reduction schemes improve the power conversion efficiency. Also, this $3\boldsymbol{\Phi }$ -ReSC converter implements a flying capacitor pre-charge scheme to guarantee a safe startup. The chip, fabricated in a 65-nm CMOS process, occupies a silicon area of 1.39 mm2. We achieve a peak efficiency of 85.5% and a maximum output current of 130mA, in a mm-sized solution, with an input range of 2.3 V – 2.5 V.

for automobile applications, a high-switching 48-to-5V DC-DC buck converter is implemented with 0.5µm CMOS process and 0.5µm Gallium-Nitride (GaN)-on-Si process, including the pre-charge tracking technique, temperature-dependent controlled gate driver, and adaptive relaxation gate-drive control technique, which can increase the efficiency by about 8.8% and ensure the current capacity of Enhance-GaN (E-GaN). The inner local negative feedback loop can enhance the reliability and reduce the RON by 12mΩ. The peak efficiency is as high as 95.4%.

This article describes the memory cell proposed design of a low-power 8T SRAM cell. Two PMOS transistors are employed in this proposed approach, one of which is connected to the node voltage Q and the other one is connected to the Qbar. In order to remove the swing voltage at the bit and bit bar lines. When the cell is in working mode, the swing voltage is minimized, which reduces the dynamic power dissipation. Precharge voltage level is a technique in which a PMOS transistor acts as a switch and an NMOS transistor acts as a resister, resulting in a series of leakage current reductions when the transistors move from sleep to active and vice versa. The findings of the comparison show that the read, write, and hold mode operation for the proposed 8T SRAM cell is superior to that of the 6T SRAM cell. This is frequently because greater static noise margins are obtained, ensuring good bit cell write ability. All simulation results of read and write on the proposed 8T SRAM cell and current models of 6T SRAM cell have been applied to 130 nm CMOS technology utilizing the Symica DE tool.

A pulse-width-modulation (PWM) bidirectional ac-dc converter (i.e., active rectifier) with dc-faultblocking and self-pre-charge capabilities is proposed in this paper for low-voltage dc (LVDC) applications. The proposed converter, which is named as ”H5 + converter”, consists of an H4 bridge, a bidirectional switch, and a transient-voltage-surge (TVS) diode. The bidirectional switch and the TVS diode enable the dc-fault blocking and dc-bus self-pre-charge, while preserving the low common mode voltage noise and low leakage current of the converter. Additionally, the proposed H5+ converter has advanced features under a dc-side short circuit fault, such as fault diagnosis and fault recovery. Operation principles of the proposed converter are presented and analyzed. A down scaled prototype is built. Experiment results are shown and analyzed, including steady-state waveforms, common-mode performance, start-up dynamics, as well as dc fault blocking, fault diagnosis, and fault recovery. Moreover, the proposed converter is compared with other two dc-fault blocking converters for LVDC applications, in terms of converter capabilities, required devices, and power switch losses.

Emerging device-based crossbar-array can improve energy efficiency and performance in Spiking Neural Network (SNN) that performs numerous addition and multiplication operations. However, for the large size of crossbar array, delay for SL voltage development increases due to large capacitances of bit-line, and area overhead of peripheral circuit increases significantly. In this paper, we propose STT-MRAM architecture for SNN by minimizing area overhead and operation delay with peripheral circuit optimization. When the proposed method is applied, in 512×512 crossbar array, voltage development delay is reduced by 5.75 (ns), making it possible to perform faster inference operation.

A non-volatile memory designed to FLASH recollections and switch SRAM seems to be the Magnetic RAM (MRAM) proximity unit. Due to its inherent radiation hardness, Spin Transfer Torque Magnetic Memory (STT-MRAM) was also used for top-responsibility applications. CMOS circuit sensitive to radiation Pre Charge Sense electronic equipment (PCSA); but we are able to recharge the non-volatile storage ceaselessly to urge accurate details. Since the current advantages are abandoned by radiation effects, STT-MRAM cannot be used specifically for top radiation applications. In this paper, a new style in the change of PCSA STT-MRAM sensing circuit is proposed and the paper focused more on power and space with performance up gradation.

Pre-charge as a key step in the battery manufacture processes, which has a great impact on the film-forming properties and electrochemical performances, especially the Li-rich system batteries. As a key influence factor, it is necessary to clarify the effect of pre-charge temperature on battery performance. In this paper, we mainly studied the influence of different pre-charge temperatures (25°C, 40°C, 60°C) on the gas production and electrochemical performance of the batteries. The results show that the increase of the pre-charge temperature will result in the increase of gas production, and the gas components are mainly CO2, H2. After the long-term cycle, the sample under 40°C maintains the highest capacity retention rate, and as the pre-charge temperature increases, the median voltage of the battery can be effectively increased. In addition, compared with room temperature pre-charge, high pre-charge temperature samples have more excellent rate performance.

Dielectric Modulated Field Effect Transistor (DMFETs) offer advantages over many other well-known biosensors, making them extremely important in the fields of medicines and diagnostics. The paper aims to model a DMFET using the SPICE Level-3 model. This adapted model of the DMFET sensor can be used to detect the presence of both the charged as well as uncharged biomolecules in the nanogap cavity etched in gate-dielectric. The presence of both negatively charged and uncharged DNA molecules at the nanogap cavity changes the threshold voltage, thereby changing the on-current. Finally, this work integrates a low noise, low power pre-charge amplifier designed in 90-nm CMOS technology with the small-signal output of the adapted DMFET model. Charge sensitivity of 984.2 mV/pC was achieved without using any high magnitude passive feedback resistance.

Modular multilevel converter (MMC) is one of the most promising topologies in high-voltage applications. Kinds of modular topologies have been widely studied and discussed, but the dc fault ride-through capability and operating efficiency are still considered as a trade-off. In this paper, an enhanced alternate arm multilevel converter (AAMC) is proposed with the arm phase-shift modulation. By adjusting the phase-shift angle, the energy balance is achieved to allow a wide operating range. Combining the merits of low-cost half-bridge submodules and bipolar full-bridge submodules, the proposed T-type AAMC requires less power devices than traditional MMCs and AAMCs while keeps the dc fault ride-through capability. Since an additional ac arm stack is equipped in the T-AAMC, the dc-side based pre-charge methods is not applicable. The ac-dc coordinated pre-charge strategy is proposed to charge both the full-bridge stacks and half-bridge stacks to the reference voltage. Simulation cases are presented to validate the effectiveness of the proposed topology, modulation and pre-charge strategy.

Due to limited scalability and leakage power of CMOS-based logic circuit, Spin Transfer Torque (STT) device, which has the characteristics of a low area, zero leakage power, nonvolatile and infinite endurance, is one of the strongest candidates to overcome limitations of CMOS. Based on these characteristics, efforts have been made to develop STT-device logic circuit. However, STT-device logic circuit has encountered the problem of read reliability. To address read reliability issue, we propose a new Sense amplifier, named variation-tolerant separated precharge sense amplifier. This circuit, by using transmission gate and feedback, is resilient to process variation and has high read reliability. Simulation using the 65nm process is conducted to show the performance of the proposed sensing circuit. Simulation results demonstrate that the reading error rate of the proposed sense amplifier decreased by 68% and 37% respectively, compared to the conventional SPCSA and RESPCSA.

This paper proposes the pre-charge, discharge, and mini-UPS circuits of an auxiliary power network architecture for 10kV SiC-based power electronics building block. The design and working principle of all components are given with hardware prototypes and test waveforms. This architecture proposes a simple auxiliary-power-only pre-charge method, and increase the system reliability by having a rapid discharge circuit for dc-link, and a mini-UPS backup power supply.

This paper presents a cost-effective electromagnetic energy harvester (EMEH) based on wire-wound technology. It also shows the energy management system used to convert the EMEH's AC voltage to a DC one. The EH system is self-powered and does not require external sources or pre charge of any of its components and provides maximum power point tracking.

The intent of this paper is to analyze the working of the Magnetic Tunnel Junction (MTJ) based Ternary Content Addressable Memory (TCAM) with and without the match-line (ML) pre-charge. The designs of the memory with MTJs that have been implemented by previous researchers have made use of ML pre-charge. In this paper, for performance comparison, three different TCAM cells have been implemented - one with ML pre-charge (PC) and the other two, namely Self-Controlled Pre-charge free (SCPF) and Hybrid SCPF (HSCPF), without ML pre-charge. The designs were simulated on Cadence Virtuoso design tool using CMOS 180 nm technology with a supply voltage of 3 V. Arrays of different sizes for all three circuits were simulated and compared with respect to delay, area and power. The study revealed that, for an 8X16 array, the delay for SCPF and HSCPF is 79.77% and 25013.5% more than that of PC circuit, area occupied is 98.65% and 38.04% more than that of PC Circuit. Power consumed for SCPF and HSCPF arrays is 125.38% and 7.5% more than that of PC Circuit. This is in contrast to the Static Random Access Memory (SRAM) based TCAM circuits where power and delay for SCPF and HSCPF circuits is lesser than that of PC circuit.

The paper focuses on control analysis and operational issues of a recently proposed direct voltage regulated active capacitance reduction circuit, consisting of a small auxiliary capacitance interfaced to dc link by bidirectional dc–dc converter. The aim of such a system is replacing the bulk dc bus capacitor without escalating the ripple. While the hardware of the system under study is similar to some of the proposed active capacitance reduction solutions, the control structure is quite different. The primary goal of the controller is direct regulation of dc-link voltage rather than dc-link current, performed by most of existing solutions, thus avoiding the use of invasive dc-link current measurement/s. It is revealed that such an active capacitance reduction circuitry may be perceived as output-voltage regulated wide-input-range converter feeding a bidirectional power load. Such an arrangement was neither mentioned nor analyzed in the literature by far, requiring nontrivial and challenging control design. A dual-loop voltage-current arrangement widely used in typical power supplies is proposed to control the active capacitance reduction circuitry. It is shown that the control structure is sufficient to yield satisfactory performance even though the system possesses a slow unstable mode when absorbing power from the dc link. The revealed findings are fully supported by simulations and experimental results.

The deployment of electric vehicles (EVs) protects the environment by reducing carbon emissions. Since plugged-in EVs require energy from the power grid to charge their batteries, the charger component is inevitable. With the appropriate control, additional functions can be achieved with the existing charger’s converter topology. This paper discussed the implementation of a new control strategy in a three-phase off-board EV charger, which provided grid voltage regulation while charging the vehicle. The vehicle charging control (P-control) and grid voltage regulation control (V-control) were implemented in the back-end DC/DC converter and front-end AC/DC converter of the charger, respectively. The proposed P-control utilized the constant current/reduced constant current charging approach to rapidly charge the battery while alleviating battery deterioration. Meanwhile, the proposed V-control had the capability to regulate the grid voltage and DC-link voltage during the EV charging process. Besides the PSCAD/EMTDC simulation, experimental testing was performed on a 2 kVA laboratory EV charger to validate the control performance. While complying with the harmonic standards, the experimental results showed that the charger prototype effectively regulated the grid voltage to the pre-charge voltage while maintaining the DC-link voltage at 150 V during various charging currents of up to 5 A.

To improve light load efficiency, a three-phase photovoltaic (PV)-based microinverter may operate in single-phase, two-phase or three-phase mode depending on the available input power. Therefore, its dc-link capacitor may be subjected to large peak-to-peak voltage ripple when operating in phase skipping mode. This paper determines the minimum value of the dc-link capacitor by allowing the maximum acceptable voltage ripple on the dc link. This allows for the use of film capacitors instead of electrolytic capacitors in order to improve the microinverter reliability. Unfortunately, higher dc-link voltage ripple introduces harmonic distortion on the inverter output current waveform if it is not compensated for by the dc-link voltage controller. This paper proposes a simple synchronous control method to regulate the dc-link voltage with the presence of large voltage ripple. The dc-link voltage controller is synchronized with the phase-locked loop and samples the average value of dc-link voltage without introducing unwanted harmonics into the voltage sense path. Experimental results were obtained from a 300-W three-phase half-bridge microinverter prototype to verify the proposed dc-link voltage control performance. Inverter output current total harmonic distortion of 1.6% was achieved even though the dc-link peak-to-peak voltage ripple reached as high as 87 V with 219-V split dc-link voltage. Dynamic response is fast enough to easily track the most extreme ramp change in input PV power.

This paper presents a voltage-controlled distribution static synchronous compensator (DSTATCOM)-based voltage regulator for low-voltage distribution grids. The voltage regulator is designed to temporarily meet the grid code, postponing unplanned investments while a definitive solution could be planned to solve regulation issues. The power stage is composed of a three-phase four-wire voltage-source inverter and a second-order low-pass filter. The control strategy has three output voltage loops with active damping and two dc bus voltage loops. In addition, two loops are included to the proposed control strategy: the concept of minimum power point tracking (mPPT) and the frequency loop. The mPPT allows the voltage regulator to operate at the minimum power point, avoiding the circulation of unnecessary reactive compensation. The frequency loop allows the voltage regulator to be independent of the grid voltage information, especially the grid angle, using only the information available at the point-of-common coupling. Experimental results show the regulation capacity, the features of the mPPT algorithm for linear and nonlinear loads, and the frequency stability.

In this letter, the five-level packed U-cell (PUC5) inverter is reconfigured with two identical dc links operating as an active power filter (APF). Generally, the peak voltage of an APF should be greater than the ac voltage at the point-of-common coupling (PCC) to ensure the boost operation of the converter in order to inject harmonic current into the system effectively; therefore, full compensation can be obtained. The proposed modified PUC5 (MPUC5) converter has two equally regulated separated dc links, which can operate at no load condition useful for APF application. Those divided dc terminals amplitudes are added at the input of the MPUC5 converter to generate a boosted voltage that is higher than the PCC voltage. Consequently, the reduced dc-links voltages are achieved since they do not individually need to be higher than the PCC voltage due to the mentioned fact that their summation has to be higher than PCC voltage. The voltage balancing unit is integrated into the modulation technique to be decoupled from the APF controller. The proposed APF is practically tested to validate its good dynamic performance in harmonic elimination, ac-side power factor correction, reactive power compensation, and power quality improvement.

A novel write bitline (BL) charge sharing write driver (CSWD) and a half-V DD read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half-V DD to V DD essentially reduces the write dynamic power dissipation by 50%. Half-V DD precharging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and I on /I off ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).

To deeply understand interrupting phenomena in high-voltage circuit breakers, it is important to measure the electrical characteristics of switching arcs in high-speed gas flow at current zero. A ring-shaped capacitive probe is proposed to measure a spatial arc voltage distribution. The configuration of the probe is decided by considering the effects of arc position and arc radius. The difference between arc voltage distributions is distinguished for an interrupting current of 12 and 30 kA on interrupting tests using the circuit breaker model.

– This paper presents a zero voltage switching DC/DC converter for DC micro-grid system applications. The proposed circuit includes three half-bridge circuit cells connected in primary-series and secondary-parallel in order to lessen the voltage rating of power switches and current rating of rectifier diodes. Thus, low voltage stress of power MOSFETs can be adopted for high voltage input applications with high switching frequency operation. In order to achieve low switching losses and high circuit efficiency, asymmetric pulse-width modulation is used to turn on power switches at zero voltage. Flying capacitors are used between each circuit cell to automatically balance input split voltages. Therefore, the voltage stress of each power switch is limited at Vin/3. Finally, a prototype is constructed and experiments are provided to demonstrate the circuit performance.