Charge sharing write driver and half‐ pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

A novel write bitline (BL) charge sharing write driver (CSWD) and a half-V DD read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half-V DD to V DD essentially reduces the write dynamic power dissipation by 50%. Half-V DD precharging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and I on /I off ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).