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Different carbon-nanotube-based field-effect transistors (CNFETs) including Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs systematically from a circuit/system design perspective are compared and studied. Results reveal that CNFET design's performance is limited by the gate overlap capacitance and the quality of nanocontacts to these promising transistors.

Research is presented describing the study of linewidth interconnections on integrated circuits based on high package density and fast transmission speed.

The V transmission line was analyzed using a Yee-cell based finite-difference time-domain method to determine its characteristics for higher frequency ranges. Results showed that the V line is less dispersive than conventional microstrip lines, thus allowing faster propagation of signals. The most significant feature of the V line is the low coupling between adjacent lines, which makes it highly applicable to high density packaging.

Four package styles for an application-specific integrated circuit (ASIC) with 270 signals are presented. The package styles include tape ball grid array (TBGA), two cases of thermally enhanced laminate BGA and ceramic flip chip BGA. Evaluation of the package design was conducted employing the Graffy. Research focused on an evaluation of the best design and the electrical models of these designs. A comparison of results is described.

A novel leadframe design solution was proposed for enhancing plastic package popcorn-cracking performance. Finite element modeling was employed in examining the influence of the leadframe design on package thermal resistance and stresses. Results show that the proposed design solution can effectively stem popcorn cracking sensitivity, delamination, warpage and package stresses.

A lead frame which meets the requirement of high speed driving large scale integration (LSI) package with superior output has been developed. Such a design tackles the problem of how to spread heat effectively while also resolving the issues of speed and exact waveform transmission to LSI. The lead frame has been manufactured using TAB tape carriers by chemical etching. Furthermore, its back side plain metal laminated with high modulus adhesive enables high speed wire bonding.

The three-dimensional memory (3-DM) module meets the demand for high packaging density and memory capacity of memory modules for electronic equipment. This module has a packaging density that is four times larger than thin small outline packages (TSOP). The 3-DM also has improved electrical performance even if it is only half the length of TSOPs, is simple in structure and is less expensive than other memory devices.

Bare dice and multichip stacking technologies are among the innovative state-of-the-art packaging technologies used for very large scale integration. They are preferable over previous packaging technologies because they utilize lower power consumption which translates to minimized operational costs in addition to being lighter and more portable. Among the criteria for effective stacking technologies are silicon efficiency, thermal management, interconnection density and speed.

A superconducting multi-chip module process was proposed for high speed digital packaging applications. The approach permits superconducting microstrip connections of superconducting chips with up to 50 ohm impedances. The process also employs a low temperature polymer, benzocyclobutene dielectric with good planarization properties. Successful packaging if superconducting chips was achieved using the process.

An analytical method solves the current induced electromigration in VLSI interconnects under time-varying current stress by reducing the two-dimensional parabolic equation to two coupled one-dimensional integral equations. Standard asymptotic techniques enable the study of important large-time behavior. A series solution and an approximate small-time solution are also obtained. A theoretical study of electromigration within the drift/diffusion model is presented.

The high-density controlled-collapse chip connection (C4)/ceramic-ball-grid array (CGBA) package provides efficient reduced-instruction-set computer complimentary metal-oxide semiconductor microprocessors. The C4/CBGA package requires very small printed circuit board area and utilizes standard surface-mount equipment. The junction-to-cap thermal resistance is below 1.5 degrees celsius/watt, and electrical parasitics are low. The CGBA solder joints accomplish 3500 on/off cycles, of 25-55 degrees celsius cycling, with a 100 ppm per package failure rate.

Low-cost production of laminate-based multichip modules (MCMs) can be achieved through the use of the ball grid array technique. Ball grid arrays offer a cheap, reliable, and simple packaging alternative to fine-pitch single-chip packaging methods. Integrated circuits (ICs) and passive components, such as chip capacitors and resistors, are incorporated in the MCMs. MCMs are very efficient, low cost, and used in such applications as car radios.

The wiring length, cooling, wireability and logic signal transmission of electronic systems were modelled and incorporated into the average length model. The resulting system-level model, which uses the interconnect length as a performance metric, was then employed to analyze planar, stacked plane and three-dimensional packaging architectures. Specifically, it was used to evaluate air- and water-cooled packages in terms of the number of parameters and total circuit count.

The feasibility of using both laminate-based printed wiring board technology and thin film deposited dielectric technology for high-density interconnection networks was examined. The concept was realized in a telecommunications module consisting of two metal and one dielectric interconnect layers. The new process entailed the application of a photosensitive benzocyclobutene coating on the boards for patterning into nested vias.

A new technique is developed for the design of packaging architectures for high density electronic systems. The performance and partitioning of the electronic systems depend on the packaging architecture. The new technique is implemented in the system stimulator AUDiT, which works in X-windows, C and UNIX, with the use of CAD system AUDiT. The concurrence of this method is illustrated using model systems that are patterned with IBM RS/600 workstation as the basis.

Pitch surface mount technology (SMT) is used to design extremely compact, low cost components used for highly density, high lead content integrated circuits (IC's), which are mainly used in the design and manufacture of portable electronic items. Packaging formats for high lead count IC's include the direct chip attachment, tape carrier package (TCP), molded TCP and Quad flat pack (QFP) formats of optimization of these SMT component packing formats depends on the user's ability.

Alternatives for very fine pitch components to be surface mounted include array packaging and multichip module packages that are required due to the reduction in peripheral package chip size to below 16 mil, the smallest size allowed by the present surface mounting techniques. These surface mounting restrictions include board materials, board cleaning and replacement and change of components.

The use of a multichip package for high-speed logic die applications was investigated. The results showed that connecting several chips together allowed board size to be significantly decreased while signal propagation was enhanced. However, the use of multichip packages is constrained by their prohibitive cost.

Experimental results obtained from the reliability testing a new tape automated bonding package with a high lead count are discussed. Two prototypes, which have features inherent to hermetic and non-hermetic packages, was subjected to thermal, mechanical and environmental stresses to evaluate the reliability issues related to the new package technology. It revealed the presence of anomalies such as lid cracking and dendritic growth.

A passive laser-fiber alignment approach is examined within the framework of a new packaging technique for optoelectronic devices. The index-alignment method entails the photolithographic setting of fiducial marks on the laser chip and fiber carrier. Its implementation at 850 nm with cleaved multimode fibers resulted in a laser fiber coupling efficiency similar to that achieved by the active alignment technique.

The performance tradeoffs between single-chip module and multichip module packaging technologies is compared for digital complementary metal oxide semiconductor logic systems. The evaluation stems from the various chip and packaging innovations which have made the fabrication of very large scale integrated chips via the MCM packaging process. The latter, as revealed by the study, actually raises the packaging density and performance while lowering the cost.

The thermal resistance of the embedded silicon dioxide layer in silicon-on-insulator circuits is investigated in terms of its effect on the device's thermal performance. The packaging density of such metal oxide semiconductor field effect transistor devices are shown to be constrained by the microscale thermal conduction possible in the aluminum wires, the silicon source, drain and gate. The thermal conduction is a significant parameter at low temperatures but remains negligible at room temperatures and above.

A power metal oxide semiconductor field effect transistor (MOSFET) configuration, for fabrication via the sacrificial spacer process, is presented. It has a heavily doped, depthless p(super +) surface zone which lessens the sheet and contact resistance of the device. This was revealed in observations of such MOSFETs under switching operation where measurements of on-state resistance were four times lower than those of other MOSFETs that maintain a voltage of 150 v in theoff-state.

The reduction of the warpage of LSI package is a critical issue to ensure good solder joint connection in surface mount. In this study, different combinations of finite element and calculating methods were used to investigate the best method for predicting the thin small outline packages (TSOP) warpage. The results indicate that viscoelastic-GK calculation with relaxation of shear modulus and of bulk modulus using the multilayer shell element is the most appropriate method for predicting the warpage. All calculations confirm that a compound thickness ratio of 1.2 results in minimal warpage for a large chip TSOP. In this case, the warpage is reduced to near zero and the compound properties have little influence on warpage. However, for a small chip TSOP, a compound thickness ratio of 2.0-2.9 reduces the warpage. The warpage of small chip TSOP shows a severe saddle shape. The ratio and the magnitude of warpage depend on the compound properties. Also, the elastic method may result in a false simulation. [DOI: 10.1115/1.1339820]

We present for the first time a low-cost high-performance pin grid array (PGA) packaging technology for K-band microcircuit and microwave subsystem packaging. The first-generation package demonstrates a 20-dB return loss to 8 GHz, and the second-generation package improves the return loss to 25 dB from dc to 26.5 GHz. We apply a comprehensive analysis method, which facilitates the optimization of the radio-frequency transition into the package. It combines the time-domain reflectometry analysis and frequency-domain full-wave analysis and reduces the optimization time significantly. The theoretical analysis is verified with measurement in both frequency and time domains. The results demonstrate that the low-cost PGA can be a much more cost-effective microwave packaging solution than the traditional deep cavity metal packages. Index Terms--Hybrid integrated circuit interconnections, hybrid integrated circuit packaging, multichip modules, optimization methods.

This short paper describes a technique for the measurement of the electric near field at the package surface of microprocessors and other VLSI devices. The technique uses precision stepper motors for highly accurate placement of an electric field probe at the surface of the device to be measured. Structural resolution across the device is on the order of 400--600 [micro]m. Typical scans accumulate 10 000 data points across a variable scan area, which can be defined by device package dimensions or by the die dimensions. Characterizing a device involves a repeated series of surface scans at harmonics of the fundamental clock frequency. This paper describes the electric near field at the surface of a multichip module (MCM) composed of a processor, a flash memory, and application specific integrated circuit (ASIC). The MCM was measured while in operation in the actual circuit application. Index Terms--Near field, VLSI.