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In this work, a ferroelectric tunnel thin-film transistor (FeT-TFT) with polycrystalline-silicon (poly-Si) channel and ferroelectric HfZrOx gate dielectric is demonstrated with analog memory characteristics for the application of synaptic devices. The FeT-TFT exhibits a much lower conduction current of ∼0.032 times in transfer characteristics and maximum conductance (Gd) of ∼ 0.14 to 0.2 times in potentiation and depression operation than the FeTFT due to FeT-TFT’s carrier transport mechanism: interband tunneling. This work employed pulse widths of 75, 150, and 300 ns to modulate Gd, and it was found that using a pulse width of 75 ns could achieve low asymmetry ∼ 1 and high Gd ratio ∼ 20.63 under the consideration of operation speed. When the pulse time is increased, the potentiation and depression voltages can be significantly decreased to maintain the low asymmetry, but the Gd ratio is also reduced. In addition, the endurance characteristic of poly-Si FeT-TFT is found to be strongly related to the degradation effect of subthreshold swing due to the dynamic stress effect in the endurance measurement. This result reveals that the reliability of ferroelectric devices is not only owing to the degradation of the remanent polarization.

This paper compares the electrical characteristics of MOSFETs and tunnel FETs at different temperatures (300 ~ 10 K) by advance Sentaurus TCAD simulations at low temperature. we deliberated output characteristics of short-channel MOSFETs based on temperature. Our massiveness indicated that MOSFETs with drift-diffusion transport mechanism exhibit higher on-currents, and the subthreshold swing first decreases with temperatures linearly and then saturates at cryogenic temperatures due to source-to-drain tunneling. Also the output current is more when device cryogenically shift from 300K to 10K, However, our simulations reveal that the subthreshold swing of a tunnel FET is almost independent on temperatures. This wok also points out the challenges of a tunnel FET working at cryogenic temperatures.

This work investigates the correlation between dipole formation and surface energy at a nonplanar dielectric interface on a Si nanowire (NW) by means of molecular dynamics simulations. According to the atom and charge distribution obtained by simulations, the built-in electric field and potential are calculated at the dielectric interface based on the Poisson equation. It is found that the built-in potential is dependent on the diameter of the Si NW, which is attributed to the dependence of the surface energy difference on the surface curvature of the dielectric heterointerface, driving atom diffusion and leading to a dipole layer at the interface. The impact of the built-in potential on the threshold voltage of a transistor with a multigate configuration is discussed as well.

In this work, the ferroelectric thin-film transistor (Fe-TFT) with polycrystalline-silicon (poly-Si) channel and HfZrO x gate dielectric is fabricated to study the characteristics of non-volatile memory (NVM). Significant threshold voltage (V TH) modulation can be achieved with low pulse voltages less than ±3.5 V and pulse widths within 1 μs. In order to achieve the NVM characteristics of low voltage and high speed operation, the impact of the program/erase (PRG/ERS) pulse voltage (V PRG/V ERS) and pulse width on endurance is a critical consideration. In the study of the pulse width effect on endurance, it can be observed that the V TH in PRG-state exhibits the wake-up effect at both short and long pulse widths. In addition, with the increase of pulse width, the V TH in the PRG-state exhibits significant fatigue effect and subthreshold swing (SS) degradation effect. For V TH in the ERS-state, the increase of the pulse width also exhibits the fatigue effect and the SS degradation effect, which is dominated by the SS degradation effect at long pulse widths. In the study of the pulse voltage effect on endurance, the increase of V PRG shows the imprint effect that the V TH in either PRG- or ERS-state reveals a decreasing trend. When the V ERS increases, the SS of the PRG- and ERS-states is degraded, and the fatigue effect of the PRG-state is enhanced. Moreover, the retention characteristics of poly-Si Fe-TFTs exhibit stable characteristics at both room temperature and 50 °C.

According to quantum transport simulations, source-to-drain tunneling (SDT) has been recognized as the main cause leading to subthreshold swing ( SS ) saturation and degradation of short-channel MOSFETs at cryogenic temperatures. Generally, at a given low temperature, the steeper constant SS of thermionic currents may be overwhelmed by less-steep SDT currents at lower gate bias, degrading the average SS . Our simulations show that the SS of SDT currents is insensitive to temperatures for a MOSFET with a given channel length, accounting for SS saturation as lowering temperature. This work reveals the key points differentiating the possible reasons (interface traps, band tail and SDT) of SS saturation at cryogenic temperatures. We also study the impacts of carrier effective masses, gate-SD underlapping and a tunneling barrier at the source junction on SS saturation. SDT may pose a potential challenge and limit for scaling cryogenic CMOS of a quantum processor.

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations.

It is well known that there is a critical Sn content for a GeSn alloy, at which the conduction band edges at ${L}$ and $\Gamma$ symmetry points are aligned in energy. For GeSn tunnel FET (TFET) simulations, with a given donor concentration, this paper reveals that simulations neglecting the multivalley and nonparabolic band structure would incorrectly predict the subthreshold slope (SS) and the off-currents. We highlight the indispensability of the consideration of the multivalley band structure of GeSn for TFET simulations. This paper provides the required parameters, which may be useful for numerical simulations of other optoelectronic and electronic GeSn devices.

For the first time, a 3D stacking of MoS 2 and Si CMOS integrated with embedded RRAM is proposed and fabricated, and CMOS inverter comprised of MoS 2 nFET and Si pFET is demonstrated. Vertically stacked multiple MoS 2 channels are required for the performance matching. Resistive switching (RS) of a Ti/MoS 2 /p+-Si structure showing high ON/OFF ratio of 106 is demonstrated firstly by highly Si-compatible process. Surface modification is the key to formation of uniform and smooth stacked MoS 2 multiple channels and to enhanced resistive switching endurance. This scheme can be applied to CMOS-based bipolar RRAM 1T1R or 2T1R without increasing the cell size. Our work offers a new pathway with high feasibility of integrated 2D materials and Si FETs into CMOS to enabling 3D embedded logics and memories for future computing systems.

For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

In this work, the synaptic characteristics together with 5 bits (32 states) operation based on polycrystalline-silicon (poly-Si) ferroelectric thin-film transistor (FeTFT) with HfZrO x gate dielectric are demonstrated for the first time. A 1.2 V threshold voltage shift of memory window is obtained. The impacts of pulse time on the potentiation and depression states are studied by a modulation scheme with incremental pulse voltages. The potentiation and depression rates of the conductance (G d) states of FeTFTs are found to be asymmetric and become more severe when increasing the pulse time. In order to realize high recognition rate and accuracy of neuromorphic computing, low asymmetric nonlinearity of potentiation ( α p ) and depression ( α d ) of poly-Si FeTFTs can be achieved with the reduction of operation voltage. Low asymmetry α p − α d = 0.71 and high G d ratio ∼40 of FeTFTs are obtained based on the small pulse time of 50 ns and low average potentiation/depression voltages of 2.63/–2.69 V. When the pulse time is increased from 50 to 150 ns, the average potentiation/depression voltages can be further reduced to ∼1.59/–1.69 V for low asymmetry α p − α d = 0.25 due to the enhanced G d potentiation and depression rates, and the G d ratio is also reduced to 9.96 with the reduction of potentiation/depression voltages. The small pulse time and potentiation/depression voltages of FeTFTs are responsible for the polarization switching of the ferroelectric layer following the minor operation-loop. Compared to the depression state, it leads to more stable retention and endurance behavior of the potentiation state due to the different depolarization electric fields.

In this work, we observe the distinct V TH characteristics in the Au-free gate-first processing p-GaN/AIGaN/GaN HEMTs with two commonly used passivation layers, i.e., SiN and SiO 2 . The device with SiN shows a depletion-mode (D-mode) characteristic (V TH ,. .., -5V) whereas the device with SiO 2 passivation exhibits an enhancement-mode (E-mode) characteristic (VTH, ..., +0.7V). Furthermore, Transmission Line Measurement (TLM) devices are fabricated to investigate the effects of the passivation on two dimensional electron gas (2DEG) in p-GaN/AIGaN/GaN stack. The results indicate that a low Rsh is obtained while passivating device surface with SiN layer, suggesting that 2DEG is present, which is most probably due to an unfunctional p-GaN layer. The SIMS results indicate a high H−intensity in the p-GaN/AIGaN/GaN stack with a SiN passivation layer. Thus, P-GaN deactivation due to the formation of complex Mg-H after SiN passivation is proposed to explain the D-mode characteristic in the device with a SiN passivation layer.

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+ FB can control the electrostatic potential of the channel more efficiently for multi- ${V} _{\text{TH}}$ (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor ( $\gamma $ ) is predicted for wide range ${V} _{\text{TH}}$ modulation. Thanks to the stronger potential coupling between the channel and FB, the proposed device exhibits $\gamma $ improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi- ${V} _{\text{TH}}$ operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption.

A device design technique using tunneling barriers (TBs) for reducing the short-channel effects (SCEs) is proposed. By introducing TBs at the source and drain junctions of a Si FET, the threshold voltage ( ${V}_{\text {th}}$ ) roll-off can be significantly suppressed. This is because the TBs weaken the electrical coupling between drain bias and transmission/current spectrum in energy. Specifically, as compared with a conventional FET, the ${V}_{\text {th}}$ roll-off for channel length reduction from 20 to 5 nm is mitigated by more than 40% when a thin TB is embedded at the source junction. This paper further reveals that the TB at the source junction dominates the physical mechanism minimizing the SCEs of the TBFET, and thus the device performance can be improved appreciably by removing the TB at the drain side and by decreasing the TB height at the source side.

In this work, we observe the distinct VTH characteristics in the Au-free gate-first processing p-GaN/AlGaN/GaN HEMTs with two commonly used passivation layers, i.e., SiN and SiO2. The lower incorporated H was found in the p-GaN/AlGaN/GaN heterostructure with higher activation anneal temperature (i.e., 700 °C). Furthermore, Photoluminescence (PL) spectrum demonstrates a higher blue luminescence (BL) intensity after higher annealing treatment. The X-ray photoelectron spectroscopy (XPS) spectrum near valence band edge depicts a similar valence band maximum (VBM) characteristic, by means no impact on p-GaN surface bending by using distinct thermal treatment. The device with SiN shows a depletion-mode (D-mode) characteristic (VTH ~ -5 V) whereas the device with SiO2 passivation exhibits an enhancement-mode (E-mode) characteristic (VTH ~ +0.7 V). Moreover, Transmission Line Model (TLM) devices are fabricated to investigate the effects of the passivation on two-dimensional electron gas (2DEG) in p-GaN/AlGaN/GaN stack. The results indicate that a low Rsh is obtained while passivating device surface with SiN layer, suggesting that 2DEG is present, which is most probably due to an unfunctional p-GaN layer. The secondary ion mass spectrometry (SIMS) results indicate a high hydrogen intensity in the p-GaN/AlGaN/GaN stack with a SiN passivation layer. Thus, the p-GaN deactivation process that correlates to the formation of complex Mg H after SiN passivation is proposed to explain the D-mode characteristic in the device with a SiN passivation layer.

This paper investigates the impacts of typical semiconductor material properties—electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core–shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core–shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications.

By using numerical simulations, we demonstrate that a proper source/drain contacting strategy not only boosts the on-currents, but also eliminates random dopant fluctuation (RDF) of a junctionless FET (JLFET). Two contacting strategies for JLFETs with a wide range of doping concentration ( $10^{10} \sim ~10^{20}$ cm $^{-3})$ are compared and discussed: metal–insulator–semiconductor (MIS) and metal–semiconductor (MS) contacts. The Schottky barrier at the MS contact shows more negative impacts on the on-current when the JLFET is not doped heavily. With dopantless and unintentionally doped Si (doping concentration $= 10^{10} \sim ~10^{17}$ cm $^{-3}$ for both n-type dopants and p-type dopants), the JLFETs with MIS contacts may exhibit higher on-currents than those with MS contacts and show almost the same transfer characteristics. The later result actually implies that the JLFET with MIS contacts possesses the immunity against RDF.

By adopting the charge-plasma concept, dopingless FETs with metal-semiconductor and metal–insulator–semiconductor (MIS) contacts in parallel at the source/drain (SD) have been studied in this letter. Currents are found to flow mainly through the MIS contacts for a given SD metal workfunction when the insulator thickness is thin enough. In order to avoid the possible penalty caused by Fermi level pinning, the dopingless FET with only SD MIS contacts has been proposed as well. The impacts of insulator material parameters, such as bandgap, electron affinity, dielectric constant, and physical thickness, on the electrical characteristics of the dopingless FET have been investigated systematically. Based on numerical simulations, this letter provides a general guideline with physical insights for designing dopingless FETs with high-permittivity insulator at the SD MIS contacts.

This paper clarifies for the first time the origin of ferroelectricity in the Negative Capacitance Field-Effect Transistors (NCFETs) by molecular dynamics (MD) simulation. MD simulation considering atomic interactions between all atoms enables accurate predictions for the microstructure even at all interfaces. By incorporating the results from MD simulations into a kinetic model, it is able to predict the conditions of crystallization and phase transition during RTP and cooling processes that govern ferroelectricity in FETs. Our simulation reveals that the comparable interfacial energy between o-and t-phase, and in-plane tensile stress from metal capping or interfacial layers (ILs) enable more phase transition from t-to o-phase, and more ferroelectricity in NCFETs. Finally, design methodology to maintain the electric variation of NCFETs is also proposed

In this letter, the Metal-Insulator-Semiconductor (MIS) contacts are fabricated on the GaN substrates and compared to the Metal-Semiconductor (MS) contacts. To alleviate the Fermi level pinning effect at the Metal-Semiconductor interface, an Al 2 O 3 interfacial layer (IL) (1 ~ 3 nm) is used to form the MIS contacts. By comparing the electrical characteristics, the contact with 0nm Al 2 O 3 layer, i.e., MS contact, shows a lowest current compared to the contacts with an Al 2 O 3 IL, i.e., MIS contact. Furthermore, the current at 0.5V in the fabricated Transmission Line Measurement (TLM) device with 1nm Al 2 O 3 IL is 103 times higher the one without an Al 2 O 3 IL. This proves that inserting an Al 2 O 3 IL could mitigate the Fermi level pinning, resulting in a low Schottky barrier height. Finally, based on the TLM analysis, the resistivity of 5.1×10−4 Ω.cm2 is demonstrated in the MIS contact with 1nm Al 2 O 3 IL.

In this work, polarization-dependent time-dependent dielectric breakdown in ferroelectric HZO Ge MOSCAPs is presented. First, ferroelectric HZO Ge MOSCAPs with and without in-situ NH3 plasma interfacial layer treatment exhibit the two distinct remnant polarization (Pr). Secondly, the device with a larger Pr shows a higher gate leakage current and smaller time-to-breakdown (tBD) compared to the device with a smaller Pr. Then, a physical model based on the high probability of the electron tunneling accelerating the formation of the percolation path is proposed. Finally, the device with large Pr shows a lower extrapolated operating voltage. However, more than 1.5 V of the extracted operation voltage for 1% failure of 10 year lifetime in the device with large Pr still can be obtained.

The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (T FE ~2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO 2 .

Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 107 and 106 for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.

With relaxed SiGe, this work elaborates the correlation of semiconductor band edges and source-drain metal workfunction for the electrical characteristics of p- and n-channel FETs based on numerical simulations. For a given high workfunction source-drain metal, it is found that the on-current, threshold voltage and off-current of p-channel devices increase monotonously with the Ge mole fraction. The trend of the n-channel devices, however, seems more complicated, but it can be interpreted by the band edge variation of SiGe alloy.

Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO x (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al 2 O 3 IL results in paraelectric behavior, HZO on GeO x IL exhibits significant FE. High I on /I off (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L g ) of 60 nm and a FE-HZO/GeO x gate stack.

This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1- μm gate length device shows on current in excess of 20 μA/μm at VGS=VDS=1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ~ 0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.

Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically.

For the purpose of calibrating the nonlocal Kane band-to-band tunneling model for Si1-xGex based on TCAD simulations, SiGe p-i-n tunnel diodes are fabricated by epitaxial growth. The quality of the tunnel junction is examined by the ideality factors of the diodes and the band-to-band tunneling regime is determined based on activation energy extractions. By comparing experimental data to simulations with theoretically calculated prefactors of Kane's model, we conclude that the TCAD simulator overestimates the tunneling current in strained Si1-xGex diodes.

The optimized tunnel field-effect transistor with a gate electrode overlapping the source region exhibits a steeper subthreshold swing (SS) and a higher on-state tunneling current than the transistor with a gate on the channel only. In the presence of a counterdoped pocket in the source region underneath the gate electrode, the vertical tunneling component dominates over the unwanted lateral tunneling component, and the performance variability is reduced compared to its no-pocket configuration. The optimal pocket thickness, which is a tradeoff between realistic gate work function and the desired SS, is dependent on the bandgap, electron or hole effective mass, permittivity, and tunneling orientation of semiconductor materials, as analyzed in detail in this paper. A numerical procedure is provided to determine the optimal pocket thickness for arbitrary semiconductor materials.

We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge09Si01 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs.

A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth ( 107) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.

In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperature instability (NBTI), and hot-carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep-trap states of the effective interfacial layer (IL), tail-trap states of poly-Si grain boundaries, and electron trapping of the gate dielectric is observed for the PBS and PBTI of the LTPS-TFT. In addition, both the deep- and tail-trap states of the effective IL are generated under NBS and NBTI of the LTPS-TFT.

In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO 2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I on / I min current ratio 1.9 × 10 6 are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO 2 /polysilicon interface. Significant improvements on subthreshold swing and I min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage ∼1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I on / I min current ratio 1.21 × 10 7 , which is suitable for the application of system-on panel (SOP).

In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current ION and reduce the off leakage current IOFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the ION/IOFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric

In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET) with high-κ gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-κ offset spacer to further improve the on-state driving current Ion to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current Ioff by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-κ material as a spacer. This enhanced fringing electric field can markedly increase Ion/Ioff current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.

For the first time, a novel junctionless (JL) FinFET structure with a shell doping profile (SDP) formed by molecular monolayer doping (MLD) method and microwave annealing (MWA) at low temperature is proposed and studied. Thanks to the ultra thin SDP leading to an easily-depleted channel, the proposed JLFinFET can retain the ideal subthreshold swing (∼ 60 mV/dec) at a high doping level according to simulations. Poly Si based JLFinFETs processed with MLD and MWA exhibit superior subthreshold swing (S.S. ∼ 67mV/dec) and excellent on-off ratio (>106) for both n and p channel devices. Threshold voltage (V TH ) variation due to random dopant fluctuation (RDF) is reduced in MLD-JLFinFETs, which can be attributed to the molecule self-limiting property of MLD on the Si surface and quasi-diffusionless MWA at low temperature. Our results reveal the potential of the proposed SDP enabling a JLFET showing reduced variation and outstanding performance for low power applications.

Group IV based tunnel field-effect transistors generally show lower on-current than III-V based devices because of the weaker phonon-assisted tunneling transitions in the group IV indirect bandgap materials. Direct tunneling in Ge, however, can be enhanced by strain engineering. In this work, we use a 30-band k.p method to calculate the band structure of biaxial tensile strained Ge and then extract the bandgaps and effective masses at Gamma and L symmetry points in k-space, from which the parameters for the direct and indirect band-to-band tunneling (BTBT) models are determined. While transitions from the heavy and light hole valence bands to the conduction band edge at the L point are always bridged by phonon scattering, we highlight a new finding that only the light-holelike valence band is strongly coupling to the conduction band at the Gamma point even in the presence of strain based on the 30-band k.p analysis. By utilizing a Technology Computer Aided Design simulator equipped with the calculated band-to-band tunneling BTBT models, the electrical characteristics of tensile strained Ge point and line tunneling devices are self-consistently computed considering multiple dynamic nonlocal tunnel paths. The influence of field-induced quantum confinement on the tunneling onset is included. Our simulation predicts that an on-current up to 160 (260) mu A/mu m can be achieved along with on/off ratio > 10(6) for V-DD = 0.5V by the n-type (p-type) line tunneling device made of 2.5% biaxial tensile strained Ge. (C) 2014 AIP Publishing LLC.

In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated for the first time. The devices of low threshold voltage VTH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility muFE ~ 240 cm2/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO2 gate dielectric with the effective oxide thickness of 5.12 nm.