3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

For the first time, a 3D stacking of MoS 2 and Si CMOS integrated with embedded RRAM is proposed and fabricated, and CMOS inverter comprised of MoS 2 nFET and Si pFET is demonstrated. Vertically stacked multiple MoS 2 channels are required for the performance matching. Resistive switching (RS) of a Ti/MoS 2 /p+-Si structure showing high ON/OFF ratio of 106 is demonstrated firstly by highly Si-compatible process. Surface modification is the key to formation of uniform and smooth stacked MoS 2 multiple channels and to enhanced resistive switching endurance. This scheme can be applied to CMOS-based bipolar RRAM 1T1R or 2T1R without increasing the cell size. Our work offers a new pathway with high feasibility of integrated 2D materials and Si FETs into CMOS to enabling 3D embedded logics and memories for future computing systems.