Back to Search Start Over

First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

Authors :
M. Miura
T.-Z. Hong
C.-J. Tsai
X.-R. Yu
Y.-T. Huang
Y. Chuang
Hiroyuki Ishii
Seiji Samukawa
Chia-Min Lin
G.-L. Luo
C.-J. Su
Jiun-Yun Li
Kuo-Hsing Kao
T.-Y. Chu
Tatsuro Maeda
Po-Jung Sung
W. C.-Y. Ma
H.-Y. Chao
Ta-Chun Cho
Hisu-Chih Chen
W.-H. Chang
Guo-Wei Huang
N.-C. Lin
S.-M. Luo
Kun-Lin Lin
Jia-Min Shieh
Toshifumi Irisawa
K.-P. Huang
Fu-Kuo Hsueh
Chien-Ting Wu
Jianqing Lin
C.-Y. Yang
W.-F. Wu
S.-T. Chung
J.-H. Tarng
Tien-Sheng Chao
Ricky W. Chuang
Darsen D. Lu
Yeong-Her Wang
Yao-Jen Lee
A. Agarwal
Yiming Li
M.-J. Li
Wen-Kuan Yeh
Source :
2020 IEEE International Electron Devices Meeting (IEDM).
Publication Year :
2020
Publisher :
IEEE, 2020.

Abstract

For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

Details

Database :
OpenAIRE
Journal :
2020 IEEE International Electron Devices Meeting (IEDM)
Accession number :
edsair.doi...........b0b85a6f84bd690a0af5c9400f93a632
Full Text :
https://doi.org/10.1109/iedm13553.2020.9372001