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A 1.2-Mpixel indirect time-of-flight (ToF) CMOS image sensor is presented to lower peak current and to cancel out multi-user interference. The proposed 4-tap 3.5- $\mu \text{m}$ demodulation pixel is optimally designed to improve quantum efficiency (QE) and demodulation contrast (DC). A new “multiple-interleaving” scheme is proposed to reduce the peak current and self-compensate fixed-pattern phase noise (FPPN) with the minimal side effect of DC imbalance. To cancel out interference from the other ToF sensors, a multi-user interference cancellation (MUIC) scheme based on pseudorandom modulation is adopted. From the measurement results, we achieve a high QE of 38% at 940 nm and a high DC of 96% and 80% at 100- and 200-MHz modulation frequencies, respectively. With the superior pixel performance, the depth noise of $\times $ 2 binning modes, respectively. The multiple-interleaving scheme suppresses the peak current to less than 0.9 A and removes the column FPPN with constant DC for the whole pixel array. The proposed MUIC proves that at least two interferers can be successfully rejected. The sensor chip is fabricated in a two-stack process with 65 nm for the top die and 65 nm for the bottom die.

This paper presents a low-random noise of 2.6 e-rms, a low-power of 116.2 mW at video rate, and a high-speed up to 960 fps 2-mega pixels global-shutter type CMOS image sensor (CIS) using an advanced DRAM technology. To achieve a high performance global-shutter CIS, we proposed a novel architecture for the digital pixel sensor which is a remarkable global-shutter operation CIS with a pixel-wise ADC and an in-pixel digital memory. Each pixel has two small-pitch Cu-to-Cu interconnectors for the wafer-level stacking, and the pitch of each unit pixel is less than 5 μm which is the world’s smallest pixel embedding both pixel-level ADC and 22-bit memories.

Sub-micron pixels have been widely adopted in recent CMOS image sensors to implement high resolution cameras in small form factors, i.e. slim mobile-phones. Even with shrinking pixels, customers demand higher image quality, and the pixel performance must remain comparable to that of the previous generations. Conventionally, to suppress the optical crosstalk between pixels, a metal grid has been used as an isolation structure between adjacent color filters. However, as the pixel size continues to shrink to the sub-micron regime, an optical loss increases because the focal spot size of the pixel’s microlens does not downscale accordingly with the decreasing pixel size due to the diffraction limit: the light absorption inevitably occurs in the metal grid. For the first time, we have demonstrated a new lossless, dielectric-only grid scheme. The result shows 29 % increase in sensitivity and +1.2-dB enhancement in Y-SNR when compared to the previous hybrid metal-and-dielectric grid.

We developed a dual pixel with accurate and all-directional auto focus (AF) performance in CMOS image sensor (CIS). The optimized in-pixel deep trench isolation (DTI) provided accurate AF data and good image quality in the entire image area and over whole visible wavelength range. Furthermore, the horizontal-vertical (HV) dual pixel with the slanted in-pixel DTI enabled the acquisition of all-directional AF information by the conventional dual pixel readout method. These technologies were demonstrated in 1.4μm dual pixel and will be applied to the further shrunken pixels.

For years, there has been a strong drive for sub-micron pixel development, in spite of reaching the visible light diffraction limit, because a smaller pixel pitch of CMOS image sensors (CISs) is inevitably required for ever-miniaturizing camera modules as mobile devices incorporate more cameras, few of which are dedicated to ultra-high-resolution zoomed images [1]. To that end, image sensor vendors have tried to find new ways to avoid reduction in sensitivity and more crosstalk in the sensor through pixel architecture change and/or fabrication process refinement [2] –[4]. For example, a $0.7 \mu m$ pixel sensor was demonstrated with acceptable photodiode (PD) full-well capacity (FWC) of $\gt 6$,000e- as well as signal-to-noise ratio (SNR) of $\sim32$ dB without optical/electrical crosstalk by employing state-of-the-art full-depth deep-trench isolations (FDTIs). [4] However, further scaling requires elaborate fabrication innovation and layout ideas. At the same time, meeting every aspect of pixel performance compared to the previous generation becomes even more difficult, e.g., with respect to dark or illuminated characteristics, fixed-pattern or temporal noises, etc. The latter, in particular, is associated with in-pixel source-follower (SF) amplifiers. Therefore, electrical performance of scaled in-pixel transistors cannot be overlooked. In this paper, a 32-megpixel (MP) CIS with $0.64 \mu m$ unit pixels is demonstrated with FDTI design. Innovations in terms of fabrication and design to achieve this performance with scaling are discussed.

The evolution of 3D depth-sensing technology enables various applications in mobile devices, from conventional photography enhancement (e.g., autofocus and bokeh effect) to new applications such as augmented reality and 3D scanning. Usually, 3D depth sensors operate with RGB color sensors for image fusion; the spatial resolution of depth sensors should be compatible to that of RGB sensors for better image fusion quality, which requires mega-pixel depth sensors. Among different depth-sensing techniques, only indirect time-of-flight (ToF) sensors can generate higher resolution depth maps with smaller system cost and power [1,2]. Recent indirect ToF sensors have achieved continuous improvements in depth performance [1–4]. However, one of the issues with indirect ToF sensors is peak current during exposure time [1,2]. To solve the issue, current spreading can be adopted by driving each column group in a different time point; the resulting column fixed-pattern phase noise (FPPN) is compensated by time-interleaving two opposite-directional delay chains [2]. However, this approach suffers from demodulation contrast (DC) degradation around the edge of the pixel array, by combining two different phase signals at the pixel level [2]. Another issue for indirect ToF sensors is multi-user interference [5]. When multiple ToF cameras with the same modulation frequency shine light onto the same object, the reflected light signals interfere each other, which may distort depth information. In this work, a mega-pixel indirect ToF sensor is reported with the solutions for the two issues: 1) peak current mitigation with minimal side-effect, and 2) multi-user interference cancellation.

A 2.8μm 4-tap global shutter pixel has been realized for a compact and high-resolution time of flight (ToF) CMOS image sensor. 20,000 e- of high full-well capacity (FWC) per a tap is obtained by employing a supplementary MOS capacitor. 36% of high quantum efficiency (QE) has been achieved by backside scattering technology (BST) and thick silicon process. In addition, demodulation contrast (DC) is improved to 86 % by additional deep photodiode doping process for static potential gradient in a photodiode.

A 0.8μm-pitch 108 megapixels (Mp) ultrahigh-resolution CMOS image sensor has been demonstrated for mobile applications. The Nonacell was developed through a 3x3 color filter and 1x3 shared pixel structures which can be operated the 3 binning mode to achieve 12Mp resolution and improve low-illuminance signal-to-noise ratio (SNR) characteristic. The full-well capacity (FWC) of Nonacell was achieved up to 18,000e- using FD-shared dual conversion gain (CG) technology, and excellent high-illuminance SNR was demonstrated.

As the automotive and AI industries are expanding rapidly, global-shutter (GS) image sensors are playing a more significant role in the perception system. More specifically, GS image sensors are required in various fields involving IR, including the face-ID in mobile devices, the driver monitoring system in automotive applications, and factory automation. GS image sensors are necessary for these applications because they can capture freeze-frame images without motion distortion due to their advantage in the pixel operation method. The simultaneous pixel exposure and in-pixel storing capability allow GS image sensors to achieve high-quality imaging, while the sequential pixel exposure and readout of rolling-shutter (RS) image sensors results in image distortion known as the jello effect. For mobile and automotive applications, a small form factor while maintaining a low parasitic light sensitivity (PLS) and low noise is crucial. In conventional backside illuminated (BSI) charge-domain GS image sensors, a light-shielding structure over the storage area must be formed in order to suppress the influence of parasitic light during the readout operation. Therefore, the introduction of such a light-shielding structure reduces the effective photodiode area, which results in a loss of full-well capacity (FWC), light sensitivity of the sensor, and pixel scalability.

As the smart mobile device market continues to grow and the number of cameras per device rapidly increases, demand for CMOS image sensors (CIS) also increases. Two major trends in mobile device cameras are: (1) adopting smaller pixels that enable greater pixel count at similar optical format, and (2) bigger pixels for higher image quality. To be more specific, front-facing cameras have a trend towards smaller pixels, while rear main cameras have a trend towards both smaller and bigger pixels. The optical format of front-facing cameras is especially limited due to existing bezel-less or border-less display designs, yet higher resolution still-shot and video (such as 4K UHD) recording is desired. To implement greater pixel count in a limited camera module size, scaling of pixel size is required. The main challenges are to maintain acceptable photodiode full-well capacity (FWC) and sensitivity, while suppressing optical crosstalk [1]. To completely eliminate both electrical and optical crosstalk, deep-trench isolation (DTI) has evolved from early BDTI (Back-side DTI) to current FDTI (Front-side DTI) technology, which is also called full-depth DTI. In this paper, a 44Mpixel CIS with 0.7µm pixels using full-depth DTI is demonstrated.

11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performance has been improved by 25% in ring oscillator AC frequency at same Iddq or 42% power reduction is achieved. Adopting already mature 14nm and 10nm process technology, we can setup and demonstrate fast yield ramp.

10nm 2nd generation BEOL technology is described with an optimized illumination system and multi-patterning lithography. While the optimized illumination system offered a possibility to pattern reduced metal pitches in the preferred orientation, difficulties of T-T and T-S patterning still remained. It was overcome by increasing the number of available multi-patterning colors from 2 to 4. First-ever implementation of LELELELE with tight inter-color misalignment control increased scalability up to 17.1% and was demonstrated with SRAM 128Mb yield.

There are growing opportunities and demands for image sensors that produce higher-resolution images, even in low-light conditions. Increasing the light input areas through 3D architecture within the same pixel size can be an effective solution to address this issue. Organic photodiodes (OPDs) that possess wavelength selectivity can allow for advancements in this regard. Here, we report on novel push–pull D−π–A dyes specially designed for Gaussian-shaped, narrow-band absorption and the high photoelectric conversion. These p-type organic dyes work both as a color filter and as a source of photocurrents with linear and fast light responses, high sensitivity, and excellent stability, when combined with C60 to form bulk heterojunctions (BHJs). The effectiveness of the OPD composed of the active color filter was demonstrated by obtaining a full-color image using a camera that contained an organic/Si hybrid complementary metal-oxide-semiconductor (CMOS) color image sensor.

High field electrical stress effects on the mid-gap interface trap density (Dit0) and geometric mean capture cross sections (σ0) in n-MOSFETs have been studied using the pulsed interface probing method. The results show that the PIP technique is sensitive to changes in mid-gap trap cross section values caused by the Fowler–Nordheim (F–N) electrical stress. The decrease of mid-gap trap cross sections following the F–N tunneling injection is found. Our works also provide further insight into the influence of electrical stress on mid-gap interface trap generation in n-MOSFETs without the assumption of the constant capture cross section value during F–N stresses.

According to the trend towards high-resolution CMOS image sensors, pixel sizes are continuously shrinking, towards and below 1.0μm, and sizes are now reaching a technological limit to meet required SNR performance [1-2]. SNR at low-light conditions, which is a key performance metric, is determined by the sensitivity and crosstalk in pixels. To improve sensitivity, pixel technology has migrated from frontside illumination (FSI) to backside illumiation (BSI) as pixel size shrinks down. In BSI technology, it is very difficult to further increase the sensitivity in a pixel of near-1.0μm size because there are no structural obstacles for incident light from micro-lens to photodiode. Therefore the only way to improve low-light SNR is to reduce crosstalk, which makes the non-diagonal elements of the color-correction matrix (CCM) close to zero and thus reduces color noise [3]. The best way to improve crosstalk is to introduce a complete physical isolation between neighboring pixels, e.g., using deep-trench isolation (DTI). So far, a few attempts using DTI have been made to suppress silicon crosstalk. A backside DTI in as small as 1.12μm-pixel, which is formed in the BSI process, is reported in [4], but it is just an intermediate step in the DTI-related technology because it cannot completely prevent silicon crosstalk, especially for long wavelengths of light. On the other hand, front-side DTIs for FSI pixels [5] and BSI pixels [6] are reported. In [5], however, DTI is present not only along the periphery of each pixel, but also invades into the pixel so that it is inefficient in terms of gathering incident light and providing sufficient amount of photodiode area. In [6], the pixel size is as large as 2.0μm and it is hard to scale down with this technology for near 1.0μm pitch because DTI width imposes a critical limit on the sufficient amount of photodiode area for full-well capacity. Thus, a new technological advance is necessary to realize the ideal front DTI in a small size pixel near 1.0μm.

According to the high resolution trend in CMOS image sensor, pixel size is shrinking continuously towards and beyond 1.0 μm and reaching technical barrier to get the required performance. To achieve high SNR's in both low and high illumination, while high sensitivity and high full well capacity are essential but limited by pixel size of around 1.0 μm, reduction of crosstalk is more efficient way, which makes `effectively' sensitivity and full well capacity higher. In this paper, successful demonstration of ultralow crosstalk high SNR pixel will be presented.

New isolation scheme for CMOS image sensor pixel is proposed and its improved dark current performance is reported. It is well known that shallow trench isolation (STI) is one of major sources of dark current in imager pixel due to the existence of interfacial defects at STI/Si interface. On the account STI-free structure over the whole pixel area was previously reported for reducing dark current. As the size of pixel pitch is shrunk, however, it becomes increasingly difficult to isolate in-pixel transistors electrically without STI. In this work, we implemented hybrid type isolation scheme of removing STI around photodiode to suppress the dark current and remaining STI near transistors to guarantee the electrical isolation of transistors in pixel. It was successfully achieved that the dark current was significantly reduced by removing the STI around the photodiode together with normal operation of in-pixel transistors.

This paper presents a BSI(backside-illumination) 14µm-pixel QVGA CMOS image sensor SOC(System On a Chip) measuring TOF(Time-Of-Flight) by 20MHz-intensity modulation of 850nm-wavelength light. The 34% of overall QE(Quantum Efficiency) at 850nm-wavelength is acquired by BSI structure and optimized micro-lens. The DE(Depth Error) less than 1.5% within 6m is achieved with imaging lens of f/1.2 and LED array of which the optical intensity is 0.6W/m2 at 1m-distance. Additionally, the depth linearity is measured as that the coefficient of determination is equal to 0.9999. In order to operate under background light illumination on a scene, dual CG(Conversion Gain) scheme is implemented in each pixel.

Endurance failures are classified into three groups, all of which originate from the atomic transport of GST due to electromigration in molten phase. Based on the analysis, cell structure insusceptible to the atomic transport and for better cycling performance was proposed.

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

As pixel sizes continue to scale down, backside-illuminated (BSI) technology has been recently adopted as a solution to improve pixel SNR performance [1,2]. In addition, as the application of image sensors widens from digital still cameras to digital camcorders, high-resolution and high-speed operation are required. This paper presents 1/2.33-inch 14.6Mpixel CMOS image sensor employing a 1.4μm BSI pixel architecture with a floating-diffusion (FD) boosting scheme that enables high SNR and high speed read-out.

High speed imaging is one of the fastest growing semiconductor markets. Growth is currently driven by consumer and industrial applications such as HD video, slow motion play-back, machine vision, 3D range capture, and robotics. This forum will present chip architectures, circuits, and system-level solutions used in CCD and CMOS image sensors for high speed cameras. Technology topics include photon detection devices, pixel circuits and array readout circuits, A/D converters, image processing and interface circuits presented by world leading experts from industry and academia. The potential applications of this technology will be demonstrated by ultra high speed capture solutions for 3D range imaging and robotics. For advanced applications, techniques for outputing high-throughput pixel data using analog or digital interfaces are described. The forum will conclude with a panel discussion where the attendees have the opportunity to ask questions and to share their views, and this all-day forum encourages open information exchange. The targeted participants are circuit designers and concept engineers working on image sensor and camera system design.

The imaging area is one of the most exciting and dynamic areas of the electronics industry. The pervasion of imaging into society was boosted significantly when it was included inside most mobile phones. Although this a huge driver of the industry, there are still new applications that continue to push the growth and innovation of the technology. This session highlights advances in Image Sensors in several areas, including readout circuitry, pixels, and applications.

As pixel size of image sensors shrinks down rapidly, we are reaching technical barrier to get the required low light performance. In this paper, recent advanced technologies such as backside illumination, new color filter array, low F-number with extended depth of field technologies, etc. are introduced to overcome such a barrier. It is shown that the integration of these advanced sensor technologies can make pixel size shrink down toward 1.0 mum with the required performance.

A 1/2-inch 7.2Mpixel CMOS image sensor with 2.25mum pixels employs a 4-shared pixel structure with pixel-level charge summation. It achieves a 57% fill factor, full well capacity of 14ke- with 41dB maximum SNR at full resolution, 8e-random noise, 15ke-/lux-s sensitivity, and a 3dB increment in SNR for pixel-level charge summation and sub-sampling operation. A 0.13mum Cu process is used

Extended abstract of a paper presented at Microscopy and Microanalysis 2013 in Indianapolis, Indiana, USA, August 4 – August 8, 2013.

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6 approximately 0.8 mu m/sup 2/ having more than 30 fF of cell capacitance with a stack structure, has been realized. >

High average output power over +3 dBm was obtained in 10 Gb/s electro-absorption modulated laser for transmission over 80 km by amplifying the modulated signals through monolithically integrated semiconductor optical amplifier, for the first time to our knowledge.

Extended abstract of a paper presented at Microscopy and Microanalysis 2012 in Phoenix, Arizona, USA, July 29 – August 2, 2012.