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A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5 ?m CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5 mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900 e. The power dissipation without the output buffer is about 2.6 mW.

A novel data-sparsification method for multi-channel radiation detector readout ASICs is proposed. Based on the self-triggering approach, the scheme operates as follows: when one channel is being read out, the trigger signal from other channels is delayed one or more clock cycles and then processed. In this way, the dead time, during which the circuit fails to respond to the input, is reduced and so is the error rate. A 16-channel readout ASIC has been designed in a 0.5um DPTM CMOS technology. The feasibility of this novel sparse readout method is verified by simulation. Theory analysis and calculation show that the error rate is approximately 2.5%, and is reduced by about 37% compared with the conventional scanning scheme, assuming a 16-channel system with an event rate of 100 K/s per channel.

This paper presents a low jitter adaptive-bandwidth charge pump PLL with an improved passive filter. With an adaptive bandwidth, the proposed PLL maintains optimal performance over its whole operating range. In order to improve the jitter performance of the PLL, matching technique is employed in the charge pump, and a voltage-to-voltage converter is used to achieve a low gain VCO. The novel circuit has been implemented in 0.35 mum CMOS process. Post simulation results show that the PLL can scale its loop dynamics proportional to the operating frequency and has good jitter performance within its operating range from 100 MHz to 1.1 GHz.

This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology. The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit. The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array. The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function. The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage. Defective pixel correction is also implemented in this circuit. The simulation results show that the TDI function is correctly implemented and the linearity is improved from 96.15% to 97.70% (without the common output stage) at the expense of a little increase of power dissipation.

A full parasitic capacitance model of diode-class ESD structures is presented in this paper, including not only the reversed-bias capacitance model in the circuit normal operation but the forward-bias capacitance model under the ESD stress. This model successfully calculates the ESD-induced capacitances which degrade the high-speed mix-signal and RF IC performances, and also deals with the puzzle why diode-class structures have a low discharge level with a small turn-on resistance. And a novel parameter CESDV, which is named as the parasitic capacitance unit kV ESD level for the ESD device, is also proposed. The experimental results imply that the MOS-bounded diode has a CESDV about 15fF/kV, far smaller than the normal diode about 30fF/kV. It is shown that the MOS-bounded diode is an appropriate choice for the high-speed mix-signal and RF ICs ESD protection.

A fast-settling, temperature-insensitive voltage buffer is analyzed and designed. Class AB output stage in the buffer leads to high slew rate with relatively low power dissipation. The current switch not only sets the quiescent current of the output transistors, but also compensates the variation of Vth with temperature, which makes the buffer workable in a wide range of temperature. Simulation results show that the 0.1% settling time with 2V input step and 2OpF load is always less than 165ns when the temperature varies from 0°C to 100°C while the dissipation is less than 3mW. The die area without pads in 0.5um CMOS process is 350* 150um2.

A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 6.74mw, which reduced more than 85%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers. A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 0.5μm DPDM n-well CMOS process.

The paper presents a power analysis model for adiabatic SRAM. According to different performance frequency and different memory size, we simulate, analyze and compare adiabatic SRAM's power characteristics and propose the model. Based on the power analysis model, a scheme of array-division for adiabatic SRAM is presented. With array-division structure, the power dissipation is related to m, which is the array-division value. When the value increases, the main source of SRAM power is changed from word-line and cell-clock to decoder

In this paper, instead of the traditional experience-based trial-and-error ESD design approach, a novel ESD protection design methodology is proposed, which resolves the costly and time-consuming problems of high-performance ESD protection development in deep-submicron CMOS technology. And this novel design method is conducted and verified in a 0.5-mum CMOS technology to accomplish I/O cell design of a CMOS ASIC library, whose human-body-model ESD level can be great than 4.5kV. To effectively improve latchup free capability, latchup prevention design is also discussed

The paper presents one kind of adiabatic driver for multi-port register file. Between decoder part and memory array, the adiabatic driver is added to reduce the power dissipation of word-line. At the same time, we also designed adiabatic sensing amplifier for register file. Adiabatic circuits require trapezoidal wave or sinusoidal wave as inputs and outputs. But the register file presented in this paper hasn't any requirement for inputs, so it can be easily used in embedded microprocessors. The experiment results show that the power dissipation of adiabatic register file reduces 40% versus traditional register file.

A new structure of low-noise CMOS differential amplifier has been presented in this paper. The structure is mainly based on a load of common-gate MOSFETs with resistances in series at sources (CG-R load), which does not increase complication of the circuit. This structure decreases 1/f noise of the load by a (1 + g/sub m2/R) /sup 2/ coefficient, while keeps the voltage gain high. The simulation result for the given example reveals an average reduction of 90% for load noise at low frequencies, compared with current-mirror load (CM load).

A novel method to adjust gain in CMOS infrared (IR) readout integrated circuit (ROIC) which is suitable for the application of small pixel size has been proposed in this paper. Current mirror is inserted in the pixel to adjust gain. Two comparators have been added outside of the pixel and provide the decision to select different gains. Adjustable gain makes the design of following signal process circuit easier and allows long integration time to increase SNR. With this method of automatic gain adjust, ROIC can deal with the current that varies from 40nA to 300nA, with the integration capacitor of 2pF and the integration time of 40/spl mu/s. An experimental 4/spl times/4-pixel ROIC has been designed and it will be fabricated with 0.5/spl mu/m DPDM n-well CMOS process.

A design model is proposed to exactly simulate operating principles of gate-coupling NMOS (GCNMOS) ESD protection circuit under ESD stress. Using this model, adequate coupling capacitor C/sub n/ and coupling resistor R/sub n/ can be calculated to improve the efficiency of GCNMOS ESD protection circuit.

SRCMOS (self-resetting CMOS) is one kind of popular technique which can be used for designing high-speed circuits. This paper presents a new kind of locally self-resetting SRCMOS technique. According to the operational principle that the reset signal is generated by a mechanism local to its stage, the technique can realize high-speed circuits and has low design complexity. Based on the locally SRCMOS technique, the paper presents the design of a 32 word/spl times/64 bits 2write/6read eight-port register file. Using 1.8 V 0.18 /spl mu/m CMOS technology, simulation results show that the write access delay of the register file is 700 ps, and read access delay is 910 ps.

An op-amp with a push-pull output stage for infrared focal plane array (IRFPA) readout integrated circuit (ROIC) is described in this paper. It works in the class AB mode with little die area. The op-amp is simulated by the SMIC 0.35-/spl mu/m CMOS process. The circuit is designed to operate from a single 5 V power and drive a capacitive load of 15 pF. The unity gain-bandwidth (GBW) is 30 MHz. the rising slew rate (SR) 34 V/s. and the falling slew rate (SR-) 39 V/s. The common-mode input and the output swing are almost 5 V.

A novel dual-window readout structure is presented in this paper. The ROIC with this structure can work in two modes: normal mode and windowing mode. The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode. Furthermore, the positions and sizes of these sub-arrays can be specified by users. This feature allows image system to trace two fast moving objects without using two ROICs. An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 0.5/spl mu/m DPTM n-well CMOS process.

Design of CMOS high-speed self-regulating voltage-controlled oscillator (HSSR VCO) using negative skewed delay scheme is presented in this paper. With a SMIC standard logic 0.18-/spl mu/ 1.8V CMOS process, the simulation results show that the HSSR VCO can work at 2.2 GHz with good linearity in frequency-voltage space as over an acceptable tuning range as well as a built-in compensation for the delay variation caused by supply fluctuation.

This paper presents a precise compensated bandgap reference without resistors. This bandgap reference uses an improved voltage-transfer unit instead of resistors. A current proportional to T/sup /spl alpha// (/spl alpha/ is a constant) is produced to compensate for the higher order of the V/sub EB/. This bandgap reference is based on 0.5/spl mu/m n-well CMOS technology. The supply voltage is 5V, working from -10/spl deg/C to 90/spl deg/C, the effective temperature coefficient of the output voltage is only 7 ppm//spl deg/C, and the maximum power dissipation is 0.76mW.

A correlated double sample (CDS) stage design is proposed for CMOS image readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive switch capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports integration-while-read (IWR) mode, then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

Microprocessors are extremely versatile and complexity that present significantly test challenges. This paper describes a retargetable functional test platform system design for various microprocessors. Characterized by configurable test environment generator, retargetable assembler and strong ATPG the platform system could automatically produce different test environment and assemble out relative test codes to adapt to the microprocessor under test. Experiments show that the platform system works correctly, flexibly and efficiently.

A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 mW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 mW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 mm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.

An improved CMOS snapshot readout structure called RRSCA (Reset Row-by-row Snapshot Charge Amplifier) for infrared focal plane array (IRFPA) is presented in this paper. The pixel circuits in RRSCA readout structure are reset row by row after each row's pixel signals were readout to the column stage in parallel and pixel circuit is very simple including only three MOSFETs. Thus, the RRSCA readout structure is very suitable for the readout circuit design with large-format and very small pixel size such as 30*30 or 25*25 mm2. An experimental 130 t 130 RRSCA chip has been fabricated with 1.2-mm Double-Poly Double-Metal (DPDM) n-well CMOS technology. Both simulation results and experimental results are presented.

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.

A design of a 32-bit microprocessor core PKURS002 for embedded system is presented in this paper. It consumes much less power yet remains the high performance, compared with its prior PKURS001. The core employs low power design techniques at the controller, data path and internal memorial cells. The controller employs distributed logic instead of centralized one to reduce the signal transition by enlarging the self-loop. A new algorithm LSA (Logarithmic Skip Adder) has been provided to implement ALU and bit-split technique is applied to the structure of register file. The core is described by HDL and verified on 0.35 mm CMOS process. Result shows it reduce 30% power consumption compared with its predecessor at the same performance.

In our project of IP library creation, MAC is an important IP module. Here, a new approach is proposed for designing high performance single cycle MAC. We combine the full custom design, gate level VHDL design and standard cell based synthesis together to get good performance and technology portability. After the technology is decided, basic circuit modules are custom designed and accurate HSPICE simulation is performed to generate exact driven, delay and area information. It is added to the standard cell library. We need to write the gate level HDL of a MAC using optimized special circuits, and then apply logic synthesis. Then the structure and the interconnection of MAC have been decided by the gate level netlist, it can get the good performance of full custom design and have better portability. When being changed to a new technology, the designer only need to redesign the small circuits and simulate them, the gate level netlist need no change. We compared the traditional 3-2 full adder, the redesigned 4-2 compressor, and the 9-2 compressor in this paper. The result is almost the same with the references. This new approach has advantages in IP reuse, shortens the developing times and can get the high performance of full custom design.

This paper gives a delay model of the register files which are made of multi-port SRAM technology. Then we realized a 32wordt32 bit 2write/6read eight-Port register files. During the realization, according to the presenting delay model, we present a grouping wordline method to reduce the delay time of register files, also there are some structure modifying for the storage cells of register files. With the 2.5 v 0.25 mm CMOS technology, simulation results show that delay time of the register file is reduced by 11.5% than the register file which hasn't adopted novel method.

A multi-layer modeling approach is proposed in this paper for creating behavioral models of charge-pump phase-locked loops, which offers great flexibility of trading off between the simulation speed and accuracy. Also the approach allows time domain noise simulation with a specific layer. A multi-layer Verilog-A charge-pump PLL model is created to illustrate the proposed approach. A simulation speed up factor of 12 to 99 is achieved with reasonable loss of accuracy.

The digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs Manchester chain to fulfil the compare operation. Compared with the static implementations, MCP's highest operating frequency (125 MHz) is much higher. At the same operating frequency, MCP's power dissipation is 15%-22% lower than static version's. The layout area of MCP is only 87.6% of the static's and it is very convenient for implementing parallel or pipeline structure that is important for high performance VLSI design. By a series of optimizations the MCP gained a good noise immunity, though it is sensitive to noise glitches for its dynamic structure. MCP is a high quality function block and suitable for high performance VLSI design.

A new Quadru-Tree algorithm, by which the transition probabilities of circuit nodes, including all internal and output nodes, can be exactly worked out, and its program implementation are presented in this paper. As evidence of its accuracy and efficiency, the result of one example run in the prototype is reported, as well.

An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 /spl mu/m P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible.

An improved low power CMOS snapshot readout structure called OESCA (Odd-Even Snapshot Charge Amplifier) for focal plane array (FPA) is presented in this paper. Using two low power charge amplifiers as column readout circuit (one is for the odd-row readout and the other is for the even-row), this structure not only can eliminate the influence of column bus parasitic capacitance, but also can save 15% power dissipation of the column readout stage. The pixel circuit includes only three NMOSFETs. Thus, it is very suitable for large-format small-pixel lower-power readout circuit. An experimental 64/spl times/64 OESCA chip has been fabricated with 1.2-/spl mu/m Double-Poly Double-Metal (DPDM) n-well CMOS technology. The charge handling capacity is 10.37 pC with pixel size 50/spl times/50 /spl mu/m/sup 2/. A description of the readout circuit structure, pixel circuit, operation principle is given in detail. Both excellent simulation results and experimental results of the fabricated OESCA readout chip are presented.

With the rapid progress of information technology, security becomes one of the key factors in information storage, communication and processing. For the reason of speed and security, the requirement for VLSI chips or modules that support data encryption and decryption increases rapidly. The design and implementation of a data ciphering processor (DCP) chip adopting block cipher algorithm is demonstrated in this paper. The cipher algorithm is qualified for commercial use. The plaintext, ciphertext and key are all 64-bit long. A top-down design flow is used in the implementation. Several methods are employed to enhance the security of the chip. A standard-cell library is also developed in the design. All the design and implementation of this DCP are performed in China. A 0.9um double-layer-metal CMOS technology is adopted for manufacture. The chip achieves the required result in the first time implementation. The encryption/decryption processing speed reaches 40MBit/s.

This paper describes the optimized design of two kinds of operational amplifier (OPA) in the column readout circuit and output buffer of focal plane array (FPA) circuit, based on 1.2 /spl mu/m double poly double metal (DPDM) CMOS process. Hspice simulation shows that the OPA for column readout circuit works with GBW of 0.9 MHz, power of 35 /spl mu/W, settling time of 3 /spl mu/s. The OPA in output buffer can work at GBW of 12 MHz, power of 1.8 mW, settling time of 144 ns, which may support the dimension of FPA as large as 400*400 pixels at 30 frames/sec.

The threshold model is one of the models of BSIM3V3. The authors have investigated the parameter extraction of the threshold model. Both single-bin and multi-bin algorithms are implemented which avoid the parameter redundancy problem. Refined device schemes are designed to support the group extraction strategy. For the single-bin algorithm, the relative error of the extracted values of the parameters is less than 0.02%.

We develop a novel algorithm for parameter extraction of semiconductor devices. The S/sup 3/ algorithm, which is functional for NP-hard problems in discrete space, is applied to the parameter extraction of BSIM (Berkeley Short-channel IGFET Model). By using this algorithm, a relatively large number of model parameters can be optimized globally and extracted simultaneously. As to BSIM1, two distinct S/sup 3/ smoothing strategies, accompanied by the LS-NR method, are used to extract the parameters. In contrast to the results obtained by using the LS-NR method alone, those derived after the introduction of these strategies are improved greatly.

Thispaperdescribesan8-bit125MHzlow-powerCMOSfully-foldinganalog-to-digitalconverter(ADC). A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5 m CMOS technology and occupies a die area of 2 × 1.5 mm 2 . The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply. In this paper, a novel mixed-averaging distributed T/H circuit is proposed which improves the accuracy and provides a better tradeoff between accuracy, size and power dissipation. In addition, a novel bit synchronization architecture is pre- sented to reduce the number of comparators, and this architec- ture employs folding circuits to produce a bit synchronization signal. Therefore, folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchroniza- tion block. A special low-power CMOS ADC is designed and only 22 comparators are used in the whole ADC. The ADC is implemented in 0.5 m CMOS technology. Measured results show that the power dissipation of the ADC is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

With analyzing features of the accumulator in numerically controlled oscillator (NCO), it is pointed out that design based on pipeline for NCO is feasible. The schematic and results of logic simulation are given in this paper. The pipeline based NCO has evidently more advantages: higher speed (about twice) and fewer components (about 2/3) than usual. >