New efficient design of digital comparator

The digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs Manchester chain to fulfil the compare operation. Compared with the static implementations, MCP's highest operating frequency (125 MHz) is much higher. At the same operating frequency, MCP's power dissipation is 15%-22% lower than static version's. The layout area of MCP is only 87.6% of the static's and it is very convenient for implementing parallel or pipeline structure that is important for high performance VLSI design. By a series of optimizations the MCP gained a good noise immunity, though it is sensitive to noise glitches for its dynamic structure. MCP is a high quality function block and suitable for high performance VLSI design.