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Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS2. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performedex situand transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

The main requirement for using the Fluctuation Enhanced Sensing technique is the ability to perform low-frequency noise measurements. The portability of the measurement system is also a quite desirable feature not limited to this specific application. In this paper, an approach for the realization of a dual channel spectrum analyzer that is capable of exploring frequencies down to DC, although based on a USB sound card, is proposed. The lower frequency range of the input signals, which is outside the frequency range of the sound board, is upconverted to higher frequencies by means of a very simple modulation board. Then, the entire spectrum is reconstructed numerically by proper elaboration. With the exception of the modulation board, the approach we propose does not rely on any specific hardware. Thanks to the efficiency of the spectra estimation and reconstruction software, which is based on a public domain library, the system can be built on a low-cost computer single board computer, such as the Raspberry PI3. Moreover, when equipped with an optical TCP/IP link, it behaves as a compact spectrum analyzer that along with the device under test can be placed into a shielded environment, thus being isolated from external electromagnetic interferences.

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μFE> 1 cm2V−1s−1) and excellent stability under gate bias stress (bias stress Vds = 0V). However, after prolonged bias stress performed at high drain voltage, Vds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high Vds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.

Junctionless Transistors (JL) and One-Transistor (1T) DRAMs are concepts that come out in order to improve the scalability of logic and volatile memories, respectively. In some recent papers, Floating Body (FB) DRAMs (a class of 1T-DRAM) and JL transistors have been joined in order to propose a solution to overcome the scaling limit of the conventional 1T-1C DRAM cells. In this paper they are discussed in detail the physics of operation and the performances of FB-DRAM cells based on JL transistors including the effect of Trap-Assisted-Tunneling (TAT), neglected in most of previous works. As expected, TAT severely limits the retention time due to the large doping, in particular during HOLD operation. The discussion is supported by 2D device simulation on a double gate junctionless transistor including the effect of statistical variability induced by random dopant fluctuations, and the technology (bandgap, lifetime) scaling. It is found that the cell, at least at the nanoscale, can work only by independent gate operation, having maximum performance when the bottom gate works at the limit of the BBT bias region during READ, and that at a gate length as large as 100 nm and fin width of 10 nm the cell can sustain the high doping induced variability to a retention time in the order of 1 ms, while the use of materials with higher bandgap (~1.3 eV) than Silicon can improve the retention time to the order of 10 ms. However several concerns remain on their actual use related to the necessary bias level and to the impact of the actual technologies on the lifetime, which strongly affects TAT degradation.

DC coupled transimpedance amplifiers based on operational amplifiers are common in the field of noise measurements on electron devices. The current required to bias the device under test typically flows through a resistor whose noise adds to the background noise of the amplifier with a contribution inversely proportional to the resistance value. The supply voltage of the circuit (typically a few volts) sets a limit to the maximum resistance for a given bias current and, hence, a minimum to the background noise that can be reached. To address this issue we propose to employ integrated solar cells to make available in the circuit voltages in the tens of volts range from which bias currents can be sourced with larger resistances leading to lower background noise. We propose the design and preliminary testing of such a system that is intended for applications in which bias currents are in the tens of nA range.

One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and field enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude.

Knee injuries are among the most common health problems in the world. They not only affect people who practice sports, but also those who lead a rather sedentary life. Factors such as age, weight, working and leisure activities can affect the health of the knees, causing disorders such as inflammation, edema, deterioration of cartilage and osteoarthritis. Although for the diagnosis and treatment of the various pathologies it is always advisable to contact orthopedists and specialized structures, it would often be useful to monitor the state of health of the knees in order to evaluate the healing (or worsening) process and the effects of sport/motion activities or rehabilitation. In this perspective, a portable knee health monitoring system was developed to be used at home or in gyms and sports environments in general. Besides requiring a simple custom front end, the system relies on a PC audio board capable of a sampling rate of 192 kHz to perform bioimpedance measurements at frequencies in excess of 50 kHz. A simple numerical calibration procedure allows to obtain high accuracy while maintaining low hardware complexity. The software developed for the operation of the system is freely available to any researcher willing to experiment with the bioimpedance measurement approach we propose, ensuring the conditions of portability and low complexity. Primary (intracellular and extracellular resistances and cell membrane capacitance) and secondary (real and imaginary parts of the total impedance) bioimpedance parameters can be obtained and analyzed through direct measurements with reference to an equivalent circuit model. The functionality of the system has been tested on nine subjects with different well-known health conditions, providing encouraging results in terms of the ability to correlate bioimpedance measurements to the health status of the knees. If proper clinical trials were to confirm our preliminary results, a system such as the one we propose could be used for fast and frequent monitoring of knee joints, thus possibly reducing the frequency at which complex and expensive medical exams, sometimes involving long waiting lists, must be performed.

It is shown how some photovoltaic MOSFET drivers can be used for the realisation of a low noise, programmable voltage source, with a dynamic range that can easily exceed several tens of volts starting from standard ± 12 V power supplies. Such a source can be useful in the investigation of the electrical properties, and particularly noise properties, of organic thin film transistors on plastic substrates, since relatively large gate voltage sweeps are required in order to obtain a significant change in the conduction properties of the channel.

Focusing on the interplay between interface chemistry, electrochemistry, and integrated electronics, we show a novel low-cost and flexible biosensing platform for continuous glucose monitoring. The amperometric biosensing system features a planar three-electrode structure on a plastic substrate, and a wireless near-field communication-powered electronic system performing sensor analog front-end, A/D conversion, digital control, and display tasks. The working electrode is made of electropolymerized poly (3,4-ethylenedioxythiophene) film onto a polyethylene terephthalate/gold electrode followed by immobilization of cross-linked glucose oxidase by glutaraldehyde. The advantages offered by such a device, including low-cost materials and instrumentation as well as the good sensitivity of 9.24 $\mu \text{A}/({\mathrm {mM}} \cdot {\mathrm {cm}}^{2})$ are promising tools for point-of-care monitoring. It is demonstrated that the devices are good candidates for the development of advanced sensing approaches based on the investigation of the noise produced during operation (fluctuation-enhanced sensing).

We propose a simple topology for the realization of ultra low noise differential-input, differential-output preamplifiers. The input devices can be either low noise JFET pairs (for high impedance sources) or low noise BJT pairs (for minimum low frequency voltage noise). Besides the input devices, the circuit requires only two matched low noise BJT transistor pairs (either PNP or NPN, depending on the input device type) and a few excess noise free resistors for consistently obtaining differential gains of 100 (40 dB) with a bandwidth in excess of 100 kHz and an equivalent input noise floor comparable to (or better than) those reported in the literature for similar devices. The preamplifier is to be regarded as an off-the-shelf component that can be employed as a building block for a number of applications in the field of low frequency noise measurements.

When performing voltage noise measurements on a biased device, the DC component due to the bias must be rejected in order to avoid saturation of the high gain low noise input stage of the voltage amplifier employed to raise the level of the signal prior to sampling for spectral analysis. This is normally done by interposing an RC high pass filter between the device and the DC coupled amplifier input. The problem with this approach is that in order to reduce the noise contribution coming from the resistance R in the filter, its corner frequency must be chosen much smaller than the minimum frequency of interest, thus resulting in extremely long transients upon device connection or bias change. In order to address this problem we propose to employ a low noise, programmable floating voltage source that, together with a proper feedback loop, behaves as a noiseless AC coupling filter, thus allowing to considerably reduce the duration of the transients.

Impedance and low frequency noise measurements are valuable and complementary methods for electron device characterization. In this work we propose an integrated method for impedance and low frequency noise measurements in which impedance measurements are performed by means of crosscorrelation low frequency noise measurements. The method is implemented in a three-channel measurement system for the automatic DC, Gate-Drain low frequency noise, and impedance characterization of electron devices. Method and system operations are described and validated by means of measurements on known reference devices.

We report on experiments performed in order to verify the ability of low frequency noise measurements to serve as a sensitive tool for the characterization of the degradation of electron devices on flexible substrates as a consequence of mechanical stress. We designed and build a dedicated stress chamber for performing stress (repeated bending) in controlled environmental conditions. Test devices are copper resistance onto plastic substrates. We observe that, whenever the flicker noise produced by the resistances is clearly detectable, the level of flicker noise increases as the mechanical stress increases. In some cases noise increment of 100 % are observed when the change in the DC resistance of the sample is as low as 0.1%.

We present, for the first time, Low Frequency Noise measurements in Vertical Organic Transistors. Investigated devices are p-type Metal-Base Organic Transistors employing Pentacene and Copper Phthalocyanine as active layers for the Emitter and Collector regions, respectively. The power spectral densities measured at the Base and Collector terminals follow a 1/fγ law, with γ≈1, suggesting that noise is generated, in both cases, by a continuous distribution of traps. Cross-correlation measurements show that Base current noise and Collector current noise are uncorrelated meaning that the physical origin of the noise measured at the Base and Collector terminals is different.

A simple platform is proposed for the accurate characterization of Quartz Tuning Fork (QTF) based sensors. The system is based on a Personal Computer (PC) and takes advantage of the fact that the resonance frequency of standard wristwatch QTFs falls well within the acquisition bandwidth of modern soundcards. The choices in the design of the extremely simple measurement hardware result in the ability to accurately compensate for non-idealities without any need for compensation hardware. Experimental test results are presented that demonstrate the effectiveness of the approach we propose.

Vertical organic transistors are a promising candidate to overcome the scaling limits of conventional horizontal organic field-effect devices. In this paper, based on the results of direct current (dc) and low-frequency noise (LFN) measurements, we propose a picture for the carrier transport in metal-base organic transistors in which transmission across the base is due to the combined action of both hot-carriers (HCs) and high-conduction paths (pores) in the metal base. Investigated devices employ pentacene and copper phthalocyanine as active layers for the emitter and collector regions, and a bilayer consisting of Au/MoO3 as injecting electrode. The dc analysis highlights that the charge transport in the investigated devices is due to drift diffusion of the emitter-injected carriers in the highest occupied molecular orbital (HOMO) band and is dominated by HC injection, although conduction via pores increases and becomes not negligible at high base–emitter fields. The LFN analysis highlights the presence of two dominant and uncorrelated 1/f current noise sources, one located between base and emitter, due to the fluctuations of the not-transmitted HC current, and a second source located between collector and emitter, due to the fluctuations of the transmitted HC current and/or to the fluctuations of the current through the pores in the metallic base.

We propose a simple but effective approach for the estimation of power spectra at very low frequencies (down to the tens of mHz range) by exploiting the characteristics of the sound system (sound card) and the computational power of modern personal computers. A simple mixer board has been designed that allows to transfer the low frequency region of the spectrum at a higher frequency in the passband of the personal computer sound card. Proper digital signal elaboration allows to recover the entire spectrum (from very low frequencies up to the sound board passband). Results obtained by the proposed approach on test spectra are compared to the results obtained by laboratory grade dynamic signal analyzer boards. The approach we propose is mostly useful for applications in the field of low frequency noise measurements, where the ability to explore frequencies well below 1 Hz is more important than obtaining large bandwidths.

We propose an elaboration and visualization approach for spectral measurement that allows to monitor the progress of the estimation process in real time while maintaining a quaqi-constant resolution bandwidth over frequency ratio in a wide frequency range. The approach we propose is particularly useful in the estimation of low frequency noise, where the flicker component is dominant, since it allows to immediately recognize the presence of systematic errors due to insufficiently small resolution bandwidth and to optimize the measurement time based on the detailed shape of the spectrum as it unveils during the estimation process.

SUMMARY Equivalent input current noise and bandwidth are the most relevant parameters qualifying a low-noise transimpedance amplifier. In the conventional topology consisting of an operational amplifier in a shunt-shunt configuration, the equivalent input noise decreases as the feedback resistor (RF), which also sets the gain, increases. Unfortunately, as RF increases above a few MΩ, as it is required for obtaining high sensitivity, the bandwidth of the system is set by the parasitic capacitance of RF and reduces as RF increases. In this paper, we propose a new topology that allows overcoming this limitation by employing a large-bandwidth voltage amplifier together with a proper modified feedback network for compensating the effect of the parasitic capacitance of the feedback resistance. We experimentally demonstrate, on a prototype circuit, that the proposed approach allows to obtain a bandwidth in excess of 100 kHz and an equivalent input noise of about 4 fA/, corresponding to the current noise of the 1 GΩ resistor that is part of the feedback network. The new approach allows obtaining larger bandwidth with respect to those obtained in previously proposed configurations with comparable background noise. Copyright © 2014 John Wiley & Sons, Ltd.

Floating Body one transistor Dynamic Random Access Memories (FBRAMs) have been widely studied and proposed in the literature as an alternative for conventional one transistor/one capacitor DRAMs. FBRAM performance depends on charge degradation during READ and HOLD operations and on the body effect during READ operation, the first setting the amount of the residual non-equilibrium charge during READ operation, and the second setting the effectiveness of this residual charge to modulate the source-body barrier during READ operation. In this work it is proposed a simple analytical charge-based compact model for the body-effect in FBRAMs which is able to reproduce device performance in terms of READ Sense Margin and current ratio. Physical insights of the body effect and charge degradation mechanisms, with particular emphasis to their bias dependence, are discussed in detail. Conclusions can be useful for the choice and the optimization of the bias in FBRAMs. All the discussion is supported by two-dimensional drift–diffusion device simulation on a template double-gate MOSFET.

A public domain software library is introduced and discussed that aims at enabling the development of customized real-time spectral analysis applications in the field of Low-Frequency Noise Measurements. Besides allowing spectral and cross-spectral estimation on multiple channels, the library effortlessly enables the implementation of quasi-logarithmic frequency resolution for real-time spectral analysis over several decades of frequency. By exploiting the library, the burden of the selection of the proper spectral estimation parameters in any given application is virtually eliminated.

In this paper, we discuss a few techniques that allow an effective reduction of the background noise and/or the reduction of the measurement time when performing voltage noise measurements by employing a number of nominally identical voltage amplifiers with negligible equivalent input current noise. It is demonstrated in particular that, if $N\ (N > 2)$ voltage amplifiers are connected to the device under test and if the properties of cross-correlation among all $N$ acquisition channels connected to the output of each amplifier are exploited, the time required for obtaining a given accuracy is reduced by a factor $N(N - 1)/2$ with respect to the conventional setup for cross-correlation that employs only two channels. From another point of view, the effective background noise is reduced for constant measurement time. Such a factor can be further increased if amplifier paralleling is also employed for reducing the equivalent input voltage noise for each channel. Measurements on two different setups employing up to four channels and up to eight channels are presented that confirm the expected reduction factors in measurement times.

Low-frequency noise (LFN) has been used in order to gain insight into the physical properties of the materials involved in organic thin-film transistors (OTFTs) fabrication, often with contradictory results. Besides the physical origin of noise, contact effects on noise have been a source of concern and discussion. In this paper, we report on accurate LFN measurements in p-type staggered top-gate OTFTs over four decades of channel current, from the subthreshold to the strong accumulation region. The measured spectra follow a clear 1/ $f$ behavior attributed to the trapping/detrapping of channel charge carriers into interface and oxide defects, while the influence of noise sources at contacts is found to be negligible. However, contacts affect the measured noise by a nonnegligible differential resistance. Noise data are interpreted in the context of a multitrap correlated mobility fluctuations (CMFs) model, showing that noise is dominated by acceptor-like traps. Despite the low mobility ( $\mu _{{\mathrm{eff}}}\sim $ 2 cm2/V/s), the large scattering parameter ( $\alpha \sim 10 ^{7}$ Vs/C) produces an increase of the noise at the higher currents due to CMFs. The product $\alpha \mu _{{\mathrm{eff}}} \approx 2\cdot 10^{7}$ cm2/C, which measures the strength of CMFs, is similar to what was reported for a-Si:H and much higher with respect to crystalline silicon MOSFETs revealing a strong correlation between CMFs and the state of disorder of the active layer.

Investigation of gate dielectric conduction properties in organic p-type staggered thin-film transistors is reported by means of direct-current, capacitance–voltage, and noise measurements. Results suggest that transport in the CYTOP™ gate dielectric is dominated, at low currents, by Schottky conduction due to the emission at the aluminum gate interface through a barrier $\phi _{B} \approx 1$ eV, while is limited, at higher currents, by space-charge conduction in the trap-limited regime with an effective mobility $\mu \theta $ estimated in the order of $10^{-9}$ cm2/(Vs). Gate current noise follows a 1/ $f$ law and it is found to be proportional to $I_{G}^{2}$ , which is inconsistent with the commonly assumed mobility fluctuation. Traps responsible for gate noise are dielectric-bulk traps, not located at the semiconductor interface, since the gate noise is found to be uncorrelated with drain noise.

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.

Strontium titanate (STO) has been proposed as dielectric material in metal-insulator-metal (MIM) capacitors for future DRAM generations due to its higher dielectric constant and corresponding lower equivalent oxide thickness. In this letter, we show for the first time the impact of electrode composition and processing on the low-frequency noise (LFN), hence on the device material defectiveness, in large area (1000 μm × 1000 μm) MIM capacitors with STO dielectric (EOT is ~0.4nm, physical thickness is ~8.5nm) and Ru/TiN or TiN as metal electrodes. LFN measurements show that the power spectral density (S IG ) associated with gate current (I G ) fluctuations follows a 1/f shape and that SIG αI α G with α measured between 1.6 and 1.9. In particular, it is shown that PVD processing for top electrode Ru in place of chemical vapor deposition processing results in a significant (more than three decades) noise reduction (lower trap density) according to the observed lower gate leakage (

In this paper, we study the operation mode and the scalability of the second generation (type II) of double-gate capacitorless one transistor dynamic random access memory (1T-DRAM) cells. We find that the memory operates by accumulating charge at the gate interfaces, not in the body of the cell. The type-II configuration allows an infinitely long retention of state “1,” whereas the total retention time is limited by the leakage associated with state “0” due to band-to-band tunneling (BTBT) at the source/drain to bulk junctions. Extensive and careful scaling analysis shows that longitudinal scaling is limited by short-channel effects related to source/drain to bulk barrier lowering, whereas transverse scaling is limited by BTBT. We conclude that type-II 1T-DRAM is somewhat more scalable than type-I 1T-DRAM (i.e., 15 nm versus 25 nm). The better scaling perspective of type-II 1T-DRAM cells is ascribed to the higher READ sensitivity, programming window, and retention time.

In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.