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We investigate heavy ion irradiation effects on large area capacitors with an Oxide-Nitride-Oxide (ONO) stack as dielectric. Despite the thickness of this stack (16.5 nm), we observe the onset of a leakage current after irradiation. We demonstrate that this leakage current is a truly DC current that flows through the ONO stack and decreases with time. Electrical stresses demonstrate that irradiation does not reduce the time-to-breakdown of these devices. Noticeably, capacitors with a 9-nm Si[O.sub.2] layer as dielectric and irradiated with the same ion specie and with the same fluence do not show any measurable leakage current. Index Terms--Flash memories, floating gate memories, heavy-ion, nitride, ONO, radiation effects, radiation induced leakage current.

We studied the response of a commercial 0.13-[micro]m CMOS technology to high-energy (24-GeV) proton irradiation, which emulated the environment the front-end electronics of future high-energy accelerators will have to operate in, for fluences up to [10.sup.16] p/[cm.sup.2]. After irradiation, large negative shifts in the threshold voltage and large drops in the maximum transconductance were observed in PMOSFETs, whereas comparatively smaller effects were present in NMOSFETs. Furthermore, both kinds of devices exhibited an increase in the drain off-current and in the gate leakage current. All the observed effects were roughly proportional to the proton fluence. For the PMOSFETs only, the amount of the degradation depended on the device channel length. The changes in the characteristics of the irradiated devices were attributed to the build-up of positive charge in the LDD spacer oxide and to the creation of defects in the gate oxide. Index Terms--CMOS, high-energy physics experiments, ultra-thin gate oxides.

In this work, we have focused our attention on MOSFETs, which are the real basic elements of all CMOS applications. We have studied the immediate and latent effects produced by heavy ion irradiation on MOSFETs with ultrathin gate oxide, even after electrical stresses subsequent to irradiation. We found that a single ion can generate a physically damaged region (PDR) localized in the Si-Si[O.sub.2] interface, which may hamper the surface channel formation. In order to generate a PDR the ion hit must be close enough to MOSFET borders, i.e., in correspondence with the STI or the LDD spacer. Consequently, if both MOSFET W and L are large enough only few ion hits may give place to a PDR, mitigating the radiation damage. Finally we have developed an original model to describe the impact of the PDR on channel conductance in the ohmic linear region. On the basis of this model, we predicte a PDR size around 0.2-1 [micro]m.

In this work, we present an original model to explain the accelerated wear-out behavior of irradiated ultra-thin oxides. The model uses a statistical approach to the breakdown occurrences based on a nonhomogeneous Poisson process. By means of our model, we can estimate the number and the time evolution of those damaged regions produced by ion hits that generate breakdown spots during high field stresses after irradiation, including the dependence on the oxide field. Also, by using the proposed model, we have studied the wear-out dependence on the stress voltage, gate area, and ion fluence. In particular, by studying the stress voltage dependence of wear-out acceleration, it is feasible to extrapolate the device lifetime even at low operating voltage. Index Terms--Accelerated breakdown, CMOS devices reliability, nonhomogeneous Poisson process, radiation stresses, thin oxide reliability.

We have investigated how ultra-thin gate oxides subjected to heavy ion irradiation react to a subsequent electrical stress performed at low voltages. Even in devices exhibiting small (or even no) increase of the gate current after irradiation, the time-to-breakdown is substantially reduced in comparison with unirradiated samples due to the onset of a soft or hard breakdown, in contrast with previous results found on thicker oxides. In fact, we have demonstrated that the radiation damage acts as a seed for further oxide degradation by electrical stress during the device operating life. The accelerated oxide wear-out depends on the linear energy transfer (LET) coefficient of radiation source. Index Terms--Accelerated breakdown, CMOS devices reliability, radiation stresses, thin oxide reliability.

We have investigated new aspects of the gate leakage current due to radiation-induced soft breakdown (RSB) of thin oxides subjected to heavy-ion irradiation. Temperature and noise characteristics of RSB on MOS capacitors with 3- and 4- nm MOS oxides have been experimentally investigated. We have developed an empirical law to describe quantitatively the temperature dependence of the RSB current. A small activation energy has been found by using an Arrhenius relation, in agreement with the RSB tunneling conduction mechanism. The RSB variation at high temperature has been only estimated, as measurements of RSB oxides easily produced catastrophic breakdown. We have studied the RSB noise and identified different contributions to the characteristic random telegraph noise, correlated with the trapping and conduction characteristics of the RSB spots. An original model has been developed that successfully describes the different probability distributions of the current fluctuations that cannot be simulated by using previous models, such as those based on L6vy or Gaussian distributions. Finally, a correlation was established between the shape of the fluctuation distribution and the degradation level of the oxide. Index Terms--Noise in MOS devices, oxide reliability, radiation soft breakdown, radiation stresses.

An investigation of the quantum yield (QY) experiment reveals that stress-induced leakage current (SILC) and QY are caused by different defects in the oxide. It is concluded that it is not correct to interpret reduction in QY after stress as a measure of energy loss of SILC electrons.

A model for the analytical expression of the tunneling current over a thin oxide layer for a MOS capacitor has been developed.

A stress induced leakage current model in MOS capacitors with thin oxide layers was developed.

This paper focuses on the impact of annealing on the current conduction and trap states of metal-insulator-metal capacitors with CeO2/La2O3 dielectrics. Capacitance-frequency measurements identify two main trap levels (T1 and T2), characterized by an activation energy of 0.2 and 0.3 eV, respectively, and by a time constant of 1 ms and 20 μs at room temperature. The current conduction is found to be ruled by a Poole-Frenkel effect and space charge limited current under positive and negative bias, respectively. Selective annealing of CeO2 and La2O3 layers clarifies the nature of the aforementioned traps. Although providing no change in the activation energy, an additional annealing of the CeO2 and La2O3 layer is found to significantly change the trap amplitude of T1 and T2, respectively. The corresponding change of the current conduction in the region where trap assisted mechanisms play a major role is discussed. [ABSTRACT FROM AUTHOR]

Efforts to extract MOS parameters are reported using a new model of gate capacitance.

The breakdown of thin and ultrathin silicon dioxide films has been studied by developing a unified model. It is based on the ability of trapped charges to increase the effective local permittivity of silicon dioxide by increasing the polarization. Results indicate that breakdown is associated with the presence of a fixed amount of trapped charges inside the oxide. There is also good agreement between the experimental and theoretical data.

The goal of this work is to study the transient electrical features of metal/high-k interface in MOS stacks. To this aim, electrons are injected from the gate of TaN/Al2O3/SiO2/p-Si capacitors in pulsed regime. The displacement current flowing during the pulse front is detected, and the capacitance is extracted. As a result, for the first time, a flat-band instability related to electron trapping in states near the metal/high-k interface is measured on a millisecond timescale. A picture of the time evolution of the charge density inside the oxide bulk is drawn, with the aid of a finite-element simulator. Reliability of the metal/high-k interface is also investigated by performing stress experiments in pulsed conditions. It is shown that after a certain number of pulses, the creation of new traps at the top interface of the MOS stack becomes relevant. [ABSTRACT FROM AUTHOR]

We study heavy ion irradiation effects on capacitors with the structure of a Floating Gate Flash cell. We demonstrate that the modifications of the capacitors electrical characteristics observed after irradiation depend on the physical position of the defects produced by ions into the dielectric. In particular, we focus our attention on the leakage current produced by ion irradiation. We demonstrate that SiO2 capacitors feature a leakage current higher than that observed in capacitors with an Oxide-NitrideOxide (ONO) stack as dielectric. Finally, we investigate the behavior in time of the leakage produced by ions. [ABSTRACT FROM AUTHOR]

We studied the response of a commercial 0.13-μm CMOS technology to high-energy (24-GeV) proton irradiation, which emulated the environment the front-end electronics of future high-energy accelerators will have to operate in, for fluences up to 1016 p/cm². After irradiation, large negative shifts in the threshold voltage and large drops in the maximum transconductance were observed in PMOSFETs, whereas comparatively smaller effects were present in NMOSFETs. Furthermore, both kinds of devices exhibited an increase in the drain off-current and in the gate leakage current. All the observed effects were roughly proportional to the proton fluence. For the PMOSFETs only, the amount of the degradation depended on the device channel length. The changes in the characteristics of the irradiated devices were attributed to the build-up of positive charge in the LDD spacer oxide and to the creation of defects in the gate oxide. [ABSTRACT FROM AUTHOR]

We propose in this letter a simple technique based on C-V measurements which allows the estimating of the thicknesses of SiOx and high-k layers of interpoly dielectric (IPD) stacks. We apply this technique to IPD Al2O3-based stacks for floating-gate memory applications, finding a good agreement with TEM measurements. In addition, simulation results are provided to demonstrate the correctness of the basic assumption of this technique. [ABSTRACT FROM AUTHOR]

Stress-induced leakage current (SILC) modeling requires consistency with a variety of experimental observations, like steady-state leakage, transient discharge currents and impact ionization characteristics observed after stress. Here we present a SILC model based on trap-assisted tunneling and recombination at deep-levels in the oxide, which successfully reproduces all SILC features. Based on a detailed analysis of SILC data, a two-band defect distribution is determined, in which the low- and high-energy ranges account for stationary SILC and transient currents, respectively. The stress-induced impact ionization (SIII) components associated with these defect distributions are then calculated, showing that the main contribution results from high-energy states. Simulation results are in good agreement with experimental data for leakage and SIII currents in p-channel devices with an oxide thickness of 8.2 nm. These results point out the limitation of the quantum yield method for measuring the mean energy loss in the SILC mechanism. [Copyright &y& Elsevier]