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12. SOI MOSFETs

Author

Balestra, Francis, Ghibaudo, Gérard, Balestra, Francis, editor, and Ghibaudo, Gérard, editor

Published
2001
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17. Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances

Author

Ben Akkez, Imed, Fenouillet-Beranger, Claire, Cros, Antoine, Perreau, Pierre, Haendler, Sébatien, Weber, Olivier, Andrieu, François, Pellissier-Tanon, D., Abbate, F., Richard, C., Beneyton, R., Gouraud, P., Margain, A., Borowiak, C., Gourvest, E., Bourdelle, K.K., Nguyen, B.Y., Poiroux, T., Skotnicki, Thomas, Faynot, Olivier, Balestra, Francis, Ghibaudo, Gérard, and Boeuf, Fréderic

Published
2013
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24. Advanced Materials and Nanodevices for Brain-InspiredComputing

Author

Balestra, Francis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and balestra, francis

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2020

25. Challenges and possible solutions for the end of the Nanoelectronic Roadmap

Author

Balestra, Francis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and balestra, francis

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2020

26. Comparative experimental study of junctionless and inversion mode nanowire transistors for analog applications

Author

Bosch, Daphnée, Colinge, J.P., Lugo, J., Tataridou, A., Theodorou, Christoforos, Garros, Xavier, Barraud, Sylvain, Lacord, Joris, Sklenard, Benoit, Cassé, Mikaël, Brunet, L., Batude, Perrine, Fenouillet-Beranger, Claire, Lattard, D., Cluzel, J., Allain, F., Nait Youcef, R., Hartmann, J.M., Vizioz, C., Audoit, G., Balestra, Francis, Andrieux, François, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Democritus University of Thrace (DUTH), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire des champs magnétiques intenses (LCMI-GHMFL), Centre National de la Recherche Scientifique (CNRS), Département Nanotec (D2NT), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), and balestra, francis

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; We fabricated junctionless and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junctionless transistors for analog applications: AVT=1.4mV.µm matching, Av0=62dB gain (L=200nm), fT=126GHz cutoff frequency and fMAX=182GHz maximum operating frequency (L=35nm). Junctionless transistor performances even exceed those of inversion-mode ones in terms of back-bias capability, low-frequency noise, hot-carrier degradation and fMAX. This is explained by junctionless physics: channel length modulation, bulk conduction and high channel-depth sensitivity to back bias.

Published
2020

28. Executive Summary

Author

Wilson, Linda, primary, Ishiuchi, Hidemi, additional, Gargini, Paolo, additional, Allan, Alan, additional, Balestra, Francis, additional, Hayashi, Yoshihiro, additional, and Kenny, Leo, additional

Published
2021
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33. Modelling of self-heating effect in FDSOI and bulk MOSFETs operated in deep cryogenic conditions

Author

Ghibaudo, Gérard, Cassé, M., Maria, F. Serra Di Santa, Theodorou, C., Balestra, Francis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
Materials Chemistry, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, Condensed Matter Physics, ComputingMilieux_MISCELLANEOUS, Electronic, Optical and Magnetic Materials
Abstract

International audience

Published
2022
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34. A novel FDSOI transistor-based uncooled microbolometer sensor for disruptive IRFPAs

Author

Leduc, Patrick, Aliane, A., Balestra, Francis, albouy, antoine, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), and balestra, francis

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Uncooled bolometer detecting in the long wave infrared (LWIR) is a key technology for a fast growing market supported by innovations in defense and security, automotive industry and Internet of Things (IoT). Thermistor materials-whose resistance changes with temperature-like amorphous silicon (a-Si) or Vanadium Oxide (VOx) are commonly used as thermal sensitive element of uncooled bolometers. They are nevertheless not well suited for an ultimate cost reduction, as their fabrication requires a dedicated manufacturing line. One way to reduce the cost of production of this class of detectors is to aim at a bolometer integration scheme fully compatible with microelectronics industry. In this context, we propose a novel approach based on FDSOI (Fully Depleted Silicon-On-Insulator) MOS transistors as thermal sensitive element. Unlike thermistor technology, FDSOI transistors are realized on a standard CMOS line for high-throughput and low-cost manufacturing. Their performance as thermal sensors in subthreshold operation are besides higher than thermistors materials, with TCC (Temperature Coefficient of Current) in the range of 5.5-6 %/K against 2-2.5 %/K for the TCR (Temperature Coefficient of Resistance) of thermistor materials. From a technological point of view, the FPA final structure might be obtained by bonding these transistors from a first silicon wafer onto a second ROIC (Read Out Integrated Circuit) wafer thanks to a classical 3D integration process known as hybrid bonding (copper-copper and dielectric-dielectric direct bonding). This work consists in a first insight in the feasibility of the technology. It presents results obtained on FDSOI transistors that have been bonded on a second silicon wafer, thanks to a classical operation of SiO 2-SiO 2 molecular bonding. The substrate of origin (sensor wafer) of these transistors has been etched away, and a second control gate has been formed on the backside of the transistors. Measurements comparing bonded and unbonded transistors are presented. Electrical parameters like I(V), low frequency noise and TCC (Temperature Coefficient of Current) measurements are discussed to compare transistors before and after bonding. Extraction of interface trap density has also been carried out in order to assess the impact of post-bonding technological steps on the interfaces of the FDSOI transistor. Results demonstrate that electrical performances are the same between transistors measured before and after bonding, including a same level of low frequency noise and a same TCC. Interface trap density extraction shows that interfaces before and after bonding are of the same quality. 2

Published
2020

35. Status and trends in nanoscale CMOS and Beyond-CMOS

Author

Balestra, Francis, balestra, francis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2020

39. Charge Carrier Mobility: Precise Extraction of Charge Carrier Mobility for Organic Transistors (Adv. Funct. Mater. 20/2020)

Author

Xu, Yong, primary, Li, Yun, additional, Li, Songlin, additional, Balestra, Francis, additional, Ghibaudo, Gerard, additional, Li, Wenwu, additional, Lin, Yen‐Fu, additional, Sun, Huabin, additional, Wan, Jing, additional, Wang, Xinran, additional, Guo, Yufeng, additional, Shi, Yi, additional, and Noh, Yong‐Young, additional

Published
2020
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41. On the modelling of temperature dependence of subthreshold swing in MOSFETs down to cryogenic temperature

Author

Balestra, Francis, Ghibaudo, Gérard, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])

Subjects
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2020

42. Hot-carrier effects and reliable lifetime prediction in deep submicron N-and P-channel SOI MOSFET's

Author

Renn, Shing-Hwa, Pelloie, Jean-Luc, and Balestra, Francis

Subjects
Metal oxide semiconductor field effect transistors -- Research, Business, Electronics, Electronics and electrical industries
Abstract

A detailed analysis of hot-carrier effects in deep submicron N and P channel SOI MOSFETs is presented, for gate lengths down to 0.1 mum. The two-stage time dependence of degradation is also investigated to provide reliable lifetime prediction methods that can be used under various hot-carrier stress conditions. Saturation levels are reliant on gate length, thus degradation time dependence needs to be carefully determined.

Published
1998

43. A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFET's

Author

Renn, Shing-Hwa, Raynaud, Christine, Pelloie, Jean-Luc, and Balestra, Francis

Subjects
Silicon-on-isolator -- Research, Metal oxide semiconductor field effect transistors -- Observations, Business, Electronics, Electronics and electrical industries
Abstract

Hot carrier induced degradation is more complex in SOI devices than in bulk devices due to the thin Si-film effects. The reliability of SOI technologies are assessed, focusing on the hot-carrier effects (HCE) in deep submicron SIMOX and Unibond MOSFETs, hot carrier immunity of PD devices and analysis of the degradation N and P channel transistors. An investigation of the aging/recovery mechanisms for P-channel MOSFETs is also made.

Published
1998

44. Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs

Author

Renn, Shing-Hwa, Rauly, Emmanuel, Pelloie, Jean-Luc, and Balestra, Francis

Subjects
Silicon-on-isolator -- Analysis, Metal oxide semiconductor field effect transistors -- Analysis, Bipolar transistors -- Analysis, Business, Electronics, Electronics and electrical industries
Abstract

Research was conducted to examine hot-carrier effects resulting from parasitic bipolar transistor action in deep submicron N-channel silicon-on-insulator metal oxide semiconductor field effect transistors for a range of temperature and gate length. Device aging was heavily influenced by variations in the leakage currents. Moreover, variations of threshold voltage shifts for a stress in off-state showed unusual behaviors.

Published
1998

46. Roadmapping of Nanoelectronics for the New Electronics Industry.

Author

Gargini, Paolo, Balestra, Francis, and Hayashi, Yoshihiro

Subjects
INDUSTRIAL electronics, ELECTRONIC industries, NANOELECTRONICS, COMPUTER industry, SYSTEM integration, SERVER farms (Computer network management)
Abstract

This paper is dedicated to a review of the international effort to map the future of nanoelectronics from materials to systems for the new electronics industry. The following sections are highlighted: the Roadmap structure with the international teams, the methodology and historical evolution, the various eras of scaling, the new ecosystems and computer industry, the evolving supply chain, the development of SoC and SiP, the advent of the Internet of Everything and the 5G communications, the dramatic increase of data centers, the power challenge, the technology fusion, heterogeneous and system integration, the emerging technologies, devices and computing architectures, and the main challenges for future applications. [ABSTRACT FROM AUTHOR]

Published
2022
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47. Low-frequency noise sources in polysilicon emitter BJT's: influence of hot-electron-induced degradation and post-stress recovery

Author

Mounib, Ahmed, Balestra, Francis, Mathieu, Nathalie, Brini, Jean, Ghibaudo, Gerard, Chovet, Alain, Chantre, A., and Nouailhat, A.

Subjects
Junction transistors -- Research, Noise generators (Electronics) -- Research, Polysilicon -- Usage, Annealing -- Influence, Business, Electronics, Electronics and electrical industries
Abstract

The major advantages of the bipolar junction transistors (BJT's) are associated with its high speed functions and low noise characteristics. Research is conducted to study the noise characteristics of polysilicon bipolar transistor. Effects of varied chemical treatments and annealing temperatures on the noise magnitude of the BJT's, before and after polysilicon deposition are discussed.

Published
1995

48. Generalized mobility law for drain current modeling in Si MOS transistors from liquid helium to room temperatures

Author

Emrani, Ayoub, Balestra, Francis, and Ghibaudo, Gerard

Subjects
Metal oxide semiconductor field effect transistors -- Research, Electron mobility -- Research, Low temperature engineering -- Research, Business, Electronics, Electronics and electrical industries
Abstract

A proposed generalized mobility law for drain current modeling in silicon metal oxide semiconductor transistors from room to liquid helium temperatures is presented. Results show that, for each temperature, there is a corresponding unique value of n which is highly accurate. The value also varies on a quasi-linear basis in intermediate temperature ranges, given the device technology used.

Published
1993

50. Challenges for high performance and very low power operation at the end of the Nanoelectronics Roadmap

Author

Balestra, Francis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and Ducroquet, Frédérique

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Hardware_LOGICDESIGN
Abstract

International audience; Future Nanoelectronic devices faces substantial challenges, in particular increased power consumption, saturation of performance, large variability and reliability limitation. In this respect, novel materials and innovative device architectures will be needed for Nanoscale FETs.

Published
2019

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