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This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K in short-channel devices are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage. [ABSTRACT FROM PUBLISHER]

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual- k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual- k spacer (dual- kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual- kS JLT shows improvement in intrinsic voltage gain ( $$A_{V0}$$ ) by $$\sim $$ 44.58 %, unity-gain cutoff frequency ( $$f_\mathrm{T}$$ ) by $$\sim $$ 7.67 %, and maximum oscillation frequency ( $$f_\mathrm{MAX}$$ ) by $$\sim $$ 6.4 % at drain current $$(I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}$$ compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual- kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance ( $$g_\mathrm{m}$$ ). Furthermore, the dual- kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects. [ABSTRACT FROM AUTHOR]

This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4 GHz) and temperature (up to 225 °C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed. [ABSTRACT FROM AUTHOR]

Abstract: In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects. [Copyright &y& Elsevier]

Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance. [ABSTRACT FROM AUTHOR]

Abstract: This paper investigates both electrostatic control improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing top- and back-gate (substrate or ground plane) as V bg = k · V g) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. Improved performance (in terms of transconductance, drive current and early voltage) in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. QDG mode is demonstrated to allow threshold voltage tuning, subthreshold swing reduction and on-current enhancement without off-state current degradation, thus of interest for digital applications. The unique feature of QDG mode is finally exploited to boost the performances of the sleep transistor in the practical use case of a power-gated processor. About 30% reduction of the leakage in stand-by mode is achieved at nominal V g with a V bg of 3V, which can be generated at marginal area/power overheads with an on-chip charge pump with an architecture proposed in this paper. [Copyright &y& Elsevier]

Abstract: In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I D =5μA/μm and V DS=0.5V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V DD=0.5V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ∼20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V DD=0.5V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ∼10%, ∼35% and ∼25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits. [Copyright &y& Elsevier]

Abstract: In this paper, we analyze, for the first time to our best knowledge, the perspectives of ultra-thin body and ultra-thin BOX (UTBB) SOI CMOS technology for analog applications. We show that UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150–220GHz. Effect of operation regime, substrate bias, channel width and high temperature (up to 250°C) on analog figures-of-merit (FoM) are analyzed. Benchmarking of UTBB with other technologies (as planar FD SOI, different FinFETs, UTB with thick BOX) is presented. [Copyright &y& Elsevier]

Abstract: This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, Gm max, and analog figures of merit, such as transconductance over drain current ratio, Gm /ID , output conductance, GD , Early voltage, V EA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher Gm max. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model. [Copyright &y& Elsevier]