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In this work, quantitative information for nonuniform hot-carrier degradation, especially under mild stressing condition, is investigated. A test structure capable of revealing hot-carrier degradations of polycrystalline silicon (poly-Si) thin-film transistors in specific portions of the channel is employed. Effective density-of-states (DOS) distributions at the damaged sites can be extracted using field-effect conductance method, thus providing an effective tool to evaluate the impact of hot-carrier degradations. By measuring along individual sections of the channel, it becomes possible to extract the DOS for the device as a whole. The combination of the proposed test structure and DOS extraction technique also provides a powerful tool for modeling and simulating current-voltage characteristics of thin-film transistors under hot-carrier stressing. [ABSTRACT FROM AUTHOR]

A test structure was proposed to investigate the spatial and temporal evolution of hot-carrier degradation in n-channel poly-Si thin-film transistors. Our experimental results clearly show that the initial damage during the early stage of hot-carrier stressing, which is still undetectable by conventional test structures, can be easily observed by the structure. In addition, the proposed test structure is also capable of resolving the evolution of the degradation along the channel, thus providing a powerful tool to study the location-dependent damage mechanisms. [ABSTRACT FROM AUTHOR]

We reported exciton binding-energy determination using tunneling-current spectroscopy of Germanium (Ge) quantum dot (QD) single-hole transistors (SHTs) operating in the few-hole regime, under 405–1550 nm wavelength (λ) illumination. When the photon energy is smaller than the bandgap energy (1.46 eV) of a 20 nm Ge QD (for instance, λ = 1310 nm and 1550 nm illuminations), there is no change in the peak voltages of tunneling current spectroscopy even when the irradiation power density reaches as high as 10 µW/µm2. In contrast, a considerable shift in the first hole-tunneling current peak towards positive VG is induced (ΔVG ≈ 0.08 V at 0.33 nW/µm2 and 0.15 V at 1.4 nW/µm2) and even additional photocurrent peaks are created at higher positive VG values (ΔVG ≈ 0.2 V at 10 nW/µm2 irradiation) by illumination at λ = 850 nm (where the photon energy matches the bandgap energy of the 20 nm Ge QD). These experimental observations were further strengthened when Ge-QD SHTs were illuminated by λ = 405 nm lasers at much lower optical-power conditions. The newly-photogenerated current peaks are attributed to the contribution of exciton, biexciton, and positive trion complexes. Furthermore, the exciton binding energy can be determined by analyzing the tunneling current spectra. [ABSTRACT FROM AUTHOR]

We report the demonstration of high-photoresponsivity Ge-dot photoMOSFETs in a standard MOS configuration for the detection of 850-1550 nm illumination. Each device has a self-organized, gate-stacking heterostructure of SiO2/Ge-dot/SiO2/SiGe-channel which is simultaneously fabricated in a single oxidation step. Superior control of the geometrical size and chemical composition for our Ge nanodots/SiO2/Si1-xGex-shell MOS structure enables the practically-achievable, gate-stacking design for our Ge-dot photoMOSFETs. Both the gate oxide thickness and the diameter of the Ge dots are controllable. Large photocurrent enhancement was achieved for our Ge-dot photoMOSFETs when electrically-biased at ON- and OFF-states based on the Ge dot mediating photovoltaic and photoconductive effects, respectively. Both photoelectric conversion efficiency and response speed are significantly improved by reducing the gate-oxide thickness from 38.5 nm to 3.5 nm, and by decreasing Ge-dot size from 90 nm to 50 nm for a given areal density of Ge dots. Photoresponsivity () values as high as 1.2 × 104 A/W and 300 A/W are measured for 10 nW illumination at 850 nm and 1550 nm, respectively. A response time of 0.48 ns and a 3 dB-frequency of 2 GHz were achieved for 50 nm-Ge-dot photoMOSFETs with channel lengths of 3 μm under pulsed 850 nm illumination. [ABSTRACT FROM AUTHOR]

A novel gate-all-around (GAA) poly-Si floating-gate (FG) memory device with triangular nanowire (NW) channels was fabricated and characterized in this work. The enhanced electric field around the corners of the NW channels boosts more electrons tunneling through the tunnel oxide layer during programming and erasing (P/E) processes, and thus the operation voltage markedly decreases. Furthermore, the nonlocalized trapping feature characteristic of the FG makes the injection of electrons easier during the programming operation, which was demonstrated by technology computer-aided design (TCAD) simulations. [ABSTRACT FROM AUTHOR]

In this work, we have successfully demonstrated the feasibility of a method, which relies solely on I-line-based lithography, for fabricating sub-100 nm tri-gated junctionless (JL) poly-Si nanowire (NW) transistors. This method employs sidewall spacer etching and photoresist (PR) trimming techniques to shrink the channel length and width, respectively. With this approach, channel length and width down to 90 and 93 nm, respectively, are achieved in this work. The fabricated devices exhibit superior device characteristics with low subthreshold swing of 285 mV/dec and on/off current ratio larger than 107. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) nanowire (NW) memory devices with a SiN- or Hf-based charge-trapping (CT) layer of the same thickness were studied in this work. The GAA NW devices were fabricated with planar thin-film transistors (TFTs) on the same substrate using a novel scheme without resorting to the use of advanced lithographic tools. Owing to their higher dielectric constant, the GAA NW devices with a HfO2 or HfAlO CT layer show greatly enhanced programming/erasing (P/E) efficiency as compared with those with a SiN CT layer. Furthermore, the incorporation of Al into the Hf-based dielectric increases the thermal stability of the CT layer, improving retention and endurance characteristics. [ABSTRACT FROM AUTHOR]

A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings. [ABSTRACT FROM AUTHOR]

In this study, we proposed a new methodology for probing the electrical properties of heavily doped polycrystalline silicon (poly-Si) nanowires (NWs), including active doping concentration, mobility, and interface fixed charge density. Implementation of this procedure is based on the modulation of the device operation of a gate-all-around (GAA) junctionless (J-less) transistor from the gated resistor mode to the ungated one. The extracted carrier concentration in the NW is found to be much lower than that of Hall measurements, while a negative fixed charge density is identified with the procedure. Dopant segregation at the oxide interface is postulated to be closely related to these observations. [ABSTRACT FROM AUTHOR]

We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9 \times 10^\mathrm \mathbf 7 and 4.2 \times 10^\mathrm \mathbf 7 , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics. [ABSTRACT FROM AUTHOR]

Beginning with our exciting discovery of germanium (Ge) spherical quantum-dot (QD) formation via the peculiar and symbiotic interactions of Si, Ge, and O interstitials, we have embarked on a journey of vigorous exploration, creating unique configurations of self-organized Ge-QDs/Si-containing layers. Our aim is to generate advanced Ge-QD photonic devices, while using standard, mainstream Si processing techniques. This paper summarizes our portfolio of innovative Ge-QD configurations. With emphasis on both controllability and repeatability, we have fabricated size-tunable, spherical Ge-QDs that are placed at predetermined spatial locations within Si-containing layers (SiO2, Si3N4, and Si) using a coordinated combination of lithographic patterning and self-assembled growth. We have successfully exploited the multi-dimensional, parameter spaces of process conditions in combination with layout designs to achieve exquisite control available through the thermal oxidation of lithographically patterned, poly-Si1 − xGex structures in close proximity with Si3N4/Si layers. In so doing, we have gained insight into the growth kinetics and formation mechanisms of self-organized, Ge spherical QDs embedded within SiO2, Si3N4, and Si layers, respectively. Our Ge-QD configurations have opened up a myriad of process/integration possibilities including top-to-bottom evanescent-wave coupling structures for SiN-waveguided Ge-QD photodetectors and Ge-QD light emitters for Si photonics within Si3N4 integrated photonics platforms for on-chip interconnects and sensing. [ABSTRACT FROM AUTHOR]

In this study, we explore the operation of operation a novel asymmetric Schottky-barrier transistor (ASSBT) through using technology computer aided design (TCAD). The new ASSBT features a silicided Schottky-barrier (SB) source, with the channel and drain made of heavily n-doped silicon. By eliminating the SB drain junction contained in conventional symmetrical-type SB metal–oxide–semiconductor field-effect transistors (MOSFETs), a larger on-state current is achievable. Moreover, combined with the adoption of fully depleted thin-film channel, the off-state leakage current can be efficiently suppressed as well. In addition, we also comprehensively analyze the transport mechanisms dominating in different operational regions of this new ASSBT. A pseudo-subthreshold region that shows worse subthreshold swing (SS) than the subthreshold region is identified. A decrease in channel and/or gate oxide thicknesses can contribute to the improvement of the SS of this region. A modified form of scaling length (λ) is also introduced to describe the impacts of structural parameters and gate configurations on the SS characteristics of this new ASSBT. [ABSTRACT FROM AUTHOR]

In this study, we derive an analytical model of an electric potential of a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On the basis of this two-dimensional electric potential model, subthreshold current and swing can be calculated. Threshold voltage roll-off can also be estimated with analytical forms derived using the above model. The calculated results of electric potential, subthreshold current and threshold voltage roll-off are all in good agreement with the results of technology computer aided design (TCAD) simulation. The model proposed in this paper may help in the development of a compact model for simulation program with integrated circuit emphasis (SPICE) simulation and in providing deeper insights into the characteristics of short-channel J-less transistors. [ABSTRACT FROM AUTHOR]

In this study, we investigate the merits of an independent double-gated configuration for nonvolatile memory operations. In contrast to the convention where the programming/erasing gate also acts as the read gate, a dedicated read gate with an oxide-only dielectric is proposed in the new mode. Using the same device under identical programming/erasing conditions, greatly improved programming speed (e.g., 61% increase under the stress condition of 18 V for 10 µs) is achieved, while the erasing speed, albeit initially retarded, shows enhancement when the erasing time is larger than a certain value, which can be explained by the back-gate bias effects. Retention characterization indicates that the new mode offers a larger memory window after 10 year extrapolation. In addition, a proper auxiliary gate bias applied during programming/erasing processes is found to improve the programming/erasing speed. Finally, by taking advantage of the separate-gated feature, two independent storage sites can be obtained by employing an oxide–nitride–oxide layer as the dielectric for both gates, thus realizing 2-bit/cell functionality. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices. [Copyright &y& Elsevier]

Abstract: This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal–oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal–oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. [Copyright &y& Elsevier]

Discusses a study which investigated polysilicon etching with three-halogen bearing plasmas in an electron-cyclotron-resonance reactor. Review of related literature; Methodology; Findings.

Moreover, at the end of third paragraph in "4.1 SiN-embedded Ge-QD microdisk light emitters", unnecessary "Ge QD SiN silicon oxide air" has been remained. Thanks to the high absorption coefficients and pseudo-direct band-gap properties of Ge near the C-band communication wavelengths, active photonic devices (light sources and photodetectors) in Si PICs are enabled [2, 3] with small form factors on 2-D silicon-on-insulator (SOI) platforms. [Extracted from the article]

Highlights: [•] Carrier concentration increased with reducing oxygen flow tends to enhance u FE, on-current; reduce V th, SS. [•] r ch is higher while μE is lower in the films with a higher oxygen flow. [•] Increasing O2 flow decreases In atom% and increases Zn atom% of IGZO films. [•] Increasing O2 flow increases channel resistance and contact resistance. [•] Visible decline in μ FE as shorter channel length of devices with higher O2 flow. [ABSTRACT FROM AUTHOR]

In this study, novel n-type double-gate (DG) junction-less (J-less) polycrystalline silicon (poly-Si) nanostrip transistors with different channel doping concentrations (NC) have been fabricated and investigated. The effects of channel doping concentration on device characteristics were examined comprehensively in this work. The experimental data show that as the channel doping concentration of the J-less device increases, the threshold voltage (VTH) becomes more negative. Besides, the drain-induced barrier lowering and the subthreshold swing of the J-less transistors become larger as the channel doping increases. We also found that as the channel doping increases, the off-current (IOFF) increases and the on-current (ION) actually decreases due to the doping-dependent mobility degradation. The conduction mechanisms under different channel doping concentrations were also investigated by TCAD simulation. The experimental results suggest that the n-type DG nanostrip J-less transistor with lower channel doping will have superior device characteristics. [ABSTRACT FROM AUTHOR]

Abstract: In this study, the influence of indium tin oxide (ITO) top electrodes with different oxygen contents on the resistive switching characteristics of HfOx/TiN capacitor structure is investigated. Switching parameters, including set and reset voltage values, and high and low resistance values are highly related to the properties of ITO thin films. Higher resistance values in both states can be obtained when ITO thin films with higher oxygen contents are used as top electrodes; such values are accompanied by larger set voltages and fluctuating transient currents during the reset process. Based on the proposed filament model, we suggest that the switching mechanism of HfOx/TiN structure is attributed to the formation and rupture of conducting filamentary paths near the anodic side, which is highly correlated with the properties of the top electrode. The top electrode must be well determined to obtain reliable switching properties. [Copyright &y& Elsevier]

Abstract: A transparent resistive random access memory used as Indium Tin Oxide (ITO) electrode, ITO/HfO2/Al2O3/…/HfO2/Al2O3/ITO capacitor structure is fabricated on glass substrate by atomic layer deposition. The unipolar resistive switching characteristics can be performed by applying the positive- or negative-bias through top electrode, however, the differences of switching and stability in the two different operations can be observed. The diversities of electrical property are attributed to different oxide/ITO interface materials, which influence the current flow of the injected electrons. [Copyright &y& Elsevier]

Abstract: High performance nickel-induced lateral crystallization (NILC) polycrystalline silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) were fabricated. The phosphorous-doped amorphous silicon (α-Si)/chem-SiO2 films were employed as Ni-gettering layers to investigate effect of Ni residues on the performance and the uniformity of NILC poly-Si NW TFTs. It was found that the performance and the uniformity of NW TFTs were greatly improved after Ni-gettering process. [Copyright &y& Elsevier]

Abstract: Enhanced surveillance of influenza requires rapid, robust, and inexpensive analytical techniques capable of providing a detailed analysis of influenza virus strains. Functionalized poly-crystalline silicon nanowire field-effect transistor (poly-SiNW FET) was demonstrated to achieve specific and ultrasensitive (at fM level) detection of high pathogenic strain virus (H5 and H7) DNA of avian influenza (AI) which is an important infectious disease and has an immediate need for surveillance. The poly-SiNW FET was prepared by a simple and low-cost method that is compatible with current commercial semiconductor process without expensive E-beam lithography tools for large-scale production. Specific electric changes were observed for AI virus DNA sensing when nanowire surface of poly-SiNW FET was modified with complementary captured DNA probe and target DNA (H5) at fM to pM range could be distinguished. With its excellent electric properties and potential for mass commercial production, poly-SiNW FET can be developed to become a portable biosensor for field use and point-of-care diagnoses. [Copyright &y& Elsevier]

Abstract: In this paper, we report a conduction-type-tunable carbon nanotube field effect transistor (CNT-FET) with double-gate structure (DG CNT-FET). In this study, a specially designed narrow top-gate is created to modulate the energy band in the middle region of a single CNT. In the proposed DG device structure, the top-gate and bottom-gate biases exhibit independent modulation behaviors. Depending on whether a positive or negative bias is applied to the top-gate, the CNT-FET can be operated in either n- or p-type conduction. Energy band diagram conducive to the physical mechanisms of the proposed DG CNT-FET device structure is proposed. Based on the proposed hypothesis, ambipolar CNT-FETs can indeed be converted to n- or p-type-like behaviors. [Copyright &y& Elsevier]

Semiconductor-based quantum registers require scalable quantum-dots (QDs) to be accurately located in close proximity to and independently addressable by external electrodes. Si-based QD qubits have been realized in various lithographically-defined Si/SiGe heterostructures and validated only for milli-Kelvin temperature operation. QD qubits have recently been explored in germanium (Ge) materials systems that are envisaged to operate at higher temperatures, relax lithographic-fabrication requirements, and scale up to large quantum systems. We report the unique scalability and tunability of Ge spherical-shaped QDs that are controllably located, closely coupled between each another, and self-aligned with control electrodes, using a coordinated combination of lithographic patterning and self-assembled growth. The core experimental design is based on the thermal oxidation of poly-SiGe spacer islands located at each sidewall corner or included-angle location of Si3N4/Si-ridges with specially designed fanout structures. Multiple Ge QDs with good tunability in QD sizes and self-aligned electrodes were controllably achieved. Spherical-shaped Ge QDs are closely coupled to each other via coupling barriers of Si3N4 spacer layers/c-Si that are electrically tunable via self-aligned poly-Si or polycide electrodes. Our ability to place size-tunable spherical Ge QDs at any desired location, therefore, offers a large parameter space within which to design novel quantum electronic devices. [ABSTRACT FROM AUTHOR]

In this paper, we present the fabrication and characterization of gate-all-around (GAA) junctionless (JL) poly-Si nanowire (NW) transistors with a dual-gated configuration, in which a sub-gate is placed over a shorter main-gate in order to control the NW potential for the offset regions between the main-gate and S/D regions. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. Inevitable misalignment of lithographic patterning for the main-gate structure leads to asymmetrical channel offsets between the main-gate to source pad and to drain pad, respectively. That is, the length of un-gated NW close to the source pad differs from that to the drain pad. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end. Such a trend become less profound as the sub-gate bias increases. • The fabrication of GAA JL poly-Si NW transistors with a dual-gated configuration. • The influence of asymmetric offsets on I D becomes less profound with increasing V sub-gate. • TCAD simulation is used to verify the mechanism of the experimental results. [ABSTRACT FROM AUTHOR]

Abstract: This study used powders containing different In2O3–Ga2O3–ZnO (IGZO) chemical compositions to manufacture targets using a metallurgical process. The resulting targets were used to deposit amorphous In–Ga–Zn–O (a-IGZO) channel films by a radio frequency magnetron sputtering process. This study examined the relationships between these target compositions and crystalline phases of the powders and the resulting material characterization, examining the impacts on electrical characteristics of a-IGZO films with varied O2 flow rates. The ternary compound phase of ZnGa2O4 became stable at 1000°C according to XRD diagrams at different calcining temperatures. An analysis of the XRD diagrams of different compositions of IGZO powders showed that the atomic ratio of ZnO is larger than that of In2O3 and Ga2O3, and that the main peaks (101) and (0015) intensity of the respective InGaZnO4 and InGaZnO6 phases intensity would increase. Ceramic targets with different compositions were used to deposit the a-IGZO films with varied O2 flow rates. When the O2 flow rate was zero, the results of a Hall measurement of a-IGZO films deposited from targets with higher Zn atomic ratio showed lower resistivity, higher carrier concentration, and lower mobility. Nevertheless, as the O2 flow rate was more than 5sccm, increasing the atom ratio of Zn in the IGZO ceramic target obviously increased the capability of capturing O2 in the a-IGZO films, leading to higher resistivity, lower carrier concentration (<1018 cm−3), and higher mobility. [Copyright &y& Elsevier]

We reported transport diagrams of self-assembled germanium (Ge) double quantum-dots (DQDs) using direct current measurement under illumination at wavelength (λ) of 850 nm and at the base temperature of 4.5 K. Ge DQDs with a coupling-barrier of Si, tunneling-barriers of Si 3 N 4 , and self-aligned p + -Si reservoirs were fabricated in a self-organized CMOS approach. Charge transport through the Ge-DQDs is facilitated by photon-assisted tunneling. Characteristic gate-controlled hexagonal-shaped cells over a wide range of hole occupancy are acquired thanks to hard-wall confinement. Large dimensions (ΔV G  > 200 mV) of hexagonal-shaped cells are favored for the operation of charge states, indicating that our Ge DQDs system is less susceptible to shot noises arising from external voltage sources. Estimated intra-QD and inter-QD charging energies are E C,R /E C,L  = 48.9 meV/42.7 meV and E Cm  = 7.8 meV, respectively., (© 2024. The Author(s).)

Over the past decade, SnO has been considered a promising p-type oxide semiconductor. However, achieving high mobility in the fabrication of p-type SnO films is still highly dependent on the post-annealing procedure, which is often used to make SnO, due to its metastable nature, readily convertible to SnO 2 and/or intermediate phases. This paper demonstrates a fully room-temperature fabrication of p-type SnO x thin films using ion-beam-assisted deposition. This technique offers independent control between ion density, via the ion-gun anode current and oxygen flow rate, and ion energy, via the ion-gun anode voltage, thus being able to optimize the optical band gap and the hole mobility of the SnO films to reach 2.70 eV and 7.89 cm 2 V -1 s -1 , respectively, without the need for annealing. Remarkably, this is the highest mobility reported for p-type SnO films whose fabrication was carried out entirely at room temperature. Using first-principles calculations, we rationalize that the high mobility is associated with the fine-tuning of the Sn-rich-related defects and lattice densification, obtained by controlling the density and energy of the oxygen ions, both of which optimize the spatial overlap of the valence bands to form a continuous conduction path for the holes. Moreover, due to the absence of the annealing process, the Raman spectra reveal no significant signatures of microcrystal formation in the films. This behavior contrasts with the case involving the air-annealing procedure, where a complex interaction occurs between the formation of SnO microcrystals and the formation of SnO x intermediate phases. This interplay results in variations in grain texture within the film, leading to a lower optimum Hall mobility of only 5.17 cm 2 V -1 s -1 . Finally, we demonstrate the rectification characteristics of all-fabricated-at-room-temperature SnO x -based p-n devices to confirm the viability of the p-type SnO x films.

A new phenomenon of highly localized, nanoscale densification and crystallization of silicon-nitride (Si 3 N 4 ) layers has been observed. A drastic reduction in the thermal budget (temperature and processing time) for local densification and even nanocrystallization of low-pressure chemical vapor deposited amorphous Si 3 N 4 layers is mediated by the presence of Ge, Si, and O interstitials in close proximity to the Si 3 N 4 . The enhancement of localized densification and nanocrystallization observed in Si 3 N 4 layers appears to be catalyzed by proximal Ge quantum dots (QDs) 'migrating' through the Si 3 N 4 /Si layers and are influenced by the oxidation time and Ge QD size. Implications of the highly localized, nanoscale densification and crystallization of silicon-nitride (Si 3 N 4 ) layers for photonic and electronic device applications are discussed.

We report a novel visible-near infrared photoMOSFET containing a self-organized, gate-stacking heterostructure of SiO 2 /Ge-dot/SiO 2 /SiGe-channel on Si substrate that is simultaneously fabricated in a single oxidation step. Our typical photoMOSFETs exhibit very large photoresponsivity of 1000-3000A/W at low optical power (< 0.1μW) or large photocurrent gain of 10 3 -10 8 A/A with a wide dynamic power range of at least 6 orders of magnitude (nW-mW) linearity at 400-1250 nm illumination, depending on whether the photoMOSFET operates at V G = + 3- + 4.5V or -1- + 1V. Numerical simulations reveal that photocarrier confinement within the Ge dots and the SiGe channel modifies the oxide field and the surface potential of SiGe, significantly increasing photocurrent and improving linearity.

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.

In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al.