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Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire.
- Source :
- Applied Physics Letters; 10/7/2013, Vol. 103 Issue 15, p153102-153102-4, 1p, 3 Diagrams, 2 Graphs
- Publication Year :
- 2013
-
Abstract
- A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings. [ABSTRACT FROM AUTHOR]
- Subjects :
- POLYCRYSTALLINE silicon
FERROELECTRIC RAM
POLYCRYSTALS
NANOWIRES
NANOWIRE devices
Subjects
Details
- Language :
- English
- ISSN :
- 00036951
- Volume :
- 103
- Issue :
- 15
- Database :
- Complementary Index
- Journal :
- Applied Physics Letters
- Publication Type :
- Academic Journal
- Accession number :
- 90679690
- Full Text :
- https://doi.org/10.1063/1.4824817