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Selective laser melting (SLM), also known as 3-D printing or additive manufacturing process, has been developed for over 2 decades. This technique exhibits the capability to fabricate three-dimensional metal objects of complex geometries & structures from metal powders used in aerospace or medical orthopedics. This additive manufacturing technology has received a lot of attention, because various metals and metal alloys can now be processed to manufacture metal parts or structures, which includes the technologically important metals of stainless steel, cobalt chrome, titanium, tungsten and various other alloys. Typically SLM selectively melts thin layers of fine metal powder above each other by using a focused laser beam with high thermal energy on a substrate plate under argon atmosphere, resulting in production of almost full density metal or alloy parts. In this fashion successive layers of material are formed according to the computer edited 3-D-CAD design. Thereby, SLM could be applied to make functional end-use and geometrically complex products with cost-effect process especially in industry. Due to the geometrically complex form of the SLM manufactured structures, atomic layer deposition (ALD) is uniquely suitable to control the composition, thickness and conformability of thin films in the large scale and complex structures. In this study we report ALD coatings of Al2O3 of SLM stainless steel with the objective of providing corrosion protection by an alumina diffusion barrier and ALD ZrO2 coatings. During the course of this work we found the parts fabricated by 3-D printers tend to be porous and exhibit a rough texture. Figures 1 (a) show FE-SEM micrographs at progressively larger magnification of the surface of the 3-D printed stainless steel samples. As can be seen, the surface is very rough and contain many beads or spheres produced during the SLM manufacturing process, which is a direct result of the laser melting of the metal powder and rapid quenching. In order to reduce the surface roughness of the 3-D printed samples, electropolishing was used to smoothen and streamline the rough surface of the 3-D samples. After electropolishing, the surface of the 3-D printed samples is bright, clean and microscopically smooth and featureless. There are no beads or spheres remaining on the samples as shown in Figures 1 (b). We used SLM 316 stainless steel samples in a cross-flow ALD reactor with TMA and H2O vapor to attempt ALD coatings, while TDMA-Zr and H2O were used as precursors for ALD ZrO2. The analysis of the ALD Al2O3 and ZrO2 films revealed satisfactory chemisorption on the 3-D printed stainless steel surface. The ALD Al2O3 and ZrO2 films were uniformly grown on the 3-D printed stainless steel surface as shown in Figure 2. Figure 1

As a green renewable technology, thermoelectric contributes to save energy by recovering waste heat into electricity based on Seebeck effect, and the inverse process based on the Peltier effect can be used for cooling. The primary challenge is to increase the efficiency of thermoelectric materials, which is expressed by the dimensionless thermoelectric figure of merit, ZT = S2σT/ k, where S is the Seebeck coefficient, σ is the electrical conductivity, and k is the thermal conductivity. A promising approach is to use low dimensional structured materials in order to improve the ZT value, such as 2-D superlattice structure, 1-D nanowire, and 0-D quantum dots. Initially it was assumed that the quantum confinement effect in lower dimensional structure results in an increase of the density of state near the Fermi level and consequently in an enhancement of the thermal power (S2σ). However, most experimental works found reduction in thermal conductivity plays a dominate role in enhancing ZT value, resulting from phonon scattering by numerous interfaces in low dimensional structures. Very recently, researchers focused their attention on phononic crystal (PnC) nanostructures in thermoelectric materials. The thermal conductivity of PnC samples is lower compared to non-patterned thermoelectric samples [1] due to phonon-boundary scattering. It has been demonstrated that porous silicon has lower thermal conductivity up to two orders of magnitude than bulk silicon [2, 3]. Our previous work indicates PbTe/PbSe nanolaminates grown on porous silicon membranes have higher Seebeck coefficients than the ones grown on regular silicon wafers. The higher Seebeck values result from the lower thermal conductivity k in porous structures. Consequently thermal conductivity of the film could be reduced and in term ZT could be enhanced by adjusting the size and periodicity of the pattern and the thickness of the thermoelectric film in relation to the mean free path (MFP) of the phonons of the TE material. Significant efforts have been made to investigate the IV-VI semiconducting lead chalcogenides, such as PbTe and PbSe due to their high figure of merit, good chemical stability, low vapor pressure and high melting point. This TE material can be synthesized by pulsed laser deposition (PLD), metal-organic chemical vapor deposition (MO-CVD), magnetron sputtering, molecular beam epitaxy (MBE) and atomic layer deposition (ALD). Since ALD is a self-limiting atomic layer reaction in each ALD cycle introduce, it can precisely control the film layer thickness, stoichiometry, composition, uniformity, and sharp interface. ALD also can be used to deposit conformal films onto very complex structures. In this work we report on the successful synthesis of PbTe and PbSe on patterned silicon substrates by a thermal ALD system. The stripe patterned silicon substrates were fabricated by etching silicon wafers in KOH solution followed by photolithography process with a stripe mask. Figure 1 provides schematic diagram of the stripe patterned silicon substrate. Different sizes of the stripe pattern were fabricated to investigate size effect of the pattern on thermoelectrical properties of the films. Lead bis(2,2,6,6-tetramethyl-3,5-heptanedionato) (Pb(C11H19O2)2), (trimethylsilyl) telluride ((Me3Si)2Te) and (trimethylsilyl) selenide ((Me3Si)2Se) were employed as the chemical ALD precursors for lead, telluride and selenide, respectively. 20 sccm N2 was used as a carrier gas to transport the chemical precursors into the ALD reaction chamber. The ALD growth temperature was 150 ˚C. The solid lead precursor was volatilized at a temperature of 170 ˚C, the liquid Te precursor required heating to 40 ˚C, and the liquid Se precursor was kept at room temperature. The chamber base pressure was kept at 30 mTorr. Since the MFP of PbTe or PbSe is around 10~20 nm. The film thickness was controlled around 10~20 nm, aiming to confine thermal transport along film coating direction and be scattered by closed patterns. Several physical characterization techniques have been employed to determine the surface characteristics of the sample. The samples were characterizated by X-ray diffraction (XRD) for film crystal structure, and by field emission scanning electron microscopy (FE-SEM) for film morphology and structure. The surface roughness was analyzed by atomic force microscopy (AFM). The analysis of the composition and stoichiometry of the ternary and binary layers were carried out by X-ray photoelectron spectroscopy (XPS) and Energy dispersive X-ray spectroscopy (EDS). For thermoelectrical properties of the sample, Seebeck coefficient, electrical conductivity and thermal conductivity of the films were measured to determine the ZT value of the samples as a function of pattern size. References: 1. Nakagawa, J., et al., Applied Physics Letters, 2015. 107(2): p. 023104. 2. Romano, G. and J.C. Grossman, Applied Physics Letters, 2014. 105(3): p. 033116. 3. Song, D. and G. Chen, Applied physics letters, 2004. 84(5): p. 687-689. Figure 1

Film quality and crystalline perfection of SOI layers obtained by bonding and etch back silicon-on-insulator (BESOI) technology have been studied. In particular, the various mechanisms of defect generation that contribute to a degradation of the original bulk Si quality in the superficial Si layer of such SOI structures have been investigated. Utilizing transmission x-ray topography combined with transmission electron microscopy (TEM), the critical processing parameters causing defect generation have been identified and the principal mechanisms of dislocation nucleation have been elucidated. Strain compensated bonded SOI wafers have also been evaluated by non-destructive elastic light scattering and optical beam induced current (OBIC) to obtain topographic defect maps of entire SOI wafers. This analytical technique has the capability to comprehensively characterize surface and subsurface morphological features which result from the bonding and thinning processing steps. A comparison of wafer bonding and etch back technology with different etch stop fabrication techniques is presented. In this review, it is demonstrated that the presence of a boron-doped etch stop layer, with its accompanying lattice contraction and strain compensation, represents a key difference in the observed morphological patterns of bonded SOI wafers.

The incorporation of strain is inherent in the manufacture of bond and etchback silicon-on-insulator (BESOI) substrates. In this paper, the principal sources of strain are identified and the magnitude of the strain is estimated. The strain sources discussed include dopant (boron) induced lattice contraction of the etchstop layer, differential thermal expansion, and interfacial microroughness at the time of bonding. Reduction or elimination of SOI layer degradation from some of these strain sources is possible.

Alternative deposition methods and materials are of interest for the fabrication of thin film solar cells since they offer potential enhancements for either low cost, high speed or high efficiency but also because they can help in better understanding the underlying physical and chemical processes that could lead to the next generation of solar cells. In this study, we will present new results on the deposition of ZnS by atomic layer deposition (ALD) as an alternate to CdS deposited by chemical bath deposition.

In recent years, the use of III-V nitride compound semiconductors such as GaN, AlN, and InN has seen a rapid growth in the optoelectronics industry. Due to the efficient emission of light based on their direct bandgap several compound semiconductors are attractive for hybrid devices for optoelectronic and photovoltaic applications. It is widely acknowledged that the exploitation of the full potential of these emerging technologies is held back primarily by the high cost of prime grade crystalline quality material and the relative small wafer diameters available. On top of these challenges commercially available epitaxial samples suffer from high defectivity, because of the large lattice mismatch between these semiconductors and the commonly used sapphire substrate. In this context wafer bonding provides an alternative approach to integrate dissimilar material systems with superior crystal quality devoid of epitaxial lattice defects and at reasonable cost. The heterogeneous integration process combines semiconductor wafer bonding technology with the ion cutting process by hydrogen implantation in order to achieve novel composite material systems that are unattainable by conventional epitaxy techniques1. One of the possibilities to reduce the material cost would be the application of the ion-cut process to cleave several thin layers from the same wafer and their transfer onto foreign and cheap substrates. In principle, this ion-cut, a generic process based on light ion (using H or He) implantation and wafer bonding, can be used to transfer bulk quality fine layers onto foreign substrates thereby achieving heterostructures frequently unattainable by other methods such as epitaxy. The transfer of several layers from the initial starting wafer affords a significant reduction of the material cost. Avoiding conventional epitaxy techniques with their inherent lattice mismatch challenges when marrying dissimilar semiconductor materials constitutes a major advantage for the wafer bonding and layer transfer technology. There are two approaches to affect the bonding of dissimilar materials. In the first approach the wafers are directly bonded without the use of an intermediate layer. In the second case bonding is achieved via an intermediate layer, which is a dielectric layer in most applications. Following successful bonding of dissimilar materials the heterointegration process will be completed by release of a thin layer of the III-V semiconductor. The release and transfer of such thin layers to foreign substrates is accomplished by cleaving ion implanted III-V samples. The state-of-the-art technique is to implant, the compound semiconductor samples by H or He energetic ions to create a mechanically weak zone a below the surface of the donor wafer2. The influence of the implant fluence, the post implant annealing conditions required for the layer transfer and the resulting material modifications weakening the cleavage zone will be reviewed. Systematic studies of the influence of thermal treatment and implant dose on cleavage behavior have been performed with high resolution TEM cross-sectional analysis combined with other relevant physical characterization techniques3. Fig. 1 displays the example of AlN, where the hardness increases with annealing temperature rendering the III-V material more brittle. This presentation provides new insights in the mechanical behavior of hydrogen implanted III-V semiconductors throughout subsurface microcracking leading to thin film transfer following heterogeneous wafer bonding.

Resistive memory is being considered for next-generation non-volatile memory due to the inherent simplicity, scalability and low cost [1, 2]. Additionally, these devices show potential to replace static random access memory (SRAM) as high performance switches for reconfigurable devices [3, 4]. These devices operate by changing resistance from high (Roff) to low (Ron) values in response to applied voltage due to the formation and rupture of a metal filament as shown in Figure 1.

An active area of research in the field of photovoltaics that strives to significantly improve energy conversion efficiencies involves the exploration and manipulation of device physical structures. With knowledge gleaned from the fabrication of standard planar organic solar cells, our group has developed a technique for creating nanoscale nested structures capable of accommodating organic photoactive material that serves as a light-absorbing layer. The technique employs highly-ordered macroporous silicon templates that are used as the supporting structure and bottom contact for concentrically-nested metal oxide cylinders.

Recently, two-terminal metal-oxide-based devices showing memresitive behavior have been attracting much attention due to their promising characteristics for next generation memory and logic technologies [1]. Among different types of memresitive mechanisms, TaO X based devices combined with copper and platinum electrodes have been known to utilize metal precipitation to create conductive channel inside of the oxide thin film when a low electric voltage (only around 1V between top and bottom electrodes) is applied [1]–[3]. This unique mechanism can deliver an opportunity to explore a new type of multifunctional device; for example, the formed metal nano-filament inside of TaO X can be used as an electron spin transport channel [4].

We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO(2) charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO(2) increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO(2) thickness, which is in good agreement with simulation results. Our work also shows that the Omega gate structure improves the program speed and retention time for memory applications.

Zinc oxide (ZnO) is an important emerging material for the applications in thin film transistors, optoelectronic devices, transparent electrodes and solar cells, in the forms of thin films, tubes, rods, and nano-wires. ZnO can be deposited by pulsed laser deposition, radio-frequency magnetron sputtering, thermal synthesis and atomic layer deposition (ALD). In this study, ZnO thin films were deposited by ALD at low temperature using diethyl zinc (DEZn) and water precursors and were characterized by various techniques. ZnO tubes and rods were obtained using ALD and template replication method.

Optimizing the efficiency of polymer-based, planar organic solar cells requires nanoscale control of the thicknesses of constituent layer materials composing the device. A thin film optical simulation modeling tool has been used to determine ideal active layer thicknesses for regioregular poly(3-hexylthiophene) and phenyl-C 61 /C 71 -butyric acid methyl ester (P3HT-PC 61 BM and P3HT-PC 71 BM) organic blends used as photoactive components in polymer solar cells. Using the well understood transfer matrix formalism, solar cells are simulated layer-by-layer after varying such factors as active layer thickness and electron and hole mobilities. Spectral absorption, fill factor (FF), power conversion efficiency (PCE), and current-voltage (I–V) characteristics are obtained and the most effective active layer thicknesses determined that will enable maximum efficiency to be achieved. Figure 1 shows the simulated current densities of P3HT:PC 61 BM and P3HT:PC 71 BM as a function of device thickness and carrier mobility. This device simulation indicates the potential of higher current density achievable using P3HT:PC 71 BM. We will discuss the systematic study of the effect of the charge carrier mobilities on the current density, open circuit voltage, and fill factor as a function of device thickness.

It is well established that the strain in sSOI wafers can be maintained during the high temperature processing steps required by CMOS technology if suitable precautions are taken during patterning of the sSOI wafer into device islands [1]. Routinely a rigid capping layer, such as SiO 2 is used to reduce strain relaxation caused by cutting the strained film into small islands. Here, we study the simplest but scientifically relevant case, where in the absence of capping layers or any other precautions, strain relaxation by film patterning and high temperature annealing can be observed. The thermal stability of bi-axial strain is maintained solely by a non-epitaxial bonded interface with the amorphous buried oxide in sSOI after patterning and subsequent high temperature annealing.

There is a widely recognized need for urgent progress in non-volatile memory (NVM) technology, driven by the exponential market growth of ubiquitous portable and mobile electronics. To enable further scaling and achieve better portable electronics, the industry consensus is that fundamentally new innovations must be introduced beyond the 45-nm lithography node generation [1]. One of the approaches is to design NVM cells based on silicon nanowires (SiNWs) [2, 3]. The cylindrical symmetry of SiNWs leads to two aspects that enable SiNW NVM to outperform conventional planar FLASH NVM. (1) The electric field is more efficiently applied on the nanowire channel with the same control gate voltage, leading to higher performance at lower operation power. (2) Short channel lengths are possible with a minimal reduction of the dielectric stack thickness (to maintain good retention), making SiNW is particularly suitable for scaled NVM cells [4, 5]. Moreover, the use of high-k dielectric materials as gate stack and information storage medium will significantly improve the program speed and reliability for non-volatile memory [6].

Beyond 2011, when the channel length of a MOSFET transistor is projected to be 16 nm, effective scaling of classical planar bulk MOSFETs is expected to come to an end. Below 16 nm channel length, achieving adequate electrostatic control of short channel effects poses the most serious challenge. Non-classical double-gate, ultrathin-body transistors offer to minimize short-channel effects and allow for more aggressive scaling. Several three-dimensional (3-D) multigate structures such as FinFET, Trigate, MIGFET, ITFET [1] have been demonstrated with good electrical characteristics down to gate lengths of 12 nm. It is known from theoretical investigations that the ultimate MOSFET is realized as a nanowire (NW)-MOSFET transistor with a gate-all-around gate electrode shown in Fig. 1. In this work, a top-down approach has been adopted for the first-time to pattern single-crystalline Si NW on SOI substrates using planar technology processes. The two critical parameters of the nanowire are defined by the thickness of Si active layer and the width of a masking spacer, see Fig. 2. The NW has an elliptical cross-section having a semimajor axis less than 150 nm and the semiminor axis depending on process conditions. A complete mask set has been developed for the NW-MOSFET defining mesa island on Si and channel area of length between 5–20 µm, along with the location of the critical spacer deposition, see Fig.3. An additional mask has been fabricated to obtain channel length of about 800 nm using i-line photolithography. Solid source diffusion of phosphorus is being used to dope source/drain regions, providing at the same time a PSG glass masking layer to protect source/drain regions during subsequent process steps. A masking nitride layer of 200 nm proved sufficient to protect channel region from P doping, see Fig. 4. Because of the thinness of our active Si layer of only 88nm, our structures lend themselves to study phosphorus diffusion in two dimensional membranes and one-dimensional nanowires. Deposition and reactive ion etch recipes with appropriate selectivities have been developed to form a masking spacer of widths down to 150 nm range and to pattern the Si nanowire. Fig.5 shows an SEM picture of sub-200 nm twin oxide spacers. The spacer width can be modified by varying the initial oxide thickness deposited over the nitride mask. After the patterning of the active Si layer, the buried oxide layer BOX is underetched to provide all around access to the suspended Si nanorod. In parallel to the Si NW-MOSFET flow, the gate stack electrode has been developed using atomic layer deposition (ALD) method. Because of its nearly perfect uniformity, ALD is ideally suited to deposit a high-k dielectric HfO 2 of 25 A–40A shown in Fig.5 followed by Pt metal deposition also by ALD. Pt deposition on planar surfaces results in grain formation as seen in Fig.6. The roughness of the Pt surface could be controlled within 1 nm range. Such HfO 2 and Al 2 O 3 ALD high-k gate stacks have been applied successfully to grown Si nanowires and have been integrated subsequently into a Si nanowire non-volatile memory (NVM) process [2]. The present NW MOSFET structure can be used for NVM device applications with a gate-all-around gate structure. Currently, similar efforts are expended to fabricate a Ge NW MOSFET. Epitaxial deposition of high mobility III–V semiconductors on Si and Ge nanowires will be pursued in future work.

There is great interest in fabrication of semiconducting and piezoelectric nano-scale structures such as nanowires, nanorods and nanotubes [1–3]. These find applications ranging from sensors to sub-micron electronic devices such as field effect transistors (FET), switches, memory elements, logic arrays and MEMS. In all of these diverse applications nanostructured zinc oxide (ZnO) materials attract broad attention. This ongoing attention is justified by several unique multifunctional properties of ZnO [1]. Moreover, ZnO nanostructures such as quantum dots, wires, belts and nanotubes can be easily fabricated using Atomic Layer Deposition (ALD) over a wide range of templates such as nanoporous Anodic Aluminum Oxide (AAO).

The strain patterns detected by x‐ray topography in wafers bonded for silicon‐on‐insulator (SOI) technology were found related to the flatness nonuniformity of the original wafers. Local stresses due to the bonding process are estimated to be about 1×108 dynes/cm2. The stress is reduced about 100 times for the thin (0.5 μm) SOI films. Most of the wafer deformation occurs during room temperature mating of the wafers. The deformation is purely elastic even at 1200 °C. The magnitude of the stress appears insignificant for complimentary metal‐oxide‐semiconductor devices performance.

In the quest for new nonvolatile memory devices many new device concepts and materials systems have emerged in recent years. Notably MRAMs, FeRAMs, STTRAMs and RRAMs have attracted considerable attention and research efforts. Particularly in RRAM, the majority of these new developments are focusing on inorganic materials systems and very little work has been reported on organic or hybrid organic-inorganic memory related materials systems. Here we report on the resistive switching characteristics of a class of hybrid designer solids HKUST-1(Hong Kong University of Technology1) (or [Cu3(BTC)2]) SURMOF porous conductors which were loaded with ferrocene. SURMOF films are also referred to as porous coordination polymers (PCPs). The electrical conductivity of SURMOF films can be modulated by loading the pores with appropriate organic semiconductors. Loading with ferrocene or TCNQ can enable ion transport in addition to electron transport thus change the electrical conductivity. The SURMOF samples for this study have been grown on surface-functionalized Au-substrates by employing a layer-by-layer, liquid-phase epitaxial method. Device fabrication was carried out by depositing top electrodes from either Cu or Au using a commercial e-beam deposition system. Two different device stacks were fabricated and tested. The first device consisted of an Au/SURMOF/Cu/Au stack with SURMOF film thickness of around 75nm. The Cu/Au top electrode was deposited by e-beam evaporation with a thicknesses of 200nm and 25nm respectively and patterned with a shadow mask to produce disks of 200µm in diameter. The second device consisted of an Au/SURMOF/Al/Au stack with a SURMOF thickness of 10nm, 20nm and 50nm. The Al/Au top electrode was deposited by e-beam evaporation with a thicknesses of 700nm and 100nm respectively, and patterned with a shadow mask to yield disks of 150µm in diameter. A slow voltage ramp typically between -1.5V to +1.5V was used. Measurements have been performed on pristine samples directly after synthesis. Initially pristine SURMOF switching devices are in a high resistance state. In our device configuration the bottom electrode is grounded and the voltage is applied to the top electrode. In devices with Cu/Au as top electrode, ON was observed on negative voltage sweeps and OFF was observed on positive voltage sweeps. In devices with Al/Au top electrodes, ON was observed on positive voltage sweeps and OFF was observed on negative voltage sweeps. After increasing the voltage from 0 V to max. 0.75 V, a transition to a low resistance state is observed. The voltage was swept in the reverse polarity to switch from low to high resistance state. Current as high as 50mA was required to switch the device from low to high resistance state. Measurements were also performed on the unloaded SURMOF devices. Compared to the loaded device, the switching characteristics are quite poor. The observed phenomena are crucially dependent on ferrocene loading. Ferrocene loading increased the conductivity within the MOF layer and therefore lowers the resistance. The devices could be switched using pulse width longer than 20 ns. Although the device switched within tens of nanoseconds, the time of switching could not be established due to large device capacitance values. The polarity of the SET and RESET in the devices with the Cu as the top electrode rules out the possibility of Cu ion migration being the reason for formation and dissolution of the low resistance path during switching. Additionally, devices with Al top electrode were also measured. Similar to the Cu top electrode, the Al top electrode devices also showed resistive switching.

Atomic layer deposition (ALD) gas barrier layer coatings on polymer substrates have been studied to address the problem of short-lifetime of polymer devices. ALD Al2O3 layers deposited with trimethylaluminium (TMA) and H2O vapor precursors are relatively dense and conformal, so ALD Al2O3 layers are good candidates for effective gas barriers against water vapor and oxygen permeation. In order to seal such ALD Al2O3 coated polymer substrates without organic adhesives, the bonding technique of choice has to satisfy low temperature bonding requirements. Utilizing a high temperature bonding process would damage thermally sensitive polymer substrates during thermal compression bonding. Furthermore the gas barrier property of organic adhesives would be too low for effective sealing. The polymer substrates used in this study are polyimide (PI) sheets from XENOMAX® from Toyobo Co., Ltd that are widely used as substrates for flexible electronics. These polyimide sheets have extremely smooth surfaces (RMS ~1 nm), which are conducive for bonding, because good large contact areas can be obtained. These polyimide substrate sheets of 35 μm thickness were coated with Al2O3 films of 250 ALD cycles using different process temperatures ranging from 80 ºC, 150 ºC and 250 ºC, while 100 ALD cycles were used at 250 ºC. The warpage of the polyimide sheets, the surface morphology, and the results of bonding for these ALD Al2O3 coated polyimide samples were investigated as a function of different ALD deposition temperatures. The polyimide sample processed at the higher ALD Al2O3 temperature of 250 ºC exhibited much larger warpage, which is detrimental for bonding. We prepared PI sheets whose size was 10 cm x 10 cm. The ALD Al2O3 on polyimide samples deposited at 80, 150, and 250 ºC display warpage, and these edges lifted up to 1 mm, 3 mm, and 5 mm from a horizontal plane, respectively. This warpage is attributed to the difference of thermal expansion coefficients between the polyimide sheet and the deposited ALD Al2O3 layer. The surface morphology of the ALD layer was studied using atomic force microscopy (AFM) surface profiling. The sample deposited at a lower ALD temperature has smoother surface morphologies. Our ALD Al2O3 films synthesized at 80 ºC exhibited a very smooth surface morphology indicative of amorphous material, while the Al2O3 film synthesized at 250 ºC was observed to possess a granular structure demonstrating recrystallization into a polycrystalline film. The rough grain structure of ALD Al2O3 films deposited at 250 ºC exceeds the critical surface roughness and as a consequence prevents surfaces from bonding. For the bonding experiment, all PI samples coated by ALD Al2O3 were bonded using a modified method of Surface Activated Bonding (SAB) employing a nano-adhesion layer. First, ALD Al2O3 layers of about 25 nm are deposited on the surface of the polyimide substrates using trimethylaluminium (TMA) and water as precursors. Next, the Al2O3-coated surfaces are moved inside a high vacuum bonding machine and cleaned using Ar-ion beam bombardment. After the surface cleaning process step, Si nano-adhesive layers are deposited via ion-beam sputtering. Subsequently, the surface of the nano-adhesion layers are activated using the Ar-ion beam SAB method. Finally, surfaces were brought into close contact and bonded under compression in ultra-high vacuum. The structure of the bond interface was PI/Al2O3/Si/Si/Al2O3/PI. Here the thickness of each ALD Al2O3 layer and Si layer are 25 nm and 10 nm, respectively. We compared the results of the bonding of PI films coated at different ALD process temperatures. All bonding processes were performed at room temperature in ultra high vacuum. While the ALD Al2O3 samples deposited at 150 ºC suffered various non-bonded areas due to warpage and surface roughness, the ALD films deposited at 80 ºC revealed near perfect bonding without any voids, which is desirable for tight sealing of gas barrier layers. Room temperature bonding of ALD Al2O3 films on Si and polyimide substrates was successfully performed. Due to high temperature gradient induced warpage of the polymer substrate and elevated surface roughness of the ALD layer, a lower process temperature of 80 ºC for ALD synthesis of Al2O3 provided optimum gas barrier conditions. The results of our bonding experiments demonstrate that larger bonded areas were achieved when the ALD synthesis of Al2O3 gas barrier layers was performed at 80 ºC. This bonding method is expected to be used for future microelectronics packaging and gas barrier sealing for polymer substrate.

Thermoelectric (TE) materials can be applied for solid state power generation or heating/cooling systems that convert heat into electricity and vice-versa. The green renewable technology related to thermoelectrics could play an important role to decrease the energy consumption from fossil fuels and decrease greenhouse gas emission. The main challenge for thermoelectric devices produced currently is their low efficiency. Therefore, it is essential to develop high efficiency TE materials and devices with superior performance. The efficiency of TE materials is expressed by the dimensionless thermoelectric figure of merit, ZT = S2σT/ k, where S is the Seebeck coefficient, σ is the electrical conductivity, and kis the thermal conductivity [1]. Previous work has demonstrated two main TE materials have higher ZT values. The first TE material with a complex crystal structure called a phonon glass electron crystal in which the voids, defects, and rattlers could scatter phonons to decrease the lattice thermal conductivity, and thus to increase ZT. Another one is called nanomaterials: including quantum wells, quantum dots, superlattice, quantum wires and nanolaminates, which introduce a large density of interfaces to enhance phonon scattering. The thermal conductivity of these nanomaterials was effectively reduced, and the ZT of TE materials was improved significantly. The IV-VI semiconducting lead chalcogenides, such as PbTe and PbSe, have been investigated due to their high figure of merit, good chemical stability, low vapor pressure and high melting point. Therefore, they are promising thermoelectric materials for intermediate temperature applications ranging from 600 to 800 K. There are different techniques that can be used to synthesis PbTe and PbSe, including pulsed laser deposition (PLD), metal-organic chemical vapor deposition (MO-CVD), magnetron sputtering deposition, molecular beam epitaxy (MBE) and atomic layer deposition (ALD). The ALD is a self-limiting technique that allows atomic layer growth each time. ALD can precisely control the film layer thickness, stoichiometry, composition, uniformity, and sharp interface. ALD also shows perfect conformal coverage when it is deposited on complex surface structures. Therefore, ALD is considered as a novel and competitive method to deposit PbTe/PbSe nanolaminate structures. It is possible to generate the reproducible and well-defined nanolaminate structures. In addition, the ALD deposition can be operated at rather low temperature compared to other techniques. In this work we report on the Seebeck coefficient measurements in PbSeTe / PbSe nanolaminate structures. The multiple PbTe/PbSeTe nanolaminates were deposited on silicon substrates by a thermal ALD system. This new nanolaminate structure was achieved by first depositing a very thin layer of the PbSeTe ternary compound with binary PbTe layers. The PbSeTe ternary compound is formed by nucleation of PbSe quantum dots between binary PbTe layers, and followed by an annealing process step. It is noted that the formation of the PbSe quantum dots is facilitated by the prevailing Volmer-Weber island growth mode. Lead bis(2,2,6,6-tetramethyl-3,5-heptanedionato) (Pb(C11H19O2)2), (trimethylsilyl) telluride ((Me3Si)2Te) and (trimethylsilyl) selenide ((Me3Si)2Se) were employed as the chemical ALD precursors for lead, telluride and selenide, respectively. 20 sccm N2 was used as a carrier gas to transport the chemical precursors into the ALD reaction chamber. The ALD growth temperature was 170 oC. The solid lead precursor was volatilized at a temperature of 140 oC, the liquid Te precursor required heating to 40 oC, and the liquid Se precursor was kept at room temperature. The chamber base pressure was kept at 30 mTorr. Several physical characterization techniques have been employed to determine the ALD nanolaminate formation. The crystal structure was analyzed by X-ray diffraction (XRD). The film morphology and structure of the products were determined by field emission scanning electron microscopy (FE-SEM) and high resolution transmission electron microscopy (HR-TEM).The surface roughness was analyzed by atomic force microscopy (AFM). The analysis of the composition and stoichiometry of the ternary and binary layers were carried out by X-ray photoelectron spectroscopy (XPS) and Energy dispersive X-ray spectroscopy (EDS). The Seebeck coefficient of the sample was also measured in order to calculate ZT value using Seebeck coefficient measurement equipment of MMR SB100. Figure 1 shows an FE-SEM image of surface morphplogy of PbTe/PbSe nanolaminate films on silicon substrate. References: K. Zhang, A. D. Ramalingom Pillai, D. Nminibapiel, M. Tangirala, V. S Chakravadhanula, C. Kübelc, H. Baumgart, V. Kochergin, ECS Trans., 58, 10, 131 (2013). Figure 1

Due to various applications in electronic and optical fields, considerable efforts have been made to develop ZnO based semiconducting materials. ZnO has a wide and direct band gap of 3.37 eV, large exciton binding energy (60 meV), high mechanical and thermal stabilities, and good electrical conductivity. Therefore, ZnO thin films are intensively investigated and applied in solar cells, piezoelectrical devices, gas and biological sensors, catalysts, and high-efficiency short-wavelength optoelectronic nanodevices. To further enhance the properties of ZnO, researchers have been synthesizing ZnO films doped with aluminum or indium. Al doped ZnO (AZO) thin films have been highly developed featuring non-toxicity, low material cost, good thermal stability, high optical transmittance, and good electrical conductivity. [1, 2, 3] Many techniques have been used to deposit AZO thin films currently, such as sol gel processing, magnetron sputtering, pulsed laser deposition (PLD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Among these film deposition methods, ALD has been extensively investigated for the deposition of thin films of metals, alloys, semiconductors, and oxides. Compared with other techniques, ALD is considered as a novel technique for the deposition of AZO films due to its characteristic feature of self-limiting surface saturating reactions in each ALD cycle. ALD technology consequently and accurately controls the layer thickness with unprecedented atomic level precision, as well as the stoichiometry, composition, uniformity of large areas and maintains excellent conformity over complex surface nanostructures. The other advantage of ALD technology is to introduce each ALD chemical precursor sequentially separated by time to react on the surface of the structure. The concentration of dopant in the ZnO films can be precisely controlled by the number of ALD cycles, so that the physical properties of AZO films, such as carrier density and conductivity, can be adjusted to meet the requirements of different applications. In this study, a Savannah 100 cross-flow thermal ALD reactor was used for the deposition of Al doped ZnO thin films. The precursors of aluminium, zinc and oxygen used in the ALD process for the synthesis of Al doped ZnO thin films were trimethylaluminium (TMA: Al2(CH3)6), diethylzinc (DEZ: (C2H5)2Zn) and DI water. The growth temperature of AZO thin films was maintained at 250 oC. The flow rate of N2, used as a carrier gas, was accurately controlled at 20 sccm. In order to deposit ALD AZO films with various percentages of aluminium, TMA cycles were introduced once in every 30 pulses of DEZ and H2O injection. After deposition, AZO films were annealed in air at 500 oC, 600 oC, and 700 oC for 30 min, respectively. X-ray diffraction (XRD) was performed to characterize the crystal structure of ALD ZnO and AZO films. Field emission scanning electron microscopy (FE-SEM) was used to inspect the morphology of AZO films before and after annealing. The surface roughness was analyzed by atomic force microscopy (AFM). The compositions of AZO thin films were analyzed by energy dispersive X-ray spectroscopy (EDS). The sheet resistivity of AZO films was determined by using four-point probe measurements. Raman spectroscopy and photoluminescence (PL) were used to investigate the properties and detect structures of ALD AZO films. The band gaps of AZO films prepared by the ALD process were analyzed from PL spectroscopy results. The materials property and defect structure of ALD AZO films were investigated by Raman spectroscopy. References: P. Genevée, F. Donsanti, G. Renou, D. Lincot, Applied Surface Science 264, 464 (2013) G. Luka, T. A. Krajewski, B. S. Witkowski, G. Wisz, I. S. Virt, E. Guziewicz, M. Godlewski, J. Mater. Sci: Mater. Electron 22, 1810 (2011) J. W. Elam, D. Routkevitch, S. M. George, Journal of The Electrochemical Society, 150 (6) G339 (2003). Figure 1

With the emergence of various 3-D integration techniques, wafer bonding technology has experienced renewed interest. Decades of relentless device scaling leading to today’s state-of-the-art nanotechnology have ultimately focused on the third dimension for stacking of device layers. Temporary bonding is also of interest for the integration of dissimilar materials in device structures, which cannot be achieved by epitaxial growth techniques alone when the lattice mismatch between the dissimilar materials is too large. Recently lift-off resists (LOR) based on polydimethylglutarimide (PMGI) have been found to be especially suitable for film exfoliation and layer transfer of 2D materials by temporary bonding [1]. For the experimental preparation the 2-inch diameter Si wafers were cleaned with Standard Clean 1 (H2O:NH4OH:H2O2=5:1:1) before spin coating the Si wafers with polydimethylglutarimide LOR resist at an optimized spin speed of 2000 rpm. This was followed by a pre-bake process at 160ºC for 5 min in order to evaporate the cyclopentanone solvent with a boiling point of 131ºC. In the last process step two LOR coated Si wafers were bonded face to face via the LOR resist in an EVG®501 Wafer Bonding Systemin a vacuum of 10-3 Pa and at a temperature of 250ºC. The EVG®501 Wafer Bonding Systemis capable of thermo-compression bonding with up to 10 kN force. In this study we report on Thermal Gravimetric Analysis (TGA) which is widely applied on thermoplastic polymeric materials in order to elucidate chemical phenomena such as decomposition and mass loss, which also occur during thermal compression bonding of Silicon wafer pairs coated with spin-on LOR resist. From TGA data (Figure 1), the LOR precursor solution lost 93% of its original mass starting at 100˚C because of solvent vaporization. The LOR resist exhibits a glass transition point (Tg) of 180-190 ºC, which aids the wafer bonding process at 250ºC by rendering the resist softer and initiating viscous flow for surface planarization. The final 7% of resist mass was lost started at around 281˚C due to thermal decomposition of PMGI. The functional groups of polydimethylglutarimide based Lift Off Resist (LOR) layers were studied before wafer bonding and after wafer compression bonding by attenuated total reflection infrared (ATR-IR) spectroscopy (Figure 2). All functional groups before and after bonding via the LOR layers at 250 ºC were identical, except for the disappearance of the two bands at 3188 and 3088 cm-1after thermal compression bonding. The disappearance of these two bands, which are associated with the N–H group, is interpreted as a result of cross linking of polymers. This cross linking of polymer chains is the chemical process that enables the actual wafer bonding across the two joined polydimethylglutarimide resist interfaces. References: [1] T. Matsumae, A. D. Koehler, D. Greenlee, T. J. Anderson, H. Baumgart, G. G. Jernigan, K. D. Hobart and F. J. Kub, ECS Journal of Solid State Science and Technology, 4 (7) P1-P5 (2015). Figure 1

Two-dimensional layered transition metal dichalcogenides, such as MoS2, WSe2 and MoSe2 have received a lot of attention recently due to their promising unique thermal, mechanical, electrical, optical properties. Tungsten Diselenide (WSe2), one of the transition metal dichalcogenides of interest for 2-D electronic systems, exhibits not only good thermal stability and high melting point, but also excellent optical and electrical properties. WSe2 is a semiconductor with a bandgap which could be used for the fabrication of solar cells and LEDs of various colors [1, 2]. Many techniques have been developed for synthesis of WSe2 films on different substrates in recent years, such as sold state reaction, elctrodepositon, RF-magnetron sputtering, electrodepostion, pulsed laser depostion, chemical vapor depositon. However, there are very few references that report atomic layer deposition (ALD) results of WSe2 films. This technique exhibits self-limiting surface reactions, which means accidental overdosing of precursors does not result in increased film deposition on the substrate surface. This self-terminating character is able to accurately control thickness and composition of ultra thin films and achieves uniformity, conformality and even monolayers of transition metal dichalcogenides. Here we report on a large-area synthesis of WSe2 films on native oxide covered and hydroxyl terminated Si substrates by using the Savannah 100 ALD system from Ultratech/Cambridge Nanotech. Tungsten hexacarbonyl (W(CO)6) and (trimethylsilyl) selenide ((Me3Si)2Se) are employed as the chemical ALD precursors for Tungsten and selenium, respectively. Generally 20 sccm N2 was used as a carrier gas for the precursors. The growth temperature was set at 275, 300 and 325oC. The crystal structure and chemical composition of WSe2 films were identified by using X-ray diffraction (XRD) and energy dispersive X-ray spectroscopy (EDS). The film morphology was characterized by field emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM). The optical property was analyzed by Raman spectroscopy and photoluminescence (PL) spectroscopy. The strong Raman scattering of in-plane E1 2g and out-of-plane A1g vibration modes, and the dominant PL of direct transition from Kc to Kv and indirect transition from Λc to Γv with absence of Kc to Γv are typical optical spectra of layered WSe2. The reduction of out-of-plane vibration mode and the absence of PL from indirect transition provide the evidence of fewer layer WSe2. References: H. Wang, D. Kong, P. Johanes, J. J. Cha, G. Zheng, K. Yan, N. Liu, and Y. Cui, Nano Lett. 13, 3426 (2013). C. Huang, S. Wu, A. M. Sanchez, J. J. P. Peters, R. Beanland, J. S. Ross, P. Rivera, W. Yao, D. H. Cobden and X. Xu, Nature materials 13, 1096 (2014). Figure 1

Tungsten trioxide (WO3) thin films are extensively investigated for their remarkable semiconducting properties in electrochromics, microelectrics, selective catalysts, solar cells, gas-sensors and environmental engineering. In addition, WO3 has been particularly developed for electrochromic applications, such as smart windows for green buildings and airplanes, rear mirrors in automobiles, displays, and electro-devices.WO3 thin films have been fabricated by various methods, including physical vapor depostion (PVD), pulsed vapor deposition (PLD), RF magnetron sputtering deposition, and electrodeposition [1, 2]. Atomic layer deposition (ALD) is a novel process to synthesize variaous thin films, where the sequential alternating vapor pulses of chemical precursors are introduced into the ALD reaction chamber, one at a time. Each precursor pulse was separated by inert gas, such as Ar or N2. The excess precursors and reaction by-products were evacuated by vacuum pump from the ALD reaction chamber. The precursor is fully reacted with only one monoatomic layer on the reacting surface through a surface saturating self-terminationg process. Therefore, the ALD technique produces extremely uniform and conformal films in atomic level thickness. In general ALD has been shown to be able to generate reproducible and well-defined thin films of binary oxides, nitrides, and sulfides. In recent years ALD has been used to deposit pure elemental metals, new types of ternary and quarternary materials. Presently only a few processes have been reported on the synthesis of WO3 films by atomic layer deposition (ALD) so far. ALD WO3 thin films have been deposited using WF6 and H2O as precursors. WO3 films have also been deposited by ALD using tungsten hexacarbonyl (W(CO)6) and ozone as reactant precursors for tungsten and oxygen. In this work, we report on the synthesis of WO3 thin films on Si and quartz substrates by thermal ALD using a cross-flow reactor, with W(CO)6 and DI water as the chemical ALD precursors for tungsten and oxygen, respectively. This was followed by 600 oC furnace annealing in regular atmosphere. Characterization of WO3 thin films has been performed using X-ray diffraction (XRD), field emission scanning electron microscopy (FE-SEM), atomic force microscopy (AFM), energy-dispersive X-ray spectroscopy (EDX), UV-VIS-NIR spectrometer, Raman spectroscopy (RS). Figure 1 shows the XRD pattern of the ALD WO3 samples obtained after furnace annealing at 600 oC under atmospheric conditions. All the diffraction peaks can be indexed into the monoclinic structure of the WO3 phase [space group: P21/n (14)], which is consistent with PDF 83-0950. References: J. Malm, T. Sajavaara, and M. Karppinen, Chem. Vap. Deposition 18, 245 (2012). P. Tägtström, P. Mårtensson, U. Jansson, and J.-O. Carlsson, J. Electrochem. Soc. 146, 3139 (1999). Figure 1

Summary form only given. Recent state-of-the-art graphite strip heater ZMR wafers were examined by nondestructive diagnostic tools especially suited for the characterization of very thin Si films. In particular, glancing angle reflection X-ray topography, which revealed slip dislocation networks in the recrystallized superficial Si film, was used. It was found that the dense orthogonal network of dislocations is aligned along and superimposed on the subboundaries. According to TEM analysis the dislocation density ranges between 10/sup 7//cm/sup 2/ to 10/sup 8//cm/sup 2/ maximum. This orthogonal dislocation network has never been observed before by preferential chemical defect etching because the 0.5 mu m ZMR Si films are too thin to develop detectable each pits. As a further evaluation, transmission electron microscopy (TEM) was applied to selective areas of ZMR wafers. TEM analysis of these films showed orthogonal rows of dislocation clusters aligned along the directions. >

Large interfacial voids in bonding and etch-back silicon-on-insulator (BESOI) are discussed. After wafer contacting, the presence of several large interfacial voids is observed. High-resolution X-ray topographs confirm either foreign particles or epitaxial spikes in the center region of voids as the reason for nonbonding. The voids at the bonding interface contain trapped air pockets, which are under pressure. In general, as a result the entire area covered by the voids is lost to the SOI film due to cracking and delamination during the etch-back procedure. In order to investigate the lattice damage distribution and the strain related to it, elastic light scattering experiments were performed. The findings of local networks of elastic distortion are an indication of insufficient wafer flatness and surface finish. BESOI wafers were examined again after they had been subjected to the 30-min high-temperature polymerization bonding step at 1050 degrees C. The areas of the voids that had been free of extended defects following the wafer contracting step then exhibited a dense network of misfit dislocations. During thermal annealing at 1050 degrees C the stresses at the perimeter of the voids and at the site of particulate contamination increased to the point where they exceeded the critical resolved shear stress of silicon and dislocations were nucleated. >

Summary form only given. Recent improvements have rendered SIMOX (separation by implanted oxygen) material suitable for direct fabrication of radiation-hard and high-performance CMOS devices in the superficial Si film. A persistent problem is the presence of dislocations with undesirably high densities. These residual dislocations are attributed to the vast amounts of Si point defects that are generated in the collision cascades during the high-dose oxygen implantation. By careful optimization of the implant conditions the dislocation content has been reduced by several orders of magnitude to less than 10/sup 5/ cm/sup -2/. For this low-dislocation-content SIMOX material, the superficial Si film exhibits ordering of the oxide precipitates. In the as-implanted structure the dislocations are confined to the lower part of the superficial Si film, where no oxide precipitate ordering occurred. Precipitate ordering and silicon point defects have been shown to play an important role in the establishment of the final microstructure during oxygen implantation. >

The recombination properties of minority carriers determine the basic electronic properties of SOI materials and control the performance of a variety of SOI devices. Knowledge of the minority carrier recombination characteristics and its correlation to residual defect density is important for the evaluation of SOI technologies with varying degrees of crystal lattice imperfection. In this work we first describe a technique based on a flying spot laser scan microscope for the measurement of minority carrier diffusion length, L, and lifetime, /spl tau/, in SOI high voltage diodes. In our experiment, laser light of 633 nm wavelength is absorbed in the Si material through the generation of electron-hole pairs which, if generated in the depletion region, are separated by the high local field to give rise to a photocurrent that can be measured. >

The dependence of avalanche breakdown voltage on the drift region length and buried oxide thickness of thin silicon-on-insulator (SOI) LDMOS transistors is reported. An ideal relationship between breakdown voltage and drift length is derived. Experimental SOI LDMOS transistors with near ideal breakdown voltages in the short-drift-length regime have been realized. Specifically, 380 V was achieved in a drift length of 20 mu m. Thin buried oxides are shown to be a major cause of deviation from this ideal. Experimental results verify this finding. An 860-V LDMOS transistor made in a 0.2 mu m-thick SOI layer is reported. >

The possible advantages of an SOI (silicon-on-insulator) RESURF (reduced surface electric field) device are explored with an idealized lateral diode structure consisting of a P/sup +/ diffusion into an N-silicon-on-insulator film, supported by an N/sup +/ silicon substrate. An optimized structure is shown to have a uniform lateral electric field and a vanishing vertical electric field along the top surface of the depletion region. An analytical model based on ionization integrals indicates that, for very thin SOI, the breakdown voltage increases with decreasing SOI thickness. Two-dimensional numerical breakdown simulations also support this finding. Experimentally, breakdown voltages in excess of 700 V have been demonstrated on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers, in excellent agreement with theory. An obvious advantage of this concept lies in the integration of high-voltage devices with high-performance SOI CMOS circuits on a single chip. >

Metal-Oxide-Semiconductor (MOS) capacitors with Bi2Te3 thin film sandwiched and embedded inside the oxide layer have been fabricated and studied. The capacitors exhibit ferroelectric-like hysteresis which is a result of the robust, reversible polarization of the Bi2Te3 thin film while the gate voltage sweeps. The temperature-dependent capacitance measurement indicates that the activation energy is about 0.33 eV for separating the electron and hole pairs in the bulk of Bi2Te3, and driving them to either the top or bottom surface of the thin film. Because of the fast polarization speed, potentially excellent endurance, and the complementary metal–oxide–semiconductor compatibility, the Bi2Te3 embedded MOS structures are very interesting for memory application.

ZnO is a transparent semiconductor with a wide and direct band gape of 3.37 eV, large excitonic binding energy of ~60 meV, high mechanical and thermal stabilities, and good electrical conductivity. Therefore, ZnO based materials are extensively investigated in spintronics, gas and biological sensors, solar cells, catalysts, electronics, piezoelectric devices and high-efficiency short-wavelength optoelectronic nanodevices. In solar cell application, especially Al doped ZnO (AZO) thin films have been extensively developed and investigated due to their low cost, high thermal stability, high optical transparency and high conductivity [1, 2 , 3]. Several methods have been applied to deposit ZnO thin films in the past, such as sol gel spin coating, magnetron sputtering, pulsed laser deposition (PLD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Among these, ALD is considered as a novel technique to deposit ZnO thin films, because it possesses self-limiting surface reactions in each ALD cycle, which consequently control the layer thickness with unprecedented atomic level precision, stoichiometry, composition, uniformity of large area and maintain excellent conformity of complex nanostructures. In addition, ALD process is able to introduce separately each precursor to react on the surface of the structure. The concentration of dopant in the ZnO films can be precisely controlled by the number of ALD cycles, so that the physical properties of AZO films, such as carrier density and conductivity, can be adjusted to meet the requirements of different applications. In this study, Al doped ZnO thin films were deposited by the ALD technique with trimethylaluminium (TMA), diethylzinc (DEZ) and water vapor as aluminium, zinc and oxygen precursors, respectively. The films were grown in Savannah 100 cross-flow thermal ALD reactor. The growth temperature was maintained at 250 oC during the reaction. N2 was used as a carrier gas with a flow rate of 20 sccm. The ALD AZO films with various Al doping level were prepared by introducing TMA cycles once in every 30 pulses of DEZ and H2O injection. The structural, optical and electrical properties of the AZO films prepared by using ALD processes were investigated. The crystal structure of ZnO was analyzed by X-ray diffraction (XRD). The AZO film surface morphology was inspected using a field emission scanning electron microscopy (FE-SEM). The surface roughness was analyzed by atomic force microscopy (AFM). The sheet resistivity of AZO films was determined by using four-point probe measurements. The optical reflection was carried out by UV-VIS-NIR spectrometer. References: P. Genevée, F. Donsanti, G. Renou, D. Lincot, Applied Surface Science 264, 464 (2013) G. Luka, T. A. Krajewski, B. S. Witkowski, G. Wisz, I. S. Virt, E. Guziewicz, M. Godlewski, J. Mater. Sci: Mater. Electron 22, 1810 (2011) J. W. Elam, D. Routkevitch, S. M. George, Journal of The Electrochemical Society, 150 (6) G339 (2003).

High demands for improved performance, better power consumption, and miniaturized devices prompted the migration to SOI technology. SOI fabrication process helps in achieving greater performance and offers less power consumption compared to the Bulk Si Process. In SOI fabrication technology, transistors are built on a Si layer grown on SiO2 (145 nm) insulating layer. The SOI is fabricated using the SMART CUT wafer bonding and layer splitting technology. The strained Si on insulator (sSOI) technology has recently been developed for high mobility channel devices [1-3]. Biaxial tensile strained Si layers grown on SiGe have attracted great attention for high performance CMOS devices. Strain engineering for mobility enhancement is an attractive option to improve CMOS device performance by introducing lattice strain into the Si channel. Epitaxial Si1-xGex and most recently Ge-free bi-axially strained sSOI are among the leading candidates for higher mobility channel material. In this paper, we have analyzed how the fabrication of very thin single crystal Si device films by wafer bonding and SMART CUTTM film exfoliation technique is affecting their nanomechanical properties in comparison to bulk Si. Although both the handle wafer and the bonded thin device layer are single crystal Si, it turns out that their nanomechanical properties differ considerably. Using nanoindentation, we measured the properties of (SOI-88nm) and bi-axially tensile strained Silicon-on-Insulator (sSOI 15, 70, and 100 nm) and benchmarked the results against bulk Si. The results of Figure 1 indicate that the hardness of these films vary significantly. The field emission scanning electron microscopy (FE-SEM) image of Figure 2 represents an sSOI film of 100 nm thick. References C. Mazure and A.J. Auberton-Herve, Proc. of 35th European Solid-State Device Research Conf. ESSDERC, p. 29 (2005) T. A. Langdo, M. T. Currie, Z.-Y. Cheng, J.G. Fiorenza, M. Erdtmann, G. Braithwaite, C.W. Leitz, C.J. Vineis, J. A. Carlin, A. Lochtefeld, M. T. Bulsara, I. Lauer, D.A. Antoniadis, M. Somerville, Solid-State Electronics, 48 , 1357 (2004). I. Cayrefourcq, A. Boussagol and G. Celler, in SiGe and Ge: Materials, Processing, and Devices , ECS Trans. 3, (7), 399 (2006)

Tungsten oxide (WO3) films exhibit interesting properties, making them useful in various thin-film applications, such as smart windows or flat-panel displays [1], in electrochromic devices [2], gas sensors [3], and photocatalysis/photoconductivity [4]. Many of these applications are strongly dependent on tungsten oxide’s crystal morphology, microstructure, and mechanical properties. WO3 films of 200 and 600 ALD cycles were deposited on p-type Si (100) substrate using atomic layer deposition (ALD) technique and annealed at different temperatures. The 600 ALD cycle samples were annealed at 150, 250, and 300 °C, whereas the 200 ALD cycles sample was annealed at 250 °C. We tested these films for structural, surface morphology, and nanomechanical properties using nanoindentation. The structural and surface properties were explored using X-ray diffraction (XRD), scanning electron microscopy (SEM) and atomic force microscopy (AFM). We discuss the influence of the deposition technique on the structure and properties of the films citing the superiority of the ALD technique that is particularly used in the fabrication of the films that are presented in this study. The results in Figures 1 and 2 depict no significant difference in the hardness among the different films and annealing temperatures. The SEM image of Figure 3 shows radial cracks in the 600 ALD cycles annealed sample at 150 ˚C as an example. All other samples depict similar radial cracks. References: C.-G. Granqvist, Handbook of Inorganic Electrochromic Materials, Elsevier, Amsterdam (1995). K. Bange, Sol. Energy Mater. Sol. Cells 58 (1999) 1. M. Boulova, A. Gaskov, G. Lacazeau, Sens. Actuators, B, Chem. 81 (2001) 99. F.B. Li, G.B. Gu, X.J. Li, H.F.Wan, Acta Phys. Chim. Sin. 16 (2000) 997.

Titanium oxide (TiO2) materials experienced increased attention and growth because of their use as electrode material in lithium rechargeable batteries and they also offer excellent photocatalytic properties due to their stability, nontoxicity, and superb photo catalytic activity. However their absorption of the visible light is restricted due to their wide band gap (3.2 eV). One way of improving their absorption capabilities to the visible light is by doping such wide band gaps semiconducting oxides. The N-doped TiO2 films prepared by sputtering showed noticeable visible light absorption at wavelengths of less than 500 nm due to the bandgap narrowing by mixing of N 2p states with O 2p states [1-3]. Many of the properties in these applications are strongly dependent on titanium oxide’s crystal morphology, surface area, and mechanical properties. TiO2 films of 200, 300, and 500, ALD cycles were deposited on p-type Si (100) substrates using Atomic layer deposition (ALD) technology. These films have been tested for structural, surface morphology, and nanomechanical properties using nanoindentation. The structural and surface properties will be explored using X-ray diffraction (XRD), scanning electron microscopy (SEM) and atomic force microscopy (AFM). We will discuss the influence of the deposition technique on the structure and properties of the films citing the superiority of the ALD technique that is particularly used in the fabrication of the films that are presented in this study. A field emission scanning electron microscopy (FE-SEM) image is shown in Figure 1. References 1- R. Asahi, T. Morikawa, T. Ohwaki, K. Aoki, and Y. Taga, Science, 293, 269 (2001). 2- J. Li, Y. Qin, C. Jin, Y. Li, D. Shi, L. Schmidt-Mende, L. H. Gan, and J. H. Yang,bNanoscale, 5, 5009 (2013). 3- C. X. Feng,G. Q.Xu, J. Lv,Q. M. Huang, Z. X. Zheng, andY. C.Wu, J. Electrochem. Soc, 160, H727 (2013).

Thermoelectric materials have attracted much attention for their potential in conversion between heat and electricity and consequently could be used for heating and cooling systems. The efficiency of a thermoelectric material is expressed by the dimensionless thermoelectric figure of merit, ZT = S2σT/ k, where S is the Seebeck coefficient, σ is the electrical conductivity, and kis the thermal conductivity [1]. Previous work demonstrated alloying was used to decrease the lattice thermal conductivity and thus to increase ZT owning to mass difference enhanced phonon scattering. In order to further progress in the development and commercialization of the next generation of thermoelectric devices it is necessary to enhance the ZT value. Most recently research focused on low dimensional nanostructures, including quantum wells, quantum dots, superlattice, quantum wires and nanolaminates to improve ZT. In superlattice structures, reduced lattice thermal conductivity is mainly due to the phonon scattering at multiple interface boundaries. Significant efforts have been made to investigate the IV-VI semiconducting lead chalcogenides, such as PbTe and PbSe due to their high figure of merit, good chemical stability, low vapor pressure and high melting point. Therefore they are promising thermoelectric materials for intermediate temperature applications ranging from 600 to 800 K. PbTe and PbSe films have been deposited by different techniques, such as pulsed laser deposition (PLD), metal-organic chemical vapor deposition (MO-CVD), magnetron sputtering, molecular beam epitaxy (MBE) and atomic layer deposition (ALD). Among these, ALD is considered as a novel and competitive method to deposit PbTe/PbSe nanolaminate structures. The ALD is a self-limiting atomic layer reaction in each ALD cycle introduce. It can precisely control the film layer thickness, stoichiometry, composition, uniformity, and sharp interface. ALD also can be used to deposit conformal films onto very complex structures. It is possible to generate the reproducible and well-defined nanolaminate structures. Furthermore, the deposition temperature of ALD is rather low in comparison with other growth techniques. In this work we report on the successful synthesis of multiple PbTe/PbSeTe nanolaminates on silicon substrates by a thermal ALD system. In this new nanolaminate structure a very thin layer of the PbSeTe ternary compound is formed by nucleation of PbSe quantum dots between binary PbTe layers, which is followed by an annealing process step. It is noted that the formation of the PbSe quantum dots is facilitated the prevailing Volmer-Weber island growth mode. Lead bis(2,2,6,6-tetramethyl-3,5-heptanedionato) (Pb(C11H19O2)2), (trimethylsilyl) telluride ((Me3Si)2Te) and (trimethylsilyl) selenide ((Me3Si)2Se) were employed as the chemical ALD precursors for lead, telluride and selenide, respectively. 20 sccm N2 was used as a carrier gas to transport the chemical precursors into the ALD reaction chamber. The ALD growth temperature was 170 oC. The solid lead precursor was volatilized at a temperature of 140 oC, the liquid Te precursor required heating to 40 oC, and the liquid Se precursor was kept at room temperature. The chamber base pressure was kept at 30 mTorr. Several physical characterization techniques have been employed to determine the ALD nanolaminate formation. The crystal structure was analyzed by X-ray diffraction (XRD). The film morphology and structure of the products were determined by field emission scanning electron microscopy (FE-SEM) and high resolution transmission electron microscopy (HR-TEM).The surface roughness was analyzed by atomic force microscopy (AFM). The analysis of the composition and stoichiometry of the ternary and binary layers were carried out by X-ray photoelectron spectroscopy (XPS) and Energy dispersive X-ray spectroscopy (EDS). References: K. Zhang, A. D. Ramalingom Pillai, D. Nminibapiel, M. Tangirala, V. S Chakravadhanula, C. Kübelc, H. Baumgart, V. Kochergin, ECS Trans., 58, 10, 131 (2013).

The IV-VI lead chalcogenides are considered as prospective thermoelectric materials which have their potential applications in green renewable energy by waste heat recovery and infrared devices. Among these materials, PbSe demonstrates a remarkable thermoelectric performance, The thermoelectric figure of merit ZT exceeds 1 for both n-type and p-type PbSe at high temperature. ZT is defined as ZT=σS2T/κ, where S is the Seebeck coefficient, σ is the electrical conductivity, and κ is the thermal conductivity, respectively. In addition, Se element is more abandant and less costly than Te which is a scarce element [1]. PbSe thin films on Si substrates have been synthesized by various methods. However, a careful literature search reveals, there are few if any reports on the synthesis of PbSe thin films by atomic layer deposition (ALD). The ALD technique exhibits self-limiting surface reactions in each ALD cycle which consequently results in precise layer thickness control, stoichiometry, composition, uniformity of large area on the substrate. ALD also can be used to deposit conformal film onto very complex substrates or nano-porous template surfaces. This is the one advantageous property of ALD which renders it more competitive and promising in porous template nano-structures. In contrast, magnetron sputtering and PLD cannot be used to coat complex 3D structures with PbSe. Furthermore, the growth temperature of ALD is rather low in comparison with other fabrication processes. In this work we report on the successful synthesis of multiple PbSe thin films on silicon substrates and inside microporous Si templates by thermal ALD, using lead bis(2,2,6,6-tetramethyl-3,5-heptanedionato) (Pb(C11H19O2)2) and (trimethylsilyl) selenide ((Me3Si)2Se) as the chemical ALD precursors for lead and selenide, respectively. The repetitive structure of nano-porous Si templates offers an additional degree of periodicity in the quest for high ZT thermoelectric films. The XRD and FE-SEM results reveal that the Lead selenide thin films are polycrystalline at deposition temperatures of 170 °C based on Volmer Weber Island growth mode and have characteristic FCC rock-salt crystal structure as shown in Figure (1), (2) and (3). References: H. Wang, Z. M. Gibbs, Y. Takigawa, G. J. Snyder, Energy Environ. Sci., 7, 804 (2014).

Special interest continues to grow in the achievement of fundamental understanding of nanostructured assemblies that potentially open new horizons for creating novel energy conversion systems. When one-dimensional (1D) nanostructures based on nanotubes or nanowires are integrated into the assembly of well-ordered architectures, they exhibit a variety of tunable optical and electrical properties that can offer exciting opportunities in creating the next generation of solar cells. Recently, particular focus has been placed on nanostructured solar cells that can tolerate a higher level of defects and impurities. To realize their potential, semiconducting 1D nanostructures that serve as conducting scaffolding and absorbing layers should be controlled in a predictable and precise fashion in order to efficiently tailor photon harvesting and transport charge carriers [1,2,3]. While the past several years have witnessed great progress in the area of nanotechnologies, structural dimensions (height, thickness, and spacing) and spatial alignment of 1D nanostructures have not been shown to be selectively controllable with high precision [4]. Accordingly, current nanofabrication technologies allowing for precise control over the assembly of 1D nanostructures yielding optimal architectures of nanostructured solar cells are still in their infancy. Hence, a scarcity of ideal platforms consisting of highly-controlled nanostructure assemblies makes use of non-ideal systems, thereby preventing systematic studies of energy conversion processes within the cell and at the heterojunction interfaces. Therefore, we provide novel approaches to investigate material synthesis for highly arrayed nanostructured systems for solar cell applications. We developed a new process technology that can make full use of the porous template while structural dimensions such as spacing and thickness of nanostructures are also precisely controlled. Particularly, our technologies enable highly arrayed nanostructures having various material combinations such as insulators, semiconductors, and/or metals. In addition, they allow for large-scale production of such highly arrayed nanostructures. Currently, we are integrating highly arrayed nanostructures into glass or plastic substrates. Our nanofabrication technologies will provide a new class of highly arrayed, multi-walled nanostructures suitable for many optoelectronic applications including new-generation solar cells. References Z. Fan, H. Razavi, J. W. Do, A. Moriwaki, O. Ergen, Y. L. Chuen, P.W. Leu, J.C. Ho, T. Takahashi, L. A. Reichertz, S. Neale, K. Yu, M. Wu, J.W. Ager, and A. Javey, Nat. Mater. 8, 648 (2009) L. Sun, S.Zhang, X. Sun, and X. He, J. Nanosci. Nanotechnol., 10, 4551 (2010) V. Thavasi, V. Renugopalakrishnan, R. Jose, and S. Ramakrishna, Mater. Sci. Eng. R. 63, 81(2009) A. Belaidi, Th. Dittrich, D. Kieven, J. Tornow, K. Schwarzburg, M. Kunst, N. Allsop, M.-Ch. Lux-Steiner, and S. Gavrilov, Sol. Energy Mater. Sol. Cells, 93, 10336 (2009)

Direct characterization of the capacitance and interface states is very important for understanding the electronic properties of a nanowire transistor. However, the capacitance of a single nanowire is too small to precisely measure. In this work we have fabricated metal-oxide-semiconductor capacitors based on a large array of self-assembled Si nanowires. The capacitance and conductance of the nanowire array capacitors are directly measured and the interface state profile is determined by using the conductance method. We demonstrate that the nanowire array capacitor is an effective platform for studying the electronic properties of nanoscale interfaces. This approach provides a useful and efficient metrology for the study of the physics and device properties of nanoscale metal-oxide-semiconductor structures.

The fabrication of thermoelectric nanolaminate structures of alternating Bi2Te3 and Sb2Te3 ALD layers for thermoelectric application is reported. Trimethylsilyl telluride ((Me3Si)2Te), bismuth trichloride (BiCl3) and antimony trichloride (SbCl3) were utilized as chemical ALD precursors for tellurium, bismuth and antimony, respectively. The results of field emission scanning electron microscopy (FE-SEM) indicate that both metal tellurides exhibit the prevalent Volmer-Weber island growth mechanism with characteristic hexagonal crystallites. High resolution TEM X-section analysis reveals localized epitaxial growth of alternating ALD Bi2Te3 and Sb2Te3 layers within the large islands.

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