Role of surface morphology in wafer bonding

The strain patterns detected by x‐ray topography in wafers bonded for silicon‐on‐insulator (SOI) technology were found related to the flatness nonuniformity of the original wafers. Local stresses due to the bonding process are estimated to be about 1×108 dynes/cm2. The stress is reduced about 100 times for the thin (0.5 μm) SOI films. Most of the wafer deformation occurs during room temperature mating of the wafers. The deformation is purely elastic even at 1200 °C. The magnitude of the stress appears insignificant for complimentary metal‐oxide‐semiconductor devices performance.