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We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from $1.6 \times 10^{18}$ cm−3 to $4.8 \times 10^{19}$ cm−3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGaAs conduction band is experimentally manifested. It is also revealed that the contact resistivity ( $\rho _{\text {c}}$ ) of Mo/n-InGaAs contact clearly outperforms after annealing. However, for the first time, we demonstrate that the Mo/Pd (2nm)/n-InGaAs contact can achieve a $\rho _{\text {c}}~35$ % and 20% lower than a single Mo/n-InGaAs contact after annealing at 400 °C and 450 °C for 1min, respectively.

Barium titanate (BaTiO3 or BTO) is a perovskite structure material with interesting intrinsic properties, such as spontaneous ferroelectricity or electro-optical behavior, which strongly depend on thin film crystallinity. For such functional oxide systems, the pulsed-laser deposition (PLD) approach is one promising growth technique due to its precise stoichiometry control of the metals composing the perovskite crystal and higher oxygen environment compared to the classically used molecular beam epitaxy (MBE) approach. In this article, we demonstrate a BTO epitaxial layer by PLD onto an Si(001) substrate thanks to a thin pseudomorphic SrTiO3 buffer layer grown by MBE. In our study, the various investigated PLD parameters show strong impacts on the BTO polarization orientation. Hence, adjusting the growth conditions allows control of the polarization orientation, which is crucial for both electronic and optical applications. In addition, lattice parameter changes of BTO layers are investigated using x-ray diffraction and cross-sectional transmission electron microscopy, which evidenced a correlation between mismatch relaxation and oxygen growth pressure. Finally, with the analysis of BTO C– V curves, the polarization direction transition is demonstrated electrically. ispartof: Journal Of Applied Physics vol:128 issue:10 pages:104104-104104 status: published

Several approaches for growing III–V lasers on silicon were recently demonstrated. Most are not compatible with further integration, however, and rely on thick buffer layers and require special substrates. Recently, we demonstrated a novel approach for growing high quality InP without buffer on standard 001-silicon substrates using a selective growth process compatible with integration. Here we show high quality InGaAs layers can be grown on these InP-templates. High-resolution TEM analysis shows these layers are free of optically active defects. Contrary to InP, the InGaAs material exhibits strong photoluminescence for wavelengths relevant for integration with silicon photonics integrated circuits. Distributed feedback lasers were defined by etching a first order grating in the top surface of the device. Clear laser operation at a single wavelength with strong suppression of side modes was demonstrated. Compared to the previously demonstrated InP lasers 65% threshold reduction is observed. Demonstration ...

Two-dimensional transition metal dichalcogenide (TMD) semiconductors have risen as an important material class for novel nanoelectronic applications. Molybdenum disulfide (MoS2) is the most representative TMD compound due to its superior stability and attractive properties for (opto-) electronic devices. However, the synthesis of single-crystalline and functional MoS2 across large-area substrates remains crucial for its successful integration in semiconductor industry platforms. Therefore, this work focuses on the study of MoS2 epitaxy via two well-established industry-compatible synthesis methods, promising for the large-area and single-crystalline integration of van der Waals (vdW) materials. These methods are molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE) and have studied MoS2 quasi-vdW heteroepitaxy on reconstructed sapphire substrates and MoS2 vdW homoepitaxy on exfoliated MoS2 flakes. By examining the MoS2 structural properties using diffraction and spectroscopy techniques, the epitaxial relation and crystal quality are assessed, which reveals insights into the prevalence of inter- and intragrain defects such as grain boundaries and sulfur vacancies. The MBE method yields superior epitaxial MoS2 registry on both sapphire and MoS2 surfaces as compared to MOVPE, although inferior defectivity arises from the typical lower MBE growth temperature and chalcogen partial pressure. Moreover, both synthesis methods generate high densities of twinned MoS2 grain boundaries, which hamper defect-free integration. As a result, this challenging integration might become an important bottleneck for industrial TMD-based applications with a low tolerance for material defects.

Extracting plasmon-induced hot carriers over a metal-semiconductor Schottky barrier enables photodetection below the semiconductor bandgap energy. However, interfacial carrier recombination hinders the efficiency and stability of this process, severely limiting its implementation in telecommunication. This study proposes and demonstrates the use of epitaxially grown lattice-matched SrTiO3 for interfacial passivation of silicon-based plasmonic Schottky devices. The devices are activated by an electrical soft-breakdown of the interfacial SrTiO3 layer, resulting in reproducible rectified Schottky characteristics. The transition to a low resistance state of the SrTiO3 layer boosts the extraction efficiency of hot holes upon resonant plasmonic excitation, giving rise to a two orders of magnitude higher photocurrent compared to devices with a native oxide layer. Photoresponse, tunability, and barrier height studies under reverse biases as high as 100 V present superior stability with the incorporation of the SrTiO3 layer. The investigation paves the way toward plasmon-induced photodetection for practical applications including those under challenging operating conditions.

In this presentation we will report on our recent work on new materials that can be monolithically integrated on high-index contrast silicon or silicon nitride photonic ICs to enhance their functionality. This includes graphene and other 2D-materials for realizing compact electro-absorption modulators and non-linear devices, ferroelectric materials for realizing phase modulators and adiabatic couplers for realizing bistable switches.

In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques.In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques.

On-chip optical interconnects still miss a high-performance laser monolithically integrated on silicon. Here, we demonstrate a silicon-integrated InP nanolaser that operates at room temperature with a low threshold of 1.69 pJ and a large spontaneous emission factor of 0.04. An epitaxial scheme to grow relatively thick InP nanowires on (001) silicon is developed. The zincblende/wurtzite crystal phase polytypism and the formed type II heterostructures are found to promote lasing over a wide wavelength range.

The effective passivation of germanium surfaces and interfaces has been claimed to be the key to a substantial progress in developing Ge-based microelectronic devices. This paper compares the currently most promising passivation routes, i.e. oxidation and sulfidation, focusing on the underlying atomic scale processes and highlighting similarities and discrepancies between both approaches. The effect of oxidation and sulfidation on electrically active defects is addressed, and the chemical and structural properties of the passivated surfaces are described in detail.

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

To design a high performance BaTiO3 (BTO)-integrated Si modulator, understanding how BTO domain orientations influence its electro-optical (EO) properties is crucial. The 100-nm-thick BTO films with c-oriented and a-oriented domains are obtained by exploiting various thickness of SrTiO3 buffer layers grown on Si(001) substrates. Then, the electro-optical behavior for 2 differently oriented samples is analyzed using spectroscopic ellipsometry.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

We will present our work on epitaxially grown III-V on silicon DFB laser arrays, including results of pure InP-based lasers emitting around 900nm and InGaAs-on-InP lasers emitting around 1300nm.

In the paper, we review our work on heterogeneous integration of InP photonic devices on silicon. We elaborate on two integration technologies that have been widely explored in the Photonics Research group, i.e. the relatively mature adhesive bonding based integration scheme and a newly demonstrated buffer-less epitaxial growth approach. Based on these techniques, we describe a broad range of photonic devices including mode-locked lasers, high speed directly modulated distributed feedback lasers, electro-absorption modulators, photodetectors, super-luminescent light emitting diodes, etc.

An imperative factor in adapting GeSn as the channel material in CMOS technology, is the gate-oxide stack. The performance of GeSn transistors is degraded due to the high density of traps at the oxide-semiconductor interface. Several oxide-gate stacks have been pursued, and a midgap Dit obtained using the ac conductance method, is found in literature. However, a detailed signature of oxide traps like capture cross-section, donor/acceptor behavior and profile in the bandgap, is not yet available. We investigate the transition region between stoichiometric insulators and strained GeSn epitaxially grown on virtual Ge substrates. Al2O3 is used as high-κ oxide and either Ge1-xSnxO2 or GeO2 as interfacial layer oxide. The interface trap density (Dit) profile in the lower half of the bandgap is measured using deep level transient spectroscopy, and the importance of this technique for small bandgap materials like GeSn, is explained. Our results provide evidence for two conclusions. First, an interface traps density of 1.7 × 10(13) cm(-2)eV(-1) close to the valence band edge (Ev + 0.024 eV) and a capture cross-section (σp) of 1.7 × 10(-18) cm(2) is revealed for GeSnO2. These traps are associated with donor states. Second, it is shown that interfacial layer passivation of GeSn using GeO2 reduces the Dit by 1 order of magnitude (2.6 × 10(12) cm(-2)eV(-1)), in comparison to GeSnO2. The results are cross-verified using conductance method and saturation photovoltage technique. The Dit difference is associated with the presence of oxidized (Sn(4+)) and elemental Sn in the interfacial layer oxide.

Germanium is considered to be a potential semiconductor to replace silicon in future high-performance microelectronic devices. Yet, when compared to Si, very little is known about the surface chemistry of Ge surfaces. In this article, we report on the oxygen adsorption on Ge(100)-(2 × 1) surfaces and the related changes in the density of surface states. In particular, the adsorption geometry is examined both in reciprocal- and real-space using reflection high-energy electron diffraction and scanning tunneling microscopy, respectively. Our findings reveal that the insertion of oxygen atoms into the Ge backbonds is not favored under the investigated reaction conditions, i.e., at a moderate O2 exposure. The O2-exposed surface exhibits a local (1 × 1) surface reconstruction, which implies that dimer bonds are destroyed upon oxygen adsorption. Surface states related to Ge dangling surface bonds present on the clean Ge(100) surface are found to be passivated. In addition, a high density of expelled substrate at...

The integration of higher carrier mobility materials to increase drive current capability in the next CMOS generations is required for device scaling. But a fundamental issue regarding the introduction of high-mobility III–V in CMOS is the electrical passivation of the interface with the high-κ gate dielectric. In this work, we show that in situ H2S surface treatment on GaAs(001) leads to a stable and reorganized oxide/III–V interface. The exposition of the GaAs surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. Finally, MOS capacitors are fabricated to extract interface state density over the band gap. These results highlight a promising re-interest in chalcogenide passivation of III–V surfaces for CMOS applications.

From electron internal photoemission and photoconductivity measurements at the (100)GaSb/Al"2O"3 interface, the top of the GaSb valence band is found to be 3.05+/-0.10eV below the bottom of the Al"2O"3 conduction band. This interface band alignment corresponds to conduction and valence band offsets of 2.3+/-0.10eV and 3.05+/-0.15eV, respectively, indicating that the valence band in GaSb lies energetically well above the valence band of In"xGa"1"-"xAs (0=

We will present the defect density at In0.53Ga0.47As and InP interfaces with ALD Al2O3 derived by use of the conductance method and from simulation of low frequency CV-curves. Consequences of the interface state distribution for MOS transistor device operation will be highlighted through 1-dimensional electrostatic simulations. The simulation results will be compared as much as possible to different state-of-the-art transistor results presented in literature.

Si and Se implantations have been systematically investigated in In"0"."5"3Ga"0"."4"7As. Different implant doses and various activation anneals with temperatures up to 700^oC have been examined. Raising Si implant dose from 1x10^1^4 to 1x10^1^5cm^-^2 was found to increase the active doping concentration by about a factor of two. As confirmed by Transmission Electron Microscopy (TEM) and electrical measurements, the rest of the implanted Si ions remain as defects in the crystal and degrade the mobility. It was also confirmed from Secondary Ion Mass Spectrometry (SIMS) that the Si diffusivity in InGaAs is negligible up to 700^oC implant activation anneal making Si a suitable option for the formation of shallow junctions in InGaAs. The activation efficiency, sheet resistance, carrier density and mobility data of 25keV Se and Si implanted InGaAs layers are also presented under various activation anneal temperatures.

© 2018 Author(s). In0.53Ga0.47As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In0.53Ga0.47As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum EC is assigned to the "localized" states of α 60° misfit dislocations; another broad electron trap with mean activation energies between EC- 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor KT by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at EV+ 0.42 ± 0.01 and EV+ 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (VGa/In3-/2-) and 60° β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects AsGa/In are discussed for n-type In0.53Ga0.47As. ispartof: JOURNAL OF APPLIED PHYSICS vol:124 issue:16 status: published

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nuc...

The use of Ge and III/V materials for future CMOS applications is investigated. Passivation of the Ge surface can be obtained by either GeO2 or a thin Si layer. Short channel Ge pMOS devices with low EOT are fabricated. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are investigated and the performance of inversion channel MOSFET's on In0.53Ga0.47As with ALD Al2O3 is discussed.

We will shortly review the basic physics of charge carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high temperature CV-measurements are necessary for GaAs MOS characterization. The mid-gap trapping states in GaAs have characteristic emission times of the order of 1000 seconds, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures fasten these emission times, which makes measurements of the mid-gap traps possible with standard CV-measurements. CV-characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2 and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to mid-gap energies, an electron trap peak close to mid-gap energies and an electron trap peak close to the conduction band.

The energy band alignment between Ge, HfO 2 and Al 2 O 3 was analyzed as influenced by passivating interlayers (ILs) of different composition (GeO 2 , Ge 3 N 4 , Si/SiO x ). From internal photoemission and photoconductivity experiments we found no IL-sensitive dipoles at the Ge/HfO 2 interfaces, the latter being universally characterized by conduction and valence band offsets of 2.1 and 3.0 eV, respectively. However, in the case of HfO 2 growth using H 2 O-based atomic layer deposition, the Ge oxide IL appears to have a narrower bandgap, 4.3 eV, than the 5.4–5.9 eV gap of bulk germania. Accordingly, formation of this IL yields significantly reduced barriers for hole and, particularly, electron injection from Ge into the insulator. Changing to a H-free process for HfO 2 and Al 2 O 3 deposition suppresses the formation of the narrow-gap Ge oxide.

In the paper, we elaborate our recent work on both monolithic (epitaxial growth) and heterogeneous (BCB bonding) integration techniques that enable integration of various IIIV lasers on silicon.

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

In this paper we show how new materials such as InP epitaxially grown on silicon, graphene and ferroelectric materials with strong electro-optic coefficient can be integrated with silicon waveguides and enhance the functionality of the silicon photonics platform.

Trap spectroscopy by charge injection and sensing method was applied to the In0.53Ga0.47As-Al2O3 system, yielding the spatial and energetic distribution of the traps inside the Al2O3 layer. The trap density inside the atomic-layer-deposited (ALD) Al2O3 layer was found to be significantly reduced by (NH4)2S treatment of the InGaAs surface prior to the Al2O3 deposition. Indium concentration inside the Al2O3 layer was found to be reduced once the InGaAs surface is (NH4)2S treated prior to the Al2O3 deposition as measured by time-of-flight secondary ion mass spectroscopy, indicating indium as a possible origin of the oxide traps. The results suggest a new mechanism for the sulfur action at the InGaAs surface, which might be responsible for the transistor performance improvements observed after ( NH4)2S passivation. This mechanism involves sulfur as an indium diffusion/segregation barrier stabilizing the InGaAs surface during the ALD Al2O3 deposition, lowering the oxide trap density. This, in turn, improves the electron mobility through a reduction in the Coulomb scattering of the carriers due to border traps and improves the device drive current.

We introduce an ac transconductance dispersion method (ACGD) to profile the oxide traps in an MOSFET without needing a body contact. The method extracts the spatial distribution of oxide traps from the frequency dependence of transconductance, which is attributed to charge trapping as modulated by an ac gate voltage. The results from this method have been verified by the use of the multifrequency charge pumping (MFCP) technique. In fact, this method complements the MFCP technique in terms of the trap depth that each method is capable of probing. We will demonstrate the method with InP passivated InGaAs substrates, along with electrically stressed Si N-MOSFETs.

Silicon does not emit light efficiently, therefore the integration of other light-emitting materials is highly demanded for silicon photonic integrated circuits. A number of integration approaches have been extensively explored in the past decade. Here, the most recent progress in this field is reviewed, covering the integration approaches of III-V-to-silicon bonding, transfer printing, epitaxial growth and the use of colloidal quantum dots. The basic approaches to create waveguide-coupled on-chip light sources for different application scenarios are discussed, both for silicon and silicon nitride based waveguides. A selection of recent representative device demonstrations is presented, including high speed DFB lasers, ultra-dense comb lasers, short (850nm) and long (2.3 mu m) wavelength lasers, wide-band LEDs, monolithic O-band lasers and micro-disk lasers operating in the visible. The challenges and opportunities of these approaches are discussed.

Monolithically integrating BaTiO3 on silicon substrates has attracted attention because of the wide spectrum of potential novel applications ranging from electronics to photonics. For optimal device performance, it is important to control the BaTiO3 domain orientation during thin film preparation. Here, we use molecular beam epitaxy to prepare crystalline BaTiO3 on Si(001) substrates using a SrTiO3 buffer layer. A systematic investigation is performed to understand how to control the BaTiO3 domain orientation through the thickness engineering of the SrTiO3 buffer layer and the BaTiO3 layer itself. This provides different possibilities for obtaining a given BaTiO3 orientation as desired for a specific device application.

Optical interconnects require efficient and flexible optical sources. This paper presents results on two technology platforms being developed for realizing these. Integration using wafer bonding technologies is well established now and the focus is on new device types including tunable lasers, multi-wavelength lasers and switching. As an alternative, we also started work on monolithic integration using heteroepitaxy directly on silicon. We here report recent results on low threshold nanowire lasers.

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, L g of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

First-principles investigations are used to study the formation of defects in III-V fins grown using the aspect ratio trapping technique. We show that, during the growth of the III-V, the formation of intermediate chemical states with the precursors leads to the creation of in-diffused Mg/Zn and Al 2 O 3 sub-oxide. Our prediction is consistent with the experimental observations. These defect formations could be at the origin of the degradation of the electrical reliability of III-V fin-shaped field-effect transistors and the cause of the increasing difficulties met in the fabrication of III-V fin.

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-? deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.

This paper gives an overview of measurement techniques to assess border traps in high-k gate dielectrics deposited on high-mobility channel materials, like Ge and InGaAs. A short description of the measurement principle and bulk oxide trap analysis will be provided for three methods, namely, low-frequency (1/f) noise, Deep-Level Transient Spectroscopy and AC transconductance dispersion. Practical application is illustrated either on metal-oxide-semiconductor capacitors or transistors, depending on the technique.

Silicon photonics holds the promise of converging electronics and photonics. The key component, a low-cost high-performance laser, is still missing however within this platform. Although novel solutions have been proposed to increase the light emission directly from silicon (or Ge), compared with their III-V counterparts, these solutions are still in their infancy. Recently, the epitaxial growth of III-Vs on silicon regained a wide interest. III-V nanowire growth has been widely investigated. However, most of the III-V nanowire lasers on silicon require a complex cleaving and transfer process, which make these devices not suitable for dense integration. In addition, the large cavity dimensions along the nanowire axis (several microns) hinder dense integration. Here, we present the first room-temperature operation of an ultra-short InP nanowire laser that is epitaxially grown on an exactly [001] oriented silicon substrate. The sub-micron sized laser cavity largely enhances the interaction of the lasing mode with the gain medium, and a large spontaneous emission factor has been obtained.

Due to energy-filtering by band-to-band quantum mechanical carrier tunneling, Tunnel FETs promise the possibility of steeper subthreshold swings (SS < 60 mV/dec) than MOSFETs. Even if the ideal material combination is still unclear, simulations show that for a confined channel (width We first present the pseudomorphic growth of n+InAs(Si)-p+GaSb(Si) Esaki diode on a (001) p+ GaSb substrate (ED1). We particularly show the influence of the InAs/GaSb interface nature on both structural and electrical quality. After choosing the right interface stoichiometry between InAs and GaSb, the growth of n+InAs(Si)-p+GaSb(Si) Esaki diode on GaAs is investigated (ED2). In here, 90° misfit dislocations (MDs) array at the GaSb/GaAs interface is used to accommodate the mismatch strain between GaSb and GaAs. After presenting the influence of the growth conditions on the MDs array formation, the electrical results of ED2 are compared to the ones of ED1. This learning is crucial to study the effect of dislocations on BTBT behavior in tunneling devices. In the last step, the integration of n+InAs(Si)-p+GaSb(Si) Esaki diode on (001) Si is presented (ED3) using a 300 mm GaAs on Si template grown by MOCVD. After presenting the detailed growth stack, we demonstrate a high quality n+InAs(Si)-p+GaSb(Si) growth on exactly oriented (001) Si substrate exhibiting a RMS surface roughness of 1.4 nm and a dislocation density (TD) of 9x107/cm2 , as determined by XRD analysis. In summary, this study gives a broad insight on the influence of different types of defects on the tunneling current. We demonstrate that this learning is crucial for the integration of TFETs onto large area commercial Si substrates.

We report two approaches to integrate high quality III-V templates by epitaxial growth with low defectivity on Si wafers. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagation from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

Moore's Law describes the scaling of Si-based CMOS technology in terms of performance, power consumption, area and cost. As we have reached the physical limits of scaling Si channels, alternative materials with higher carrier mobility such as Ge and IIIV compound semiconductors are in order. This paper reviews some of imec's work on introducing In 0.53 Ga 0.47 As in a manufacturable and integratable way into mainstream Si-based CMOS technology. Several major issues are known: dielectric/IIIV interface passivation, mismatch of lattice and crystal structure between IIIV and Si, small bandgap leading to enhanced leakage,… We will discuss mainly the epitaxial growth aspects and the integration of IIIV materials in Si MOSFET devices, and point out some more unexpected materials and device issues.

As CMOS continues to approach the physical limits of silicon, interest has greatly increased in the use of high mobility alternatives for devices beyond the 14 nm technology node. By virtue of their high electron and hole mobilities, InGaAs and Ge respectively have emerged as the most promising candidates for n- and p-MOS but the co-integration of these materials on the same Si wafer remains a significant challenge for the introduction of a III-V/Ge CMOS solution. A promising option for integrating Ge and III-V materials on the same Si wafer is the use of the aspect-ratio-trapping (ART) technique. In this paper we present the results of using the ART technique to fabricate InGaAs based devices on 200mm Si wafers and to create virtual III-V/Ge substrates. While further development will be needed to integrate InGaAs and Ge devices on the same wafer these results create a path for the realization of a high-mobility CMOS solution

Over the last years there has been lots of interest in the use of germanium and III-V compounds as potential replacements for silicon channels. Germanium with its high hole mobility has attracted lots of attention for its application in advanced pMOS devices. Indium gallium arsenide compounds, with their intrinsically superior electron mobility and high saturation velocity, are considered as a candidate for nMOS devices beyond 14 nm node technology.

In this work we investigate the effect of different III-V surface passivation strategies during atomic layer deposition of Al"2O"3. X-ray photoelectron spectroscopy indicates that bare As-decapped and sulfur passivated In"0"."5"3Ga"0"."4"7As present residual oxides on the surface just before the beginning of the Al"2O"3 deposition while the insertion of a Ge interface passivation layer results in an almost oxide free Ge/III-V interface. The study of the initial growth regimes, by means of in situ spectroscopic ellipsometry, shows that the growth of Al"2O"3 on Ge leads to an enhanced initial growth accompanied by the formation of Ge-O-Al species thus affecting the final electrical properties of the stack. Alternatively, deposition on decapped and S-passivated In"0"."5"3Ga"0"."4"7As results in a more controlled growth process. The sulfur passivation leads to a better electrical response of the capacitor that can be associated to a lower oxide/semiconductor interface trap density.

In this work we present an in situ investigation of the interface composition between an In0.53Ga0.47As substrate and an Al2O3 oxide grown by molecular beam deposition in ultra high vacuum conditions. In the effort to improve the chemical quality of the interface, reduction of semiconductor-oxygen bonding at the interface can be obtained by growing a few thick pure Al layer before starting exposure of the surface to the atomic oxygen flux. Conversely, when a Ge interface passivation layer is intercalated between the semiconductor and the oxide stack, the interface chemistry is governed by Ge reaction with other species (Al, O), leading only to a partial suppression of the interface oxides. © 2010 Elsevier B.V. All rights reserved.

To effectively passivate the technologically important GaAs (001) surfaces, in situ deposition of Al2O3 was carried out with molecular beam epitaxy. The impacts of initial GaAs surface reconstruction and post-deposition annealing have been systematically investigated. The corresponding interfacial state density (D-it) were derived by applying the conductance method at 25 and 150 degrees C on both p-type and n-type GaAs metal-oxide-semiconductor capacitors to establish the D-it spectra in proximity of the critical midgap region. We show that significant reduction of D-it near the midgap is achieved by applying an optimized thermal annealing on samples grown on a Ga-rich (4x6) reconstructed surface. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3488813] ispartof: Applied physics letters vol:97 issue:11 status: published

Germanium has emerged as an exciting alternative material for high-performance scaled CMOS, however not without difficulties. After a review of the state-of-the-art, mainly focusing on two techniques to passivate the channel/dielectric interface, we analyze the strengths (carrier mobility, band gap), and weaknesses (n-type doping, lattice mismatch and BTBT leakage) of Ge for MOSFETs. We also identify some opportunities and the most important threats for the future of germanium.

The use of Ge and III/V materials for future CMOS applications is investigated. Good passivation of the Ge surface can be obtained by either GeO 2 or Si passivation. Short channel Ge pMOS devices with low EOT are fabricated using Si passivation at 350 and 500°C. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are discussed.

Electron beam evaporation in a molecular beam epitaxy reactor was used to deposit, at 400°C, amorphous LaAlO3 high-κ oxide films on p-type Si(001). X-ray photoelectron spectroscopy and transmission electron microscopy showed that the interface with Si is free of SiO2 or silicates. Electrical measurements performed on as-deposited samples reveal an equivalent oxide thickness as low as 5A for a film having a physical thickness of 41A, a leakage current of 5.6×10−2A∕cm2 at ∣Vg−VFB∣=1V, and no flatband voltage shift.