Integration of III-V on Si for High-Mobility CMOS

As CMOS continues to approach the physical limits of silicon, interest has greatly increased in the use of high mobility alternatives for devices beyond the 14 nm technology node. By virtue of their high electron and hole mobilities, InGaAs and Ge respectively have emerged as the most promising candidates for n- and p-MOS but the co-integration of these materials on the same Si wafer remains a significant challenge for the introduction of a III-V/Ge CMOS solution. A promising option for integrating Ge and III-V materials on the same Si wafer is the use of the aspect-ratio-trapping (ART) technique. In this paper we present the results of using the ART technique to fabricate InGaAs based devices on 200mm Si wafers and to create virtual III-V/Ge substrates. While further development will be needed to integrate InGaAs and Ge devices on the same wafer these results create a path for the realization of a high-mobility CMOS solution