Search

This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

This brief presents an all-digital PLL (AD-PLL) for a DDR5 registering clock driver (RCD) with a self-biased supply-noise-compensation (SNC) technique. By combining two Nagata current sources that have opposite dependency on supply variations, it offers a constant current to a ring oscillator over a wide range of supply voltage. Thereby, the dynamic voltage droop due to variations in workload is compensated while a voltage margin for mass production is improved. Since the SNC technique operates independently of the PLL loop bandwidth without using feedback, the proposed AD-PLL is free from the stability problem associated with bandwidth overlapping. Quantitative analyses on static and dynamic characteristics of the proposed SNC technique and relevant design considerations are addressed. Fabricated in the 28-nm CMOS technology, the AD-PLL occupies an active area of 0.06 mm2 and consumes 12.1 mW at 3.0 GHz with a 1.1 V supply voltage. The power-supply-noise-attenuation (PSNA) is measured as 40 dB and the integrated rms jitter of 271 fs is observed.

In this paper we present a novel, ultra-compact, True Random Number Generator (TRNG) architecture and its FPGA implementation. The proposed Latched Ring Oscillator (LRO) TRNG allows the generation of a TRNG bit from a single FPGA Slice. Despite its very compact structure, the proposed LRO-TRNG relies on both meta-stability and accumulated jitter as entropy sources, and exhibits very good results in terms of unpredictability and randomness. The proposed architecture has been implemented on Xilinx Spartan-6 devices and the TRNG performances have been extensively validated under supply voltage and temperature variations. Measurements results have shown that the LRO-TRNG exhibits an estimated entropy of about 7.99834 per bit (according to T8 test of the AIS-31) and a throughput of 0.76 Mbits/s with a 50MHz clock. A comparison against the state of the art shows that the proposed LRO-TRNG outperforms most of the previously published TRNGs, in terms of the ratio between throughput and FPGA resources usage.

A GaN complementary field-effect transistor (FET) inverter monolithically integrated with power gate-injection high-electron-mobility transistors (HEMTs) was realized on a Si substrate. The GaN p-channel and n-channel logic devices and power devices were fabricated based on a p-GaN/AlGaN/GaN epi-structure. Through optimization of epi-layer thickness and doping, excellent low-level noise margin (NM $_{L}$ ) of 1.47 V and high-level noise margin (NM $_{H}$ ) of 0.98 V were achieved at a supply voltage $V_{DD}$ of 3 V at room temperature. A maximum current density ( $I_{D,max}$ ) of 0.36 mA/mm/220 mA/mm at $V_{DS}$ of -3 V/3 V and a threshold voltage $V_{TH}$ of -2.0 V/+2.3 V were achieved in the p-channel and n-channel FETs, respectively. A propagation delay of an inverter stage $τ_{pd}$ in a ring oscillator was measured to be 1.67 μs. The power gate-injection HEMT has an on-resistance $R_{{on}}$ of 18.7 Ω ·mm and a breakdown voltage (BV) of 900 V. These results show the great potential of the developed GaN complementary FET technology in the applications of GaN power modules.

This paper proposes a low-power inverter in 65 nm CMOS technology, which utilizes a switched pseudo-current mirror to control the pull-up network and to reduce the short-circuit current during the transition. This inverter saves 75% power per cycle, while its power-delay product is almost half of the CMOS inverter. The proposed inverter constructs a low-power ring oscillator with improved thermal stability and aging robustness. The proposed structure of a 1 . 2 GHz ring oscillator consumes 0 . 66 mW , while its CMOS counterpart dissipates 4 . 46 mW . The immunity against supply voltage fluctuations is also improved. On the other side, the proposed inverter consumes twice the silicon area and doubles the propagation delay, limiting its usage in high-performance and high-density VLSI applications. These results indicate that the proposed inverter is a viable candidate for special applications, such as ring oscillators used in physically unclonable functions and true random number generators.

Mathematically secure cryptographic algorithms leak meaningful side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical side-channel analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include a current equalizer, IVR, non-linear LDOs, enhancing protection up to 10M traces, and current-domain signature attenuation (CDSA), and randomized NL-LDO cascaded with arithmetic countermeasures achieved protection up to >1B. This work embraces the concept of analog CDSA but makes it easily scalable over technology nodes with digital-friendly current sources, digital control loop, and digital bleed path to increase the MTD from 10M to 250M (25x improvement, using a single digital countermeasure). Ring oscillator (RO) used as the bleed path to bypass encryption-dependent leakage acts as local negative feedback (LNFB). Besides, based on RO oscillation frequency, AES node voltage can be tuned at startup, PVT, or frequency variation. Thus, RO acts as integrated LNFB and global feedback for the digital signature attenuation circuit (DSAC). Another circuit technique, namely, the time-varying transfer function (TVTF), removes the requirement of dc bias in the current-domain equalizer (best switch capacitor-based countermeasure till date) to make it digital and utilizes switch cap-based circuit for time-domain obfuscation to achieve enhanced security. This work, namely, Syn-STELLAR: SYNthesis-friendly Signature aTtenuation Embedded crypto with Low-Level metAl Routing, combines both DSAC and TVTF techniques to achieve an MTD>1.25B for both EM and power SCA, which is 25% higher than the existing state of the art. The 65-nm CMOS test chip contains unprotected and both the protected (DSAC and DSAC-TVTF) parallel AES-256 implementation. This implementation is the first synthesis-friendly countermeasure, which converges two analog-type strong protections (signature attenuation and switched cap current equalizer) in a digital-friendly solution and achieves >1.25B MTD with power and area overheads comparable to previous circuit-level countermeasures.

A temperature sensor named a thermillator (thermo-oscillator) is demonstrated, consisting of a single device with an n+-emitter, p-base and n+-collector. The thermillator with a p-base floating body shows inherent oscillation behavior. The underlying mechanism of the thermillator is based on the single transistor latch (STL). Oscillation originates with the iterative charging and discharging process in the floating p-base, and the oscillation frequency ( $\boldsymbol {f}$ ) is sensitively changed by applied temperature. Compared to a temperature sensor with a circuit-based ring oscillator, the single device-based thermillator has the advantages of small footprint area, low hardware cost, and low power consumption.

In this article, a differential ring-oscillator sensing platform for nanodroplet detection is presented. The system targets applications with volume sample requirements as low as 20 nL. The sensing mechanism is based on the dielectric constant variations of an interdigitated capacitor, embedded in a ring-oscillator structure, due to interactions with the liquid sample. Sensing is performed differentially using two oscillators operating at 692 ± 1 and 591 ± 1 MHz resulting in a frequency difference of 101 ± 1 MHz. The prototype of the sensor is fabricated using 180-nm CMOS process and occupies an area of 0.54 × 0.49 mm2. The experimental results validate the performance of the fabricated sensor to detect different concentrations of ethanol and methanol in water with sensitivity of 0.54 MHz/[L/L]% and 0.22 MHz/[L/L]%, respectively. The on-chip sensor is supplied with a 3.2-V voltage source and the average current for nominal operation is 10 mA.

Oxide semiconductor-based thin-film transistor (oxide-TFT) technology have gained significant attention since the innovation of n-channel oxide-TFT using ZnO and amorphous In–Ga–Zn–O (a-IGZO) channels because of their superior device properties including excellent electrical property such as high TFT mobility over >10 cm2/Vs and the low-cost manufacturability originating from the low-temperature processability. Already, n-channel a-IGZO-TFT is widely employed as a TFT pixel switching backplane for several high-performance active-matrix flat-panel displays, and oxide-TFT technology to date is well acknowledged as the best TFT technology for future device applications in the wide range area of electronics such as sensors, Internet of things (IoT), energy-harvesting, medical/bio-interface device, etc. Therefore, the development of large-scale circuit beyond discrete TFT device level becomes increasingly important and is vital to advance the next stage of oxide-TFT technology. In particular, developing oxide-TFT-based inverter device technology is the key for developing several digital and analog circuits. In this paper, the recent progress and challenges in oxide-TFT-based inverter technology, including unipolar NMOS, PMOS, CMOS, and CMOS-like inverters using ambipolar oxide-TFT, are reviewed.

This paper demonstrates opto-electronic ring-oscillator constructed by an odd number of opto-electronic inverters for the digital (electric) and analog (light) signals based on mixed-signal communications. The opto-electronic inverter is consisting of light-emitting and light-receiving parts which can be regarded as a digital-to-analog and an analog-to-digital converters, respectively. To investigate the light-signal processing properties, the oscillation frequency (fosc) studies were performed by controlling three different parameters of load resistors (RL), light wavelengths (λ), and photosensor type. The smaller RL or the shorter λ of the light signal brings the faster fosc in opto-electronic ring-oscillator. In addition, the photodiode-based opto-electronic ring-oscillator shows much faster signal processing characteristics than the case of CdS sensor. Our opto-electronic ring-oscillators show a wide range of tunable fosc from 0.92 Hz to 114.42 Hz; moreover, it shows small signal-like light transfer characteristics as an analog signal process that can be useful in future opto-electronic device applications.

This brief describes a fully integrated 10-V pulse driver. It comprises a four-stage switched-capacitor voltage multiplier (SCVM) and a dedicated high-voltage output driver (HVOD) with multiband pulse-frequency modulation (MPFM) to generate efficiently 10 V regulated output pulses. Specifically, an analog/digital hybrid-controlled current-starved ring oscillator (HCRO) modulates the switching frequencies at distinct bands to regulate the high-voltage (HV) supply for the HVOD, while enabling fast output transitions with an improved driving efficiency. Prototyped in 65-nm bulk CMOS, the driver demonstrates 10-V pulse generations over a 0.1-to-1-MHz range for a 15 pF//50 $\text{k}\Omega $ load. With the proposed MPFM, this work measures an overall driving efficiency of up to 19.9%, corresponding to a $\sim 1.6\times $ improvement over prior arts. The measured output rise time of 119 ns is also ~25% faster when compared with using the conventional pulse-frequency modulation (PFM) scheme.

This study is a unique approach for the design and implementation of True Random Number Generator (TRNG) using ADPLL, on Field-Programmable Gate Array (FPGA) board Artrix-7 (XC7A35T-CPG236-1) and t...

In the current work, we study the process variability of logic, interconnect, and arithmetic/DSP resources in commercial 16-nm FPGAs. We create multiple, soft-macro sensors for each distinct resource under evaluation, and we deploy them across the FPGA fabric to measure intra-die variation, as well as across multiple FPGAs to measure inter-die variation. The derived results are used to create device-signature variability maps characterizing the distribution of variability across the die. Our study includes decoupling of variability to systematic and stochastic parts, exploration of variability under various voltage and temperature conditions and correlation analysis between the variability maps of the different resources. Furthermore, we scrutinize the impact of variability on the performance of actual test circuits and correlate the retrieved results with the sensor-based maps. Our experimental results on four Zynq XCZU7EV FPGAs showed significant intra- and inter-die variability, up to 7.8% and 8.9%, respectively, with a small increase under certain operating conditions. The correlation analysis demonstrated a strong correlation between the logic and arithmetic resources, whereas the interconnects showed a slightly weaker correlation in specific devices. Finally, a relatively moderate correlation was calculated between the variability maps and performance of test circuits due their dissimilar operating behavior versus our sensors.

We report a dual gate (DG), low-temperature polysilicon (LTPS) thin-film transistor (TFT) using blue laser annealing (BLA) of amorphous silicon. The DG TFTs with variable bottom gate lengths (LBG) from 2 to 8 $\mu \text {m}$ and a fixed top gate length (LTG) of 6 $\mu \text{m}$ are investigated. The drain currents of the DG LTPS TFT with LBG > LTG by 2 $\mu \text{m}$ under DG sweep (DS) are ~4.3 times those of the single gate TFT. The high carrier concentrations (~1019 cm−3) at both interfaces (top gate insulator (GI)/poly-Si and poly-Si/bottom GI) under DS is confirmed by technology computer-aided design (TCAD) simulation, which might lead to high drain currents. The poly-Si layer exhibits no grain boundary protrusion from the transmission electron microscopy (TEM) cross-sectional micrograph and thus induces a strong bulk accumulation effect under DS. The fabricated DG TFT-based ring oscillator (RO) and shift register (SR) exhibit an excellent oscillation frequency of 15.8 MHz, fast-rising and falling time of 370 and 366 ns at a driving voltage of −10 V, respectively.

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized through changes in ring oscillator (RO) frequencies and current as a function of $V_{\mathrm {DD}}$ to model delay and power degradations in digital circuits. At the 7-nm node, tests show that gate delay decreased, and power consumption increased as TID increased. Percent increase in parameter degradations shows an inverse relationship with supply voltage, while percent increase in power consumption shows a direct relationship with supply voltage. Annealing at room temperature did not affect degradations. Circuit-level degradations for the 7-nm technology were less than 1% after TID exposure of 380 krad(SiO2). These TID exposure results will provide insight to designers about circuit-level parameters of interest concerning the 7-nm technology node.

In this article, the performance of silicon FinFET is compared with carbon nanotube (CNT-FET) and 2-D field-effect transistors (2D-FETs) for the upcoming node CMOS logic application. Based on the experimental results, a 17-stage ring oscillator (RO) circuit is implemented using the compact models to analyze the stage-delay and energy-delay performances. A tightly positioned 20- and 10-nm channel-length-based CNT-FET enhances ${I}_{\mathrm{\scriptscriptstyle ON}}$ and also increases the leakage currents significantly. Due to poor electrostatic control and increased gate leakage, the CNT-FET and 2D-FET provide lowered ${I}_{\mathrm{\scriptscriptstyle ON}}$ and a limited ac performance. Thus, targeting an off-state current, the FinFET delivers more than three times higher drive current, as well as five times better energy-delay performances in comparison to the CNT-FET and 2D-FET. On the other hand, scaled organic FETs are yet far away to compare with FinFET technology. Hence, the silicon-based (3-D) FETs are leading in all the devices (2-D, 1-D, and 0-D) for scaling next-generation CMOS technology.

This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.905@1 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage.

In this brief, we computationally examine electrical characteristics of stacked gate-all-around Si nanosheet MOSFETs (GAA NS-FETs) with and without metal sidewall (MSW) source/drain (S/D) by increasing the number of channels (NCs) and their impacts on digital circuits. The ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and circuit performances of the NS-FETs without the MSW S/D are limited to three channels due to the electrostatic potential decreasing from the top contacts to the bottom S/D side of NS-FETs; however, the MSW S/D can improve the ${I}_{\text {on}}$ with increasing the NCs over three channels because of low resistivity of tungsten ( $5.6\times 10^{-{6}}\,\, \Omega \cdot \text {cm}$ ) in the sidewall of S/D and then the circuit performances can be boost by the MSW S/D structure of the stacked GAA NS-FETs over three channels. For example, up to six channels of the NS-FETs with the MSW S/D, the frequency of ring oscillator is 57% increase, compared with the case without MSW S/D. The results of this study can be considered to design the S/D structure of the stacked GAA NS-FETs in emerging device technologies.

Physical Unclonable Functions (PUFs) exploit the manufacturing process variations inherent in silicon-based chips to generate unique secret keys. Although PUFs are supposed to be unclonable or unbreakable, researchers have found that they are vulnerable to machine learning (ML) attacks. In this article, we analyze the vulnerability of different FPGA-based Ring Oscillator PUFs (ROPUFs) to machine learning attacks. The challenge-response pairs (CRPs) data obtained from different ROPUFs is trained using different machine learning algorithms. From the study, it is found that the Artificial Neural Network (ANN) models can be used to train the ROPUFs with a training accuracy of 99.9% and a prediction accuracy of 62% when 5,000 CRPs are used for a challenge-response ROPUF. In this article, we assume a realistic situation where a small set of the CRP dataset (approximately 15% maximum) is unscrupulously obtained by the hacker. A prediction accuracy of 62% makes the PUF vulnerable to machine learning attacks. Therefore, a secondary goal of this article is the design of a ROPUF capable of thwarting machine learning modeling attacks. The modified XOR-inverter ROPUF drastically reduces the prediction accuracy from 62% to 13.1%, thus making it increasingly difficult for hackers to attack the ROPUF.

True Random Number Generators (TRNGs) create a hardware-based, non-deterministic noise that is used for generating keys, initialization vectors, and nonces in a variety of applications requiring cryptographic protection. A compromised TRNG may lead to a system-wide loss of security. In this brief, we show that an attack combining power analysis with bitstream modification is capable of classifying the output bits of a TRNG implemented in FPGAs from a single power measurement. We demonstrate the attack on the example of an open source AIS-20/31 compliant ring oscillator-based TRNG implemented in Xilinx Artix-7 28nm FPGAs. The combined attack opens a new attack vector which makes possible what is not achievable with pure bitstream modification or side-channel analysis.

The performance and reliability enhancement achieved in a conventional double-gate (DG) junctionless field-effect transistor (JLFET) by introducing a vacuum gate dielectric towards the drain terminal and a high- $$\kappa$$ gate dielectric (TiO $$_{2}$$ ) towards the source terminal is investigated. This arrangement of gate dielectrics enables enhanced gate controllability and offers significant protection against channel hot-carrier (CHC) effects at both device and circuit levels. At the device level, the DG-JLFET exhibits a 38% degradation in the drain current due to CHC stress, whereas the vacuum-gate DG-JLFET experiences only one-third of this value. The circuit-level analysis considers three benchmark circuits: ring oscillator (RO), static random-access memory (SRAM) cell, and common-source (CS) amplifier. The oscillating frequency of the RO is improved by 60% with the vacuum gate dielectric, with a 148% lower degradation in performance due to the CHC effect. The proposed approach is thus effective at both levels, not only improving the performance but also significantly enhancing the reliability.

3D integrated circuits introduce both advantages and disadvantages for security. Among the disadvantages unique to 3D is the potential insertion of a Trojan die into the stack between two legitimate dies. Such a die could be used to snoop information traveling between dies, alter the data, or otherwise interfere with stack operation. In this article, we explore the use of in-stack circuitry and various testing procedures to detect an extra die through delay analysis even in the presence of process variations. Then, we explore the performance of these techniques when the attacker modifies some of the TSVs’ characteristics to avoid detection. Our simulation results show that the proposed techniques can detect the Trojan die in a 3D stack, especially when the test structure that incorporates multiple TSVs between two dies is used.

This paper presents a wide frequency range three-stage voltage-controlled ring oscillator in CNTFET technology. The advantages of CNTFETs are the high speed of charge carriers, high signal to noise ratio, small size and ballistic transport. Therefore in comparison with MOSFETs, they have a higher frequency, and can operate at a wide frequency range with a very low phase noise if forward bulk bias and active inductor techniques are simultaneously used in the oscillators that employ CNTFETs. In this paper, the Stanford CNTFET model is implemented in Verilog-A, and the proposed CNT ring oscillator is simulated using ADS software over the 50–500 GHz frequency range. The phase noise of the oscillator is − 136 dBc/Hz at 1 MHz offset, which is suitable for PLL applications.

The voltage-controlled oscillator (VCO) is a critical block in the electronic and communication systems. It may be applied in frequency synthesis, clock signal generation, and a clock recovery circuit. In this article, the authors present the design and performance analysis of a 15-GHz, voltage-controlled ring oscillator using the 130-nm CMOS technology that operates in a 1.8-voltage power supply for high-speed applications. The designed scheme is a fivestage ring oscillator, which includes one inverter replaced by the NAND gate to shut down the ring oscillator during inactive mode. For improving the efficiency of the ring oscillator in the transceiver, different techniques such as transistor sizing are employed. In comparison to other publications, the authors' ring oscillator design is optimized with reference to the central frequency and power dissipation.

This article presents the control circuit of a power converter that regulates the computing speed of a digital circuit. The proposed circuit implements a digital delay regulation of a digital delay line (DDL) matched with the ring oscillator (RO) that clocks the digital subsystem. The converter regulates the supply voltage of the digital subsystem so that the propagation delay through the DDL matches a time reference. Consequently, the frequency of the RO tracks the DDL delay and the frequency keeps a controlled value over process, voltage, and temperature (PVT). A 65-nm CMOS prototype validates the proposed method. The prototype includes an Arm Cortex-M33 CPU and memories optimized for sub-threshold operation. With the proposed method, the computing performance of the CPU is guaranteed for running real-time application while minimizing the supply voltage margins.

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 – 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 – 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training.

Controlling an ultrafast laser oscillator repetition rate is crucial for the emerging laser burst micromachining. The efficiency of a material surface treatment process as well as the quality of live tissue ablation depends, to a considerable extent, on the number of laser pulses in a burst window. In the following article, we present an all-PM fiber harmonically mode-locked Mamyshev ring oscillator capable of producing laser pulses with a tunable period. The oscillator can be operated at any frequency, being a multiple of the fundamental repetition rate up to 305 MHz at 19th harmonic. We found that the operation frequency is limited by the available pump power only. What is worth noting is that the energy of the emitted pulses is independent of the operating frequency. The essential laser parameters are excellent: an amplitude noise of 0.1% and fundamental frequency suppression levels of 70 dB at every repetition rate. Additionally, the mechanism of harmonic mode-locking is discussed in detail and is found to be caused by gain depletion and recovery effect.

Aiming at the lack of reliability and uniqueness of the traditional configurable ring oscillator physical unclonable function (RO-PUF) due to the simple configurable path, a configurable RO-PUF is proposed based on the delay characteristics of the ring oscillator. The design scheme redesigned the RO structure, making the configurable path of the RO-PUF more flexible and increasing the number of incentive response pairs (CRPs); At the same time, the introduction of a lightweight SPONGENT hash algorithm in the RO-PUF structure makes the mapping between incentives and responses more complicated, prevents attackers from building model attacks by acquiring CRPs, and enhances RO-PUF security. And then, the design scheme is implemented on Xilinx’s Spartan series FPGA chip, and the experimental results are compared and analyzed. The results show that the configurable RO-PUF designed with this scheme has an average reliability of 98.87% and uniqueness of 49.13%.

Integrated circuits (IC) of two digitally controlled oscillators (DCO) are presented in this article – ring and LC-tank oscillator. Main parameters of these DCOs are measured and compared, applications of such DCOs are discussed. Ring DCO is made of 48 sections of 3-stage ring oscillators. Base component of ring oscillator is tristate inverter, which is accessible in modern CMOS technologies, therefore, such oscillator can be implemented using digital IC design tools. Main components of LC-tank DCO are inductor, switched-capacitor bank, and a pair of cross-coupled NMOS transistors. Frequency of ring DCO is controlled by enabling or disabling its separate sections, while frequency of LC DCO is controlled by switching capacitors of LC tank. Although LC DCO is controlled digitally, its core is analog and it can be implemented only using custom design tools. Both DCOs are designed and their prototypes are manufactured in mature and low-cost 0.13 μm RF CMOS technology. Ring DCO’s frequency tuning range is 370–873 MHz; phase noise at maximum operating frequency at 1 MHz offset from carrier is – 109.19 dBc/Hz; power consumption is 3.6 mW; used area of silicon is 0.0065 mm2. LC-tank DCO’s frequency tuning range is 9.26–10.58 GHz; phase noise at maximum operating frequency at 1 MHz offset from carrier is –106.46 dBc/Hz; power consumption is 18 mW; used area of silicon is 0.06 mm2. Operating frequency of LC-tank DCO is much higher, however Figures of Merit of ring and LC-tank DCOs are comparable and respectively equal to –140.61 dBc/Hz and –136.88 dBc/Hz. It shows, that both DCOs can be used in modern systems for appropriate applications. Main applications of LC-tank DCO are high-speed systems, where high frequency is needed, while in low-cost, low-power systems ring DCO is more suitable.

Process and parametric variation negatively impact the performance and yield of analog and digital circuits in advanced nodes. To alleviate this effect, we propose a technique to electrically adjust the threshold voltage of CMOS transistors in a post-fabrication setting in a non-volatile manner. This technique, which relies on self-heating assisted trapping of charge in high-k gate dielectric (e.g. HfOx) used in advanced CMOS nodes, does not require any extra fabrication step. In this letter, we use charge trapping for wideband non-volatile frequency tuning of a ring oscillator. We have demonstrated that the frequency of the ring oscillator can shift from 2075MHz to 1746MHz, when a supply voltage of 0.8V is used. This work serves as a foundation for non-volatile tuning, reconfiguration, and obfuscation of chips and IP blocks. The chip was fabricated in GlobalFoundries 22nm Fully-Depleted Silicon-on-Insulator (FDSOI) CMOS process.

Lightweight physical unclonable functions (LPUFs) exploit manufacturing process variations of semiconductor integrated circuits (ICs) to protect IoT-based electronic and smart devices from new cyberattacks. This paper proposes two novel security techniques to enhance the robustness of LPUFs using configurable-based ring oscillator PUFs (CF-ROPUFs). These techniques are the intra-die frequency aware (IFA) approach to improve PUF reliability and the logarithmic gamma function ( $Ln_{\gamma }$ ) technique to enhance PUF randomness. The lightweight CF-ROPUF design is realized on hardware, and data samples are collected under varying temperatures and supply voltages over a population of 30 Spartan-3E FPGAs. Experimental results of the IFA technique in terms of average Hamming Weight (HM) demonstrate that the percentage of the reliable RO sample frequencies PUF output is 98.5%. For the analysis, PUF reliability is evaluated in terms of accuracy, repeatability, and reproducibility, the international organization for Standardization (ISO) standards. The results indicate that the RO samples are accurately measured from the CF-ROPUFs mapped in all the chips. After using the proposed 1-out-of-r coding algorithm, the results demonstrate high average repeatability of 98.2% and a magnified average reproducibility of 99.63%. It is also shown that our CF-ROPUF design is immune from accelerated aging impacts reliability issues. Statistical results show that Ln( $Ln_{\gamma }$ ) enhances the normality and mitigate the negative impacts of the systematic process variations on RO sample frequencies. Randomness results show that CF-ROPUF binary response bits can successfully pass the 15 NIST test suites for true randomness with an enhanced percentage, 93.3%, with the application of the 1-out-of-r coding.

This article proposes and validates a low complexity multichannel ring-oscillator (RO)-based time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs). Channels of that TDC are mainly composed of look-up Tables (LUTs) configured as embedded memories. The channels share the same ring oscillator. A previously proposed delay tuning method was used to increase the overall accuracy by balancing the TDC channels. Compared to previously reported TDCs, the proposed architecture consumes fewer resources without degrading performances. A nine-channel TDC was implemented in a Zynq-7 Xilinx FPGA. Single-shot precision of 92.7 ps and accuracy of 92.9 ps were achieved, while consuming 1.49% and 1.31% of the available LUTs and FFs of a ZYNQxc7z010-3clg400 Xilinx FPGA, respectively.

This letter presents a compact and energy-efficient digital CMOS temperature sensor. A leakage-dominated ring oscillator (LDRO) with exponential temperature dependence and tunable supply sensitivity is proposed. A Schmitt-trigger with feedback power gating is used to minimize short-circuit currents in the delay cell. An adaptive frequency-to-digital converter is proposed in this work to improve flexibility and efficiency. It remains accurate while the reference clock can be higher or lower than the sensed frequency. Fabricated in a standard digital 55-nm CMOS process, this sensor has an active area of 2400 $\mu \text{m}^{2}$ and achieves a resolution figure of merit (FoM) of 0.26 pJ $\cdot \text{K}^{2}$ . It has a measured inaccuracy of ±0.8 °C ( $3\sigma $ ) from −40 °C to 85 °C after a 1-point correlated calibration.

In this work, we demonstrate CMOS integration that is fully compatible with a commercial double-implanted MOS (DMOS) process in 4H-SiC without requiring additional masks and cost. The characteristics of the NMOS, the PMOS, the CMOS inverter, and the ring oscillators are measured up to 175 °C. Propagation delay is reduced from 117 ns at room temperature to 17.8 ns at 175 °C, thanks to the increased current capability of both the NMOS and the PMOS. The body effect from the high substrate voltage on the PMOS is also investigated. The characteristics of the PMOS and the CMOS inverter are measured for a substrate voltage up to 800 V. The propagation delay for the ring oscillator is also measured when the substrate voltage is 300 V.

This paper proposes and analyzes a CMOS divide-by-8 injection locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-8 ILFD in the TSMC $0.18~\mu \text{m}$ 1P6M CMOS process has a locking range from 15.5 GHz to 17.8 GHz at the power consumption of 10 mW. The varactorless divide-by-8 ILFD occupies a small area of $0.8044\times 0.72$ mm2. The ILFD can be used in divide-by-4 mode and has a locking range from 4.8 GHz to 10.6 GHz at the power consumption of 10.43 mW. The ring oscillator based frequency divider (FD) is designed with a pair of differential outputs so that the whole divide-by-8 ILFD provides differential output. The ring oscillator FD uses unbalanced component parameters to optimize the circuit performance and it supplies two unbalanced tail currents to the LC ILFD, which also provide unbalanced outputs despite the circuit topology is a symmetric one. The unbalanced approach offers design flexibility.

The existence of counterfeit products, e.g., integrated circuits (ICs) and printed circuit boards (PCBs), in the modern semiconductor supply chain has seriously jeopardized the security and reliability of electronic systems, and has also caused the loss of suppliers' profit and reputation. Most of existing research papers prevent or detect counterfeit IC and PCB substrate separately, without testing the PCB as a whole, and often require the assistance of external equipment. In this article, a novel ring oscillator-based PCB authentication (ROPA) methodology to detect counterfeit PCB through supply chain is proposed, which utilizes PCB trace-based ring oscillators (PTRO) assisted by on-chip ring oscillators, and a novel PCB signature extraction methodology. By switching the PCB to different load modes, the signature can reflect the process variations in PCB traces and overall impedance. The ROPA can provide both IC and PCB authentication independently of external equipments, and allows remote authentication for the user. The ROPA structure has shown advantageous area (0.301% on average) and power (0.355% on average) overhead when implemented on a number of benchmarks. Then the ROPA is implemented on a set of authentic and counterfeit FPGA development boards to verify the effectiveness on counterfeit detection. The results show that the proposed method provides 96.7% confidence in detecting tampered PCBs and 100% confidence in detecting overproduced, recycled, and cloned PCBs.

A gallium nitride (GaN) ring oscillator based on high-performance one-chip complementary logic (CL) inverters is demonstrated on a conventional ${p}$ -GaN gate power HEMT (high-electron-mobility transistor) platform. It manifests the feasibility of the multiple-stage monolithic integration of GaN CL gates, the most energy-efficient digital circuit configuration, and consequently the potential of deploying CL circuits in the all-GaN power integration as peripheral circuits with higher energy efficiency. Thanks to the successful monolithic integration of enhancement-mode ${p}$ -channel and ${n}$ -channel field-effect transistors, the integrated CL inverters in this work present remarkable performances, including stringent rail-to-rail operations, substantially suppressed static power dissipation at both logic ‘low’ and ‘high’ states, suitable transition threshold voltages of ~2.0 V (40% of the common 5-V supply) and wide noise margins above 1.8 V (36% of 5 V).

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and inentropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation. Ministry of Education (MOE) Published version This work is supported by grants from the Engineering and Physical Sciences Research Council (EPSRC) (EP/N508664/- CSIT2), the Singapore Ministry of Education AcRF Tier 1 Grant No. 2018-T1-001-131, the National Natural Science Foundation of China (62022041 and 61871216), the Fundamental Research Funds for the Central Universities China (NE2019102) and the Six Talent Peaks Project in Jiangsu Province (2018XYDXX-009).

This article presents a novel design of high-speed ring oscillator (RO) in ${n}$ -type-only indium-zinc-oxide (IZO) thin-film transistor (TFT) technology. The proposed ROs combine the advantage of the skewed delay (SD) scheme and the bootstrap inverter to achieve a higher oscillation frequency. The design of improved output buffers with stronger driving capability is also included. For comparison, the proposed seven-stage SD ROs and the conventional bootstrap RO are fabricated on the same glass. It is measured that the oscillation frequencies of the SD ROs with $-{t}_{{\text {pd}}}$ and 0 SD are improved by more than 45% and 25% within the supply voltage ranges from 6 V up to 20 V. In addition, the measured output swings of the proposed boost buffers are improved by more than 50% with input frequencies higher than megahertz.

Physical unclonable function (PUF) is a technique to produce secret keys or complete authentication in integrated circuits (ICs) by exploiting the uncontrollable randomness due to manufacturing process variations. For better PUF applications, efficient analysis of different designs is important. In this article, a mathematical model to analyze the performance of typical strong PUF designs is proposed and applied to arbiter PUF, ring oscillator (RO) PUF, and duty cycle (DC) PUF. For better reliability, a new PUF design, DC multiplexer (DC MUX) PUF proposed in our previous work is analyzed. The proposed model indicates that DC MUX PUF achieves 2% higher reliability than arbiter PUF under environment influences. It also shows that DC PUF achieves 10% higher reliability than RO PUF. For verification, the aforementioned four PUF designs are testified using HSPICE. As our model analysis indicates, for reliability DC MUX PUF outperforms arbiter PUF, and DC PUF outperforms RO PUF. For randomness, DC MUX PUF and DC PUF outperform arbiter PUF and RO PUF, respectively. For security, LR attacks on DC MUX PUF and arbiter PUF are performed. The training time for DC MUX PUF is 40 000 times of arbiter PUF.

We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimentally demonstrate that the new AS provides 15% reduction in the effective capacitance ( ${C}_{{\text {eff}}}{)}$ . Such a ${C}_{{\text {eff}}}$ reduction translates to 21% performance gain at the constant power (iso-power) or 36% power reduction at the constant performance (iso-speed). The benefits provided by AS exceed the benefits of a full CMOS node scaling from 7 to 5 nm. Clearly, AS is a viable technological element for continuing CMOS scaling.

The objective of this paper is to evaluate the delay impact of staggered metal filling on the standard cells and their associated local interconnect on several metal levels. A Design of Experiment (DOE) is used to define a large range of filling pattern shapes and positions. This set of filling patterns is then inserted in a Ring Oscillator (RO). From the filled RO simulations, the RO delay is expressed as a function of the filling pattern features. The maximal timing error between the model and the simulation is 1.3%, validating the model. The filling impact on RO delay magnifies the one introduced by the front-end process variations (PVT). Consequently, the filling influence is introduced for the minimal, typical and maximal corners, defined now with Process (P), Voltage (V), Temperature (T) and Filling density (F) characteristics.

Frequency multiplying wireless transmitters (TX) employing harmonic injection-locked technique benefit from high energy efficiency and less hardware complexity but largely suffer from reference spurs that violate the TX spectral specifications. This work proposes a self-aligned phase-locked loop (PLL) in conjunction with harmonic injection locking technique to achieve significantly improved spur performance under ultra-low-power (ULP) operations for sub-GHz IoT TXs. The on-chip type-I PLL calibrates the phase error in the ring oscillator (RO) in real-time and avoids large spurs induced from the frequency deviation in the harmonic injection locking. A compact zero power consumption twin-T notch filter for spur suppression is implemented within the PLL loop to tackle the rail-to-rail voltage jump that comes from the output of the phase detector (PD). Designed and fabricated in the TSMC 180 nm CMOS process, the proposed frequency multiplying TX occupies an active area of only 0.0413 mm2. The lowest power consumption with >3X improved energy-efficiency is observed while consistently achieving >62 dB spur suppression with −14 dBm output at 915 MHz. The TX supports OOK modulation with an average power consumption of $200.9~\mu \text{W}$ only at 3 Mb/s data rate achieving a normalized 66.97 pJ/bit energy efficiency.

The utility of true random number generators (TRNGs) is not only restricted to session key generation, nonce generation, OTP generation etc. in cryptography. In the proposed work, two ring oscillator (RO) based TRNG structures adopting identical and non-identical ring of inverters have alone been employed for confusion (scrambling) and diffusion (intensity variation) processes for encrypting the greyscale and RGB images. Cyclone IVE EP4CE115F29C7 FPGA was utilised to generate a couple of random synthetic images using the two RO architectures which took a maximum of 520 combinational units and 543 logic registers. The suggested scheme of image encryption was tested on 100 test greyscale images of size 256 × 256. This non-chaos influenced image ciphering has resulted in an approximate average entropy of 7.99 and near-zero correlation figures for the greyscale & RGB cipher images. The attack resistance capability was checked by performing various occlusion and noise attacks on encrypted images.

This study presents a low-cost multi-throughput true random number generator (TRNG) intellectual property (IP) based on a variable-length multi-mode ring oscillator. The proposed TRNG implements a multi-throughput feature by bypassing inverter cells in the ring oscillator for reducing the loop delay. This multi-throughput feature offers the advantage of high-performance or low-power operation when needed. These options make the proposed TRNG suitable for end-to-end encryption in highly restricted devices such as Internet of Things sensor nodes. Measurement results show that the proposed TRNG passes national institute of standards and technology (NIST) tests for different throughput operations. The TRNG is embedded in a reduced instruction set computer V (RISC-V)-based system-on-chip (SoC) for periodical-driven applications, and it achieves an energy efficiency of 92 pJ at 3.7 Mbps, occupying 58 μ m × 150 μ m in a 180 nm technology. This study also presents a system technique to implement the entropy enhanced TRNGs, using multiple entropy sources. An extraction system provides high-quality random numbers with a sampling method that takes one entropy output to sample the other entropy sources. The system requires few resources, using low-cost TRNG IPs as entropy sources.

This paper presents a novel, real time, high speed and robust chaos-based pseudo random number generator (PRNG) design using the structures of artificial neural network (ANN)-based 2D chaotic oscillator and ring oscillator. In this study, four different robust PRNGs have been implemented using four different approaches (TS-55, Elliott-93, Elliott-2, Cordic-LUT) of TanSig activation functions (TSAF) that have been used in the design of ANN-based 2D chaotic oscillators. The designs have been coded in VHDL using IEEE-754-1985 number standard. The PRNGs have been synthesized for Virtex-6 FPGA chip using Xilinx ISE Design Tools. After Place&Route operation, FPGA chip statistics and maximum operating frequencies have been presented. The maximum operating frequencies of the proposed PRNGs range between 184 and 241 MHz. The 1 Mbit of bit streams generated by PRNGs have been subjected to NIST-800-22 randomness tests. Among 4 different proposed PRNGs, the proposed PRNGs that designed using the Elliott-93 and Cordic-LUT approaches have successfully passed all NIST-800-22 tests and have a bit production rate of 241 Mbps. The proposed secure hybrid chaos-based PRNG structures were compared with similar studies conducted in the literature in recent years. According to the results, the proposed FPGA-based secure new chaotic PRNG structures are useful in cryptographic applications.

In this work, we developed and explored the CMOS circuits ring oscillator with n- and p-channel on scaled SB-FETs for low power applications. Newly, a source-side charge plasma schottky barrier (SB) SB-FETs have been acquainted as the furthermost practical at nano-meter node technology. So, it is essential to examine the electrical characteristics of SB-FETs and their performance. Initially, we have been explored the source-side charge plasma SB-FET and its electrical characteristics has been simulated in compared with conventional SB-FET. The SILVACO simulator is used to simulate the proposed and conventional SB-FETs. In this source-side charge plasma SB-FET technique has improved resolution, and deliver outstanding concert (higher Ion/Ioff ratio) than conventional device reported in this research. Moreover, the precise exploration of the on-state performance of SB-FETs is mostly resolved by the electron and hole energy band of the channel. Additional, for the first time, source-side charge plasma SB-FET-based CMOS inverter and ring oscillator circuits have been calculated by the numerical simulator. The concentrated gate capacitance also grades in compact dynamic power degeneracy of source-side charge plasma schottky barrier SB-FET CMOS circuits and ring oscillator suggest lower voltage of process with condensed power intake, and great noise protection compared with convention device.

Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS-based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits significant p–i–n forward current with an increase in negative drain-to-source voltage bias. It is demonstrated that TFET transmission gate exhibits unconventional behaviour due to p–i–n forward current of the device. Leveraging this behaviour TFET RNG is designed that extracts random bits from delay variations of the TFET ring oscillator. The proposed TFET RNG achieves low area overhead when compared with the baseline CMOS designs. The proposed DPA countermeasure is demonstrated by integrating the original TFET substitution box (S-box) and TFET RNG. The proposed architecture is found to be resilient to DPA attack and the area overhead of single S-box and Advanced Encryption Standard AES is as low as 12 and 5%, respectively. Apart from low area overhead, the TFET designs with inherent device characteristics show high robustness against reverse engineering attacks which provide a higher level of security to TFET-based circuits and systems.