Channel-hot-carrier degradation in the channel of junctionless transistors: a device- and circuit-level perspective

The performance and reliability enhancement achieved in a conventional double-gate (DG) junctionless field-effect transistor (JLFET) by introducing a vacuum gate dielectric towards the drain terminal and a high- $$\kappa$$ gate dielectric (TiO $$_{2}$$ ) towards the source terminal is investigated. This arrangement of gate dielectrics enables enhanced gate controllability and offers significant protection against channel hot-carrier (CHC) effects at both device and circuit levels. At the device level, the DG-JLFET exhibits a 38% degradation in the drain current due to CHC stress, whereas the vacuum-gate DG-JLFET experiences only one-third of this value. The circuit-level analysis considers three benchmark circuits: ring oscillator (RO), static random-access memory (SRAM) cell, and common-source (CS) amplifier. The oscillating frequency of the RO is improved by 60% with the vacuum gate dielectric, with a 148% lower degradation in performance due to the CHC effect. The proposed approach is thus effective at both levels, not only improving the performance but also significantly enhancing the reliability.