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Improved Air Spacer for Highly Scaled CMOS Technology

Authors :
Tenko Yamashita
Andrew M. Greene
Kangguo Cheng
Frougier Julien
Miaomiao Wang
Balasubramanian S. Pranatharthi Haran
Sanjay Mehta
Nicolas Loubet
Richard A. Conti
Son Nguyen
Zuoguang Liu
Jingyun Zhang
Heng Wu
Juntao Li
Chanro Park
Rama Divakaruni
Source :
IEEE Transactions on Electron Devices. 67:5355-5361
Publication Year :
2020
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2020.

Abstract

We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimentally demonstrate that the new AS provides 15% reduction in the effective capacitance ( ${C}_{{\text {eff}}}{)}$ . Such a ${C}_{{\text {eff}}}$ reduction translates to 21% performance gain at the constant power (iso-power) or 36% power reduction at the constant performance (iso-speed). The benefits provided by AS exceed the benefits of a full CMOS node scaling from 7 to 5 nm. Clearly, AS is a viable technological element for continuing CMOS scaling.

Details

ISSN :
15579646 and 00189383
Volume :
67
Database :
OpenAIRE
Journal :
IEEE Transactions on Electron Devices
Accession number :
edsair.doi...........3eae7845f5c89eb230879ae7a8cdbff0
Full Text :
https://doi.org/10.1109/ted.2020.3031878