Switched pseudo-current mirror inverter for low-power, thermally stable and robust ring oscillator

This paper proposes a low-power inverter in 65 nm CMOS technology, which utilizes a switched pseudo-current mirror to control the pull-up network and to reduce the short-circuit current during the transition. This inverter saves 75% power per cycle, while its power-delay product is almost half of the CMOS inverter. The proposed inverter constructs a low-power ring oscillator with improved thermal stability and aging robustness. The proposed structure of a 1 . 2 GHz ring oscillator consumes 0 . 66 mW , while its CMOS counterpart dissipates 4 . 46 mW . The immunity against supply voltage fluctuations is also improved. On the other side, the proposed inverter consumes twice the silicon area and doubles the propagation delay, limiting its usage in high-performance and high-density VLSI applications. These results indicate that the proposed inverter is a viable candidate for special applications, such as ring oscillators used in physically unclonable functions and true random number generators.