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1. Parametric variability affecting 45 nm SOI SRAM single event upset cross-sections

2. Monte Carlo simulation of single event effects

3. Heavy ion testing and single event upset rate prediction considerations for a DICE flip-flop

4. General framework for single event effects rate prediction in microelectronics

5. Impact of low-energy proton induced upsets on test methods and rate predictions

6. Integrating circuit level simulation and Monte-Carlo radiation transport code for single event upset analysis in SEU hardened circuitry

7. Multi-scale simulation of radiation effects in electronic devices

8. Monte-Carlo based on-orbit single event upset rate prediction for a radiation hardened by design latch

9. A generalized SiGe HBT single-event effects model for on-orbit event rate calculations

10. Application of RADSAFE to model the single event upset response of a 0.25 [micro]m CMOS SRAM

11. Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology

12. Implications of nuclear reactions for single event effects test methods and analysis

13. Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design

14. Role of heavy-ion nuclear reactions in determining on-orbit single event error rates

15. The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM

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