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29 results on '"Laurent Brunet"'

1. Total-Ionizing-Dose Effects on 3D Sequentially Integrated, Fully Depleted Silicon-on-Insulator MOSFETs

Author

Shintaro Toguchi, Michael L. Alles, Laurent Brunet, Perrine Batude, Ronald D. Schrimpf, Severine Cheramy, Mariia Gorchichko, Stephane Moreau, Robert A. Reed, Daniel M. Fleetwood, Francois Andrieu, and En Xia Zhang

Subjects
010302 applied physics, Fabrication, Materials science, business.industry, Infrasound, Silicon on insulator, 01 natural sciences, Noise (electronics), Electronic, Optical and Magnetic Materials, Active layer, Absorbed dose, 0103 physical sciences, Optoelectronics, Irradiation, Electrical and Electronic Engineering, business, Voltage
Abstract

Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency (1/ ${f}$ ) noise measurements are compared for (1) conventional planar FD-SOI MOSFETs, and (2) MOSFETs formed in the bottom layer of the 3D process and subjected to the process steps associated with formation of a second active layer. Similar radiation-induced voltage shifts and increases of 1/ ${f}$ noise are observed after irradiation for both types of structures. These similar changes in response show that the additional thermal processing involved with 3D fabrication has little effect on border-trap densities and radiation-induced charge trapping in gate and/or buried oxides of MOSFETs formed in the bottom layer of the 3D process.

Published
2020

2. RF Performance of Devices Processed in Low-Temperature Sequential Integration

Author

Xavier Garros, Jose Lugo-Alvarez, Laurent Brunet, Perrine Batude, Christoforos G. Theodorou, P. Sideris, Philippe Ferrari, C. Fenouille-Beranger, T. Mota Frutuoso, F. Gaillard, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
010302 applied physics, Coupling, Materials science, Transistor, 01 natural sciences, 7. Clean energy, Electronic, Optical and Magnetic Materials, law.invention, Threshold voltage, PMOS logic, [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, law, Logic gate, 0103 physical sciences, Figure of merit, Radio frequency, Electrical and Electronic Engineering, Atomic physics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, [PHYS.PHYS.PHYS-DATA-AN]Physics [physics]/Physics [physics]/Data Analysis, Statistics and Probability [physics.data-an]
Abstract

RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with ${f}_{t} =105$ GHz and ${f}_{\text {max}} =175$ GHz for a gate length of 45 nm and ${V}_{\text {DD}} = -1$ V. Moreover, we demonstrate that the low- ${k}$ SiCO oxide spacer and low polysilicon gate resistance obtained with the low temperature process contribute to ${f}_{\text {max}}$ results that are better than high temperature process (above 1000°). Finally, we illustrate the crosstalk effects and the influence of the low-tier transistor gate voltage ${V}_{\text {G}}$ on the top-tier threshold voltage ${V}_{T}$ . We also show that a polysilicon ground shield integrated under the top-tier transistor substantially attenuates the intertier RF field coupling effects.

Published
2021

3. Inter-tier electrostatic coupling effects in 3D sequential integration devices and circuits

Author

Perrine Batude, Laurent Brunet, Gilles Sicard, Lorenzo Ciampolini, Christoforos G. Theodorou, P. Sideris, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
010302 applied physics, Physics, Coupling, Spice, Transistor, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Noise (electronics), Electronic, Optical and Magnetic Materials, law.invention, [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, law, 0103 physical sciences, Materials Chemistry, Electronic engineering, Static random-access memory, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Electronic circuit
Abstract

International audience; This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.

Published
2020

4. Laser Processing For 3D Junctionless Transistor Fabrication

Author

F. Balestra, C. Perrot, Joris Lacord, Didier Lattard, Perrine Batude, Benoit Sklenard, V. Benevent, P. Acosta Alba, Sebastien Kerdiles, D. Bosch, Claire Fenouillet-Beranger, J. Lassarre, J. Richy, Francois Andrieu, J.-P. Colinge, and Laurent Brunet

Subjects
010302 applied physics, Materials science, Fabrication, business.industry, Annealing (metallurgy), Doping, Transistor, 0211 other engineering and technologies, FOS: Physical sciences, Physics - Applied Physics, 02 engineering and technology, Applied Physics (physics.app-ph), Nanosecond, 01 natural sciences, Semiconductor laser theory, law.invention, law, 021105 building & construction, 0103 physical sciences, Optoelectronics, Wafer, business, Layer (electronics)
Abstract

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.

Published
2020
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5. Inter-tier Dynamic Coupling and RF Crosstalk in 3D Sequential Integration

Author

Perrine Batude, Gerard Ghibaudo, Gilles Sicard, O. Rozeau, C. Fenouillet-Beranger, Christoforos G. Theodorou, Francois Andrieu, Sebastien Kerdiles, P. Sideris, Jose Lugo-Alvarez, Laurent Brunet, P. Acosta-Alba, J.-P. Colinge, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
010302 applied physics, Digital electronics, Materials science, business.industry, Sram cell, 01 natural sciences, Active devices, Dynamic coupling, [SPI.TRON]Engineering Sciences [physics]/Electronics, Crosstalk, 0103 physical sciences, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Sheet resistance, [PHYS.PHYS.PHYS-DATA-AN]Physics [physics]/Physics [physics]/Data Analysis, Statistics and Probability [physics.data-an], Ground plane
Abstract

International audience; For the first time, an in-depth analysis of the intertier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to conclude on the need of a Ground Plane (GP) for various applications. Experiments in conjunction with TCAD simulations reveal the parasitic capacitances responsible for the dynamic coupling effects and their impact is investigated for a 3D sequential 2-bitcell SRAM cell circuit configuration. Furthermore, we show a greater than 20dB suppression up to 100GHz of the inter-tier RF crosstalk, achieved by the addition of a strategically designed polysilicon Ground Plane between active device layers enabling the possibility of heterogeneous 3DSI integration without metallic Ground Plane. We propose a technological solution to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 n-doping and 295Ω/sq sheet resistance.

Published
2019

6. Back-bias impact on variability and BTI for 3D-monolithic 14nm FDSOI SRAMs applications

Author

Francois Andrieu, L. Ciampolini, G. Cibrario, F. Balestra, Joris Lacord, Xavier Garros, Perrine Batude, Laurent Brunet, A. Makosiej, D. Lattard, Bastien Giraud, Maud Vinet, Claire Fenouillet-Beranger, J.-P. Colinge, Olivier Weber, J. Cluzel, D. Bosch, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Computer science, WNM, 02 engineering and technology, 01 natural sciences, SNM, Stress (mechanics), Planar, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Static noise margin, Static random-access memory, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, variability, 020208 electrical & electronic engineering, SRAM margins, 3D-monolithic, FDSOI, Temperature instability, BTI stress, Spatial variability, Back bias, Back/Body Biasing, Voltage, Supply Read Retention Voltage
Abstract

International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltage (VDD) and back bias (Vwell) are extracted. These data evidence that the 14nm SRAM is read-limited, which could be improved by a smart back-bias management [1]. In this work we demonstrate a 50mV Static Noise Margin (SNM) variability improvement (at VDD=0.8V) by back-biasing, without additional Bias Temperature Instability (BTI) stress. Such an assist technique can be eventually leveraged at fine-grain by 3D monolithic integration, owing to local back-planes.

Published
2019

7. Impact of Inter-Tier Coupling on Static and Noise Performance in 3D Sequential Integration Technology

Author

P. Sideris, Perrine Batude, Laurent Brunet, Gilles Sicard, Christoforos G. Theodorou, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
010302 applied physics, Coupling, Work (thermodynamics), Computer science, Silicon on insulator, Electrostatic coupling, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, 0103 physical sciences, Electronic engineering, Layer (object-oriented design), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, [PHYS.PHYS.PHYS-DATA-AN]Physics [physics]/Physics [physics]/Data Analysis, Statistics and Probability [physics.data-an]
Abstract

International audience; This work presents for the first time an analytical study of the electrostatic coupling between bottom and top layer of 3D sequential integration devices, regarding its impact on both static and noise behavior. The effect is demonstrated experimentally through statistical measurements, and TCAD simulations are used to further examine its properties and propose ways for the limitation of inter-tier coupling. It is demonstrated that regarding digital applications, the coupling-induced fluctuations are well within the mismatch variation level.

Published
2019

8. Variance Analysis in 3D Integration: A statistically Unified Model with Distance Correlations

Author

Perrine Batude, Alexandre Ayres, Laurent Brunet, Olivier Rozeau, Maud Vinet, Bertrand Borot, Laurent Fesquet, STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
010302 applied physics, Computer science, variability, 3-D integration, Spice, Monte Carlo method, Design flow, 3-D very large-scale inte- gration (VLSI), Unified Model, Integrated circuit, SRAM, 01 natural sciences, Electronic, Optical and Magnetic Materials, law.invention, noise margins, law, 0103 physical sciences, Netlist, Static random-access memory, Electrical and Electronic Engineering, across-chip variations (ACVs), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Algorithm, Scaling, Monte Carlo (MC)
Abstract

International audience; Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin.

Published
2019

9. Novel fine-grain back-bias assist techniques for 3D-monolithic 14 nm FDSOI top-tier SRAMs

Author

Francois Andrieu, Joris Lacord, R. Berthelon, Laurent Brunet, A. Makosiej, Olivier Weber, C. Fenouillet-Beranger, X. Garros, G. Cibrario, D. Lattard, J.-P. Colinge, J. Cluzel, Lorenzo Ciampolini, D. Bosch, Perrine Batude, F. Balestra, and Bastien Giraud

Subjects
010302 applied physics, Hardware_MEMORYSTRUCTURES, Computer science, Transistor, Spice, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Capacitance, Electronic, Optical and Magnetic Materials, law.invention, Reduction (complexity), Planar, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Materials Chemistry, Electronic engineering, Static random-access memory, Back bias, Electrical and Electronic Engineering, 0210 nano-technology, Access time
Abstract

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD = 0.8 V and a reduction of minimum operating voltage Vmin by 60 mV (up to 92 mV with speed penalty) at 6σ w.r.t. planar SRAMs.

Published
2020

10. Performance and Reliability of a Fully Integrated 3D Sequential Technology

Author

M. Vinet, M. Casse, F. Gaillard, Perrine Batude, Gerard Ghibaudo, A. Tsiara, C. Fenouillet-Beranger, K. Triantopoulos, Laurent Brunet, X. Garros, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Nano 2017, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), and ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010)

Subjects
010302 applied physics, Computer science, Transistor, Process (computing), 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, PMOS logic, law.invention, Reliability engineering, Reliability (semiconductor), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Inverter, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, NMOS logic
Abstract

session T7: Process and Material Technology; International audience; We investigate in detail, for the first time, both performance and reliability of a 3D sequential integration process. It is clearly demonstrated that the top level transistor can be successfully processed at 630°C with almost no impact on the performance and reliability of the bottom level. It is also highlighted that top level devices meet the P&NBTI reliability requirements. Finally an example of successful and robust 3D logic integration is proposed based on a 3D inverter combining a top-level PMOS with a bottom-level NMOS.

Published
2018

11. Breakthroughs in 3D Sequential technology

Author

C. Scibetta, S. Beaurepaire, F. Fournel, A. Roman, S. Chevalliez, C. Fenouillet-Beranger, X. Garros, Xavier Federspiel, J. Aubin, V. Larrey, Perrine Batude, F. Kouemeni-Tchouake, F. Ponthenier, J-B. Pin, Daniel Scevola, Lucile Arnaud, F. Aussenac, C. Guerin, P. Acosta-Alba, V. Mazzocchi, Sebastien Kerdiles, H. Fontaine, Shay Reboh, P. Perreau, Sylvain Maitrejean, Laurent Brunet, N. Rambal, M. Vinet, Pascal Besson, Christophe Morales, T. Lardin, V. Balan, Vincent Jousseaume, D. Ney, F. Mazen, and Francois Andrieu

Subjects
010302 applied physics, Materials science, business.industry, Order (ring theory), 02 engineering and technology, Epitaxy, 01 natural sciences, Active devices, 020202 computer hardware & architecture, Design for manufacturability, Reliability (semiconductor), CMOS, Surface preparation, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Wafer, business
Abstract

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $\mathrm{T}_{\text{TOP}}=500^{\circ}\mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

Published
2018
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12. A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit

Author

Laurent Brunet, R. Fournel, Perrine Batude, Sebastien Thuries, O. Billoint, M. Vinet, D. Lattard, C. Fenouillet-Beranger, and Francois Andrieu

Subjects
010302 applied physics, Digital electronics, Computer science, business.industry, Circuit design, Transistor, 02 engineering and technology, 7. Clean energy, 01 natural sciences, Manufacturing cost, 020202 computer hardware & architecture, law.invention, CMOS, law, Logic gate, 0103 physical sciences, Process integration, 0202 electrical engineering, electronic engineering, information engineering, Benchmark (computing), Electronic engineering, business
Abstract

In this paper, we review the main opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. Simulation results show that 3D monolithic integration can provide up to 30% power reduction at iso-performance and 30% manufacturing cost saving for digital circuits, compared to planar technology, making it an attractive alternative to the straightforward technology scaling. We benchmark the transistor-level and cell-level 3D-monolithic integrations, where the inter-tier vias (3D-contacts) are used intra-cell or inter-cell, respectively. On the one hand, transistor-level 3D-integration can be seen as a full-custom approach, both in terms of technology and circuit design. It promises more performance but at the expense of strong Design/Technology Co-Optimizations. On the other hand, the cell-level 3D-integration ensures a 50% area reduction and a re-use of the technology/design platform. The main technology challenge relative to this integration is the thermal budget constraint of the top-level process integration and the intermediate Back-End-Of-Line (iBEOL) stability. Finally, the total isolation of the top-level transistors integrated in 3D-monolithic raises new opportunities and offers new functionalities like for example an efficient dynamic back-biasing capability.

Published
2018
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13. Thermal effects in 3D sequential technology

Author

C. Fenouillet-Beranger, Perrine Batude, M. Casse, B. Mathieu, G. Reimbold, Gerard Ghibaudo, Laurent Brunet, M. Vinet, K. Triantopoulos, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), nano 2017, and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Work (thermodynamics), Materials science, Transistor, Dielectric, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Subthreshold slope, law.invention, law, 0103 physical sciences, Thermal, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, State (computer science), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Communication channel
Abstract

session 7: Characterization, Reliability, and Yield: Reliability of Advanced Devices (7.6); International audience; We present for the first time an experimental study of thermal effects in 3D sequential integration, including Self-Heating Effect (SHE) and thermal coupling between the two levels of ultra-thin body FDSOI transistors. We extracted a large set of experimental data using different thermometry techniques, and different heater-sensor configurations allowed by this specific stacked integration. We described SHE in top and bottom transistor levels, as well as the influence of a transistor in ON state on a transistor stacked above or below. At the same time, we provide for the first time an experimental validation that the temperature increase given by gate resistance thermometry technique is equal to the temperature in the channel given by the subthreshold slope. Finally, this work can be also used to manage thermal effects for logic or analog applications, and help further optimization of 3D sequential integrated circuits through both technology and design solutions.

Published
2017

14. Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

Author

C. Fenouillet-Beranger, Perrine Batude, G. Cibrario, G. Tricaud, R. Boumchedda, Pierre Morin, Franck Arnaud, Laurent Brunet, O. Rozeau, Bastien Giraud, Sebastien Thuries, M. Vinet, Joris Lacord, R. Berthelon, S. Guissi, D. Fried, B. Mathieu, O. Billoint, Francois Andrieu, J.-P. Noel, A. Ayres de Sousa, and E. Avelar

Subjects
010302 applied physics, Materials science, business.industry, Transistor, Spice, Electrical engineering, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, law.invention, Power (physics), law, Logic gate, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Inverter, Static random-access memory, business, Low voltage, Voltage
Abstract

We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (Ion) / OFF-state current (I off ) tradeoff than in single-gate (SG) mode. Moreover, a 3D-shared contact between a top and bottom electrode is experimentally demonstrated; paving the way for a local back gate, possibly connected with the top gate by a 3D-shared contact. Assuming such a construct, we have performed extensive layout and spice simulations of standard cells and SRAMs. We evidence that the back-gate overlap on the source and drain must be minimized to mitigate the parasitic capacitances. The best layout configurations of a loaded 1-finger inverter yields a 24% frequency gain at a given static power and V dd = 0.6V supply voltage, compared to SG, or to a static power divided by 5, compared to SG under Forward Body Bias (FBB). These performance boosts may be obtained without any area penalty and assuming a 20nm-thin BOX. Similarly, a 29% improvement of the read and write currents of 6T SRAMs is contemplated at V dd = 0.8V. Such new functionality provided by 3D-monolithic even enables making 4T SRAMs that are fully functional at V dd = 0.8V by improving their retention and, in turn, the maximum number of bitcells per column from 50 (SG) to 300 with a dynamic back-bias.

Published
2017

15. Self-heating assessment and cold current extraction in FDSOI MOSFETs

Author

C. Fenouillet-Beranger, Laurent Brunet, Perrine Batude, K. Triantopoulos, G. Reimbold, Gerard Ghibaudo, Mikael Casse, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Nano 2017, and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Materials science, business.industry, Thermal resistance, Transistor, 01 natural sciences, PMOS logic, Ion, law.invention, law, 0103 physical sciences, Thermal, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Current (fluid), Thin film, business, NMOS logic
Abstract

session: Modeling and Characterization; International audience; We present an experimental study of thermal effects in thin film FDSOI MOSFETs, with a focus on the impact of self-heating effect (SHE) on drain current. We have performed thermal resistance extraction using the gate thermometry method, and calculated the resulting cold drain current (Id0), i.e. without SHE. We demonstrate that SHE is more pronounced in shorter and narrower devices without essential differences between nMOS and pMOS transistors. Our experiments show that although the temperature increases significantly in the channel due to SHE, its effect on the ION performances could be limited at operating voltage.

Published
2017

16. Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells

Author

Perrine Batude, Vincent Lu Cao-Minh, Claire Fenouillet-Beranger, Sebastien Thuries, Laurent Brunet, O. Billoint, Cristiano Santos, B. Mathieu, G. Cibrario, Francois Andrieu, M. Brocard, and Jean-Philippe Colonna

Subjects
010302 applied physics, Standard cell, Materials science, Circuit design, Spice, Transistor, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, PMOS logic, law.invention, Operating temperature, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Transient (oscillation), 0210 nano-technology, NMOS logic
Abstract

This study focuses on temperature deviation during operation of transistors inside a monolithic 3D standard cell built on two tiers. Early assessment of this topic is crucial to manage circuit design and requires both steady-state and transient thermal analysis at transistor level. A representative 3D standard cell in 14nm FDSOI technology is considered, using intermediate Back-End-Of-Line (iBEOL) and top tier BEOL. Steady-state and transient power dissipations in NMOS and PMOS are extracted from SPICE simulations with variables such as output load capacitance and operating temperature. 3D thermal simulations are then performed to assess the impact of design parameters such as routing densities, thicknesses of iBEOL and BEOL, their number of metal layers and packaging techniques. Steady-state and transient thermal simulations enable precise analysis to correlate temperature deviation of transistors with these parameters. Design guidelines are provided to limit the temperature deviation between top and bottom tier which can reach 7°Celsius during circuit operations in the worst case

Published
2017

17. Key process steps for high performance and reliable 3D Sequential Integration

Author

J. Micoud, C.-M. V. Lu, Maud Vinet, Charles Leroux, Xavier Federspiel, R. Gassilloud, Perrine Batude, Laurent Brunet, Vincent Delaye, G. Romano, L. Pasini, Xavier Garros, F. Deprat, Claude Tabone, D. Nouguier, N. Rambal, Bernard Previtali, P. Besombes, D. Ney, D. Barge, Francois Andrieu, A. Toffoli, M.-P. Samson, Thomas Skotnicki, A. Tsiara, and Claire Fenouillet-Beranger

Subjects
010302 applied physics, chemistry, Computer science, Logic gate, 0103 physical sciences, Process integration, Electronic engineering, Gate stack, chemistry.chemical_element, 010502 geochemistry & geophysics, Tin, 01 natural sciences, 0105 earth and related environmental sciences
Abstract

This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550°C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration.

Published
2017

18. Recent advances in low temperature process in view of 3D VLSI integration

Author

N. Rambal, C. Fenouillet-Beranger, X. Garros, G. Cibrario, M.-P. Samson, B. Mathieu, Fabrice Nemouchi, Perrine Batude, C. Guerin, C. Leroux, Laurent Brunet, C-M. V. Lu, Sebastien Kerdiles, O. Billoint, Daniel Benoit, M. Brocard, J. Micout, R. Gassilloud, M. Vinet, Pascal Besson, Bernard Previtali, Christian Arvet, L. Pasini, Sebastien Thuries, V. Lapras, Francois Andrieu, Virginie Loup, F. Deprat, P. Acosta-Alba, V. Beugin, V. Mazzocchi, P. Besombes, and J.M. Hartmann

Subjects
010302 applied physics, Very-large-scale integration, Materials science, Fabrication, Annealing (metallurgy), Gate stack, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Dopant Activation, 021001 nanoscience & nanotechnology, Epitaxy, 01 natural sciences, Engineering physics, chemistry.chemical_compound, chemistry, Logic gate, 0103 physical sciences, Silicide, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, 0210 nano-technology
Abstract

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

Published
2016

19. Ns laser annealing for junction activation preserving inter-tier interconnections stability within a 3D sequential integration

Author

Bernard Previtali, Laurent Brunet, B. Mathieu, Perrine Batude, J-P. Nieto, L. Pasini, Pascal Besson, I. Toque-Tresonne, F. Aussenac, Fulvio Mazzamuto, P. Acosta-Alba, Sebastien Kerdiles, Karim Huet, J.M. Hartmann, M.-P. Samson, N. Rambal, F. Ibars, R. Kachtouli, M. Vinet, V. Lapras, C. Fenouillet-Beranger, and A. Roman

Subjects
010302 applied physics, Materials science, Dopant, Silicon, Annealing (metallurgy), business.industry, Recrystallization (metallurgy), chemistry.chemical_element, 02 engineering and technology, Nanosecond, 021001 nanoscience & nanotechnology, Laser, 01 natural sciences, Semiconductor laser theory, law.invention, chemistry, law, 0103 physical sciences, Electronic engineering, Optoelectronics, Process window, 0210 nano-technology, business
Abstract

In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF2). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.

Published
2016

20. Opportunities brought by sequential 3D CoolCube™ integration

Author

Cristiano Santos, Daniel Gitlin, M. Brocard, G. Berhault, Jessy Micout, Sebastien Thuries, Perrine Batude, Laurent Brunet, Fabien Clermidy, C.-M. V. Lu, Paul Besombes, Francois Andrieu, O. Billoint, Maud Vinet, G. Cibrario, F. Deprat, Claire Fenouillet-Beranger, Vincent Mazzochi, O. Faynot, N. Rambal, and Bernard Previtali

Subjects
010302 applied physics, Very-large-scale integration, Engineering, business.industry, Transistor, Power saving, Electrical engineering, 02 engineering and technology, Transistor scaling, 01 natural sciences, 020202 computer hardware & architecture, law.invention, Reduction (complexity), CMOS, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, business
Abstract

3D VLSI with a CoolCube™ monolithic integration flow allows vertically stacking several layers of devices with a unique connecting via density above tens of million/mm2. This results in increased devices density and gains in power and performance thanks to wire-length reduction without the extra cost associated to transistor scaling. In addition to power saving, this true 3D integration opens perspectives in terms of heterogeneous integration. We will review the opportunities brought by CoolCube™ and will present the most advanced technological demonstration of 3D CMOS over CMOS CoolCube™ integration.

Published
2016

21. High performance CMOS FDSOI devices activated at low temperature

Author

Louis Hutin, J. Mazurier, D. Barge, L. Pasini, Olivier Weber, Frédéric Mazen, F. Piegas Luce, Claire Fenouillet-Beranger, M. Vinet, Antoine Cros, E. Ghegin, B. Mathieu, S. Chhun, J. Borrel, Frederic Boeuf, Quentin Rafhay, Anthony Payet, Michel Haond, Perrine Batude, M. Casse, Fuccio Cristiano, Benoit Sklenard, Zineb Saghi, Joris Lacord, D. Blachier, J.P. Barnes, Gerard Ghibaudo, Francois Andrieu, V. Mazzocchi, N. Rambal, J. Micout, Vincent Delaye, V. Lapras, Laurent Brunet, R. Daubriac, Pascal Besson, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Équipe Matériaux et Procédés pour la Nanoélectronique (LAAS-MPN), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Nano 2017, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
010302 applied physics, Materials science, business.industry, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, PMOS logic, CMOS, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [PHYS.COND.CM-MS]Physics [physics]/Condensed Matter [cond-mat]/Materials Science [cond-mat.mtrl-sci], Optoelectronics, business, NMOS logic
Abstract

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

Published
2016

22. First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

Author

L. Pasini, Perrine Batude, V. Benevent, Maud Vinet, Thomas Signamarcheix, R. Kachtouli, Sébastien Barnola, A. Royer, C. Vizioz, F. Fournel, J.M. Hartmann, G. Romano, N. Allouti, Sebastien Kerdiles, Christophe Morales, A. Seignard, C. Agraffeil, Frederic Boeuf, F. Ponthenier, Vincent Delaye, F. Deprat, M. Jourdan, L. Benaissa, L. Baud, C. Euvrard-Colnat, O. Faynot, Bernard Previtali, C. Guedj, P. Besombes, C. Comboroure, Claire Fenouillet-Beranger, L. Hortemel, Laurent Brunet, Claude Tabone, Nicolas Posseme, Alain Toffoli, C.-M. V. Lu, Christian Arvet, and Pascal Besson

Subjects
010302 applied physics, Very-large-scale integration, Engineering, business.industry, Electrical engineering, Silicon on insulator, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, PMOS logic, Front and back ends, CMOS, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Wafer, business, Metal gate, NMOS logic
Abstract

For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

Published
2016

23. 3DVLSI with CoolCube process: An alternative path to scaling

Author

Maud Vinet, Thomas Signamarcheix, V. Lu, Julie Widiez, Fabien Clermidy, A. Royer, J. Mazurier, M.-P. Samson, F. Piegas-Luce, Fabrice Nemouchi, L. Pasini, J.M. Hartmann, M. Casse, F. Deprat, Laurent Brunet, N. Rambal, Maurice Rivoire, Perceval Coudrain, M. Bidaud, Ogun Turkyilmaz, Hossam Sarhan, F. Ponthenier, G. Ghibaudo, C. Euvard-Colnat, Perrine Batude, Louis Hutin, Sebastien Kerdiles, Claude Tabone, Emmanuel Josse, L. Benaissa, E. Petitprez, Remi Beneyton, Claire Fenouillet-Beranger, L. Hortemel, G. Cibrario, Pascal Besson, A. Seignard, B. Mathieu, F. Fournel, C. Bout, C. Agraffeil, S. Sollier, Michel Haond, O. Billoint, P. Leduc, O. Rozeau, Benoit Sklenard, Sebastien Thuries, Bernard Previtali, O. Faynot, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and ANR-10-EQPX-0030/10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Very-large-scale integration, Materials science, business.industry, Transistor, Stacking, Electrical engineering, 02 engineering and technology, Direct bonding, Dopant Activation, 01 natural sciences, 7. Clean energy, 020202 computer hardware & architecture, law.invention, law, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Process optimization, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Scaling
Abstract

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

Published
2015

24. High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator

Author

M. Vinet, Michel Haond, Claire Fenouillet-Beranger, O. Rozeau, F. Allain, Louis Hutin, Sebastien Kerdiles, B. Mathieu, F. Piegas Luce, Pascal Besson, Shay Reboh, Laurent Brunet, Gerard Ghibaudo, Benoit Sklenard, L. Pasini, M. Casse, N. Rambal, Claude Tabone, D. Lafond, F. Aussenac, Perrine Batude, G. Audoit, S. Martini, Nicolas Bernier, J.M. Hartmann, G. Romano, S. Barraud, V. Barral, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Very-large-scale integration, Fabrication, Materials science, 010308 nuclear & particles physics, 0211 other engineering and technologies, Insulator (electricity), 02 engineering and technology, 01 natural sciences, CMOS, 021105 building & construction, 0103 physical sciences, Scalability, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Performance improvement, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

session 5: 3D Systems and Packaging; International audience; 3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint of 14nm node channel strain preservation. This work concludes that extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.

Published
2015

25. Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length

Author

L. Brevard, Quentin Rafhay, J.M. Hartmann, Mireille Mouis, Claude Tabone, Thierry Poiroux, Cuiqin Xu, Alain Toffoli, Perrine Batude, M. Casse, C. Le Royer, F. Allain, A. Pakfar, O. Faynot, Laurent Brunet, Benjamin Colombeau, Benoit Sklenard, F.A. Khaja, Bernard Previtali, A. Pouydebasque, Clement Tavernier, R. Kies, X. Garros, J. Mazurier, M. Vinet, S. Morvan, J. Berthoz, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Varian Inc., This work was partly supported by the French National Research Agency (ANR) through Carnot funding and by the ST-IBM-LETI Alliance program., and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, Dopant, business.industry, Annealing (metallurgy), Transistor, Electrical engineering, Silicon on insulator, Short-channel effect, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, law.invention, Ion implantation, law, Logic gate, 0103 physical sciences, Optoelectronics, Field-effect transistor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

International audience; For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.

Published
2010

26. A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

Author

M. Ribotta, C. Vizioz, X. Garros, J.-M. Pedini, Joris Lacord, Perrine Batude, Sebastien Kerdiles, J. Arcamone, D. Bosch, Benoit Sklenard, A. Tavernier, Maud Vinet, L. Brevard, R. Gassilloud, A. Magalhaes-Lucas, P. Acosta-Alba, Laurent Brunet, J. Kanyandekwe, Francois Andrieu, M. Casse, Pascal Besson, Claire Fenouillet-Beranger, C. Cavalcante, V. Lapras, and Frédéric Mazen

Subjects
010302 applied physics, Materials science, business.industry, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Electronic, Optical and Magnetic Materials, PMOS logic, Back end of line, CMOS, 0103 physical sciences, Optoelectronics, Wafer, Field-effect transistor, Electrical and Electronic Engineering, 0210 nano-technology, business, Front end of line, NMOS logic
Abstract

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low- ${k}$ (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.

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27. All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors

Author

Xavier Garros, Benoit Sklenard, Laurent Brunet, C. Vizioz, J.M. Hartmann, Francois Andrieu, R. Kies, J. Cluzel, Joris Lacord, J.-P. Colinge, D. Bosch, Sylvain Barraud, Claire Fenouillet-Beranger, Gerard Ghibaudo, Perrine Batude, G. Audoit, and F. Balestra

Subjects
010302 applied physics, Physics, Dopant, Condensed matter physics, Subthreshold conduction, Doping, Transistor, Silicon on insulator, Thermal conduction, 01 natural sciences, law.invention, Impurity, law, Logic gate, 0103 physical sciences
Abstract

We evidence a unique feature of junctionless Fully-Depleted Silicon-On-Insulator (JL FDSOI) transistors: the presence of both bulk and accumulation conduction renders standard VT-variability studies incomplete. For JL transistors, we rather propose an original analysis of the (local and global) variability in all-operation-regimes, from subthreshold to accumulation. We evidence that the current variability around VT is highly sensitive to back-bias VB and film thickness $(\mathrm{t}_{\mathrm{si}})$ uniformity. We demonstrate experimentally for the first time up to 70% lower drain current (ID) local variability for Junctionless Accumulation Mode (JAM) vs. inversion mode (IM) at 1V gate voltage (V G), $\mathrm{L}=18$ nm gate length and $\mathrm{W}=20\mathrm{nm}$ width. This is attributed to the impurity screening, lowering the impact of Random Dopant Fluctuations variability.

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28. Low temperature high voltage analog devices in a 3D sequential integration

Author

O. Rozeau, Perrine Batude, C. Fenouillet-Beranger, Gerard Ghibaudo, X. Garros, C. Cavalcante, Joris Lacord, Christoforos G. Theodorou, A. Tataridou, F. Allain, G. Romano, F. Gaillard, Laurent Brunet, T.A. Karatsori, Francois Andrieu, M. Vinet, M. Casse, N. Rambal, R. Gassilloud, J.-P. Colinge, F. Ponthenier, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Materials science, Negative-bias temperature instability, 010308 nuclear & particles physics, business.industry, Annealing (metallurgy), Gate stack, High voltage, 01 natural sciences, [SPI.TRON]Engineering Sciences [physics]/Electronics, Logic gate, 0103 physical sciences, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, ComputingMilieux_MISCELLANEOUS
Abstract

We built an original stackable 2.5V device on FDSOI with analog performance comparable to high temperature reference and passing the PBTI reliability criteria. In depth characterization of low temperature (LT) gate stack devices with thick EOT are investigated, enabling to draw guidelines for future optimization. This paper demonstrates the feasibility of LT high V DD analog devices, which can be used for sensor read out operation, paving the way to ultraminiaturized smart sensor arrays.

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29. 3D Sequential Integration: Application-driven technological achievements and guidelines

Author

C. Comboroure, M. Zussy, L. Pasini, N. Rambal, J.-B. Pin, François Martin, V. Balan, Perrine Batude, C. Vizioz, J.M. Hartmann, Virginie Loup, N. Allouti, Sébastien Barnola, A. Duboust, Frédéric Mazen, O. Faynot, Louis Hutin, Mazzocchi, R. Berthelon, A. Ayres, Gilles Sicard, F. Deprat, Sebastien Hentz, J.-P. Colinge, Francois Andrieu, B. Mathieu, S. Beaurepaire, J. Micout, F. Ponthenier, E. Vianello, F. Fournel, O. Rozeau, E. Avelar Mercado, V. Ripoche, V. Beugin, Cristiano Santos, M.-P. Samson, Pascal Vivet, D. Larmagnac, S. Barraud, C. Euvrard-Colnat, Sebastien Kerdiles, M. Vinet, Benoit Sklenard, P. Acosta Alba, Sebastien Thuries, C. Fenouillet-Beranger, Philippe Rodriguez, X. Garros, Fabrice Nemouchi, R. Gassilloud, O. Billoint, Julien Arcamone, Pascal Besson, Didier Lattard, M. Casse, Laurent Brunet, C.-M. V. Lu, and Bernard Previtali

Subjects
010302 applied physics, Materials science, Silicon, Interface (computing), Stacking, chemistry.chemical_element, Ranging, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, 7. Clean energy, Engineering physics, Annealing (glass), chemistry, 0103 physical sciences, Thermal, Hardware_INTEGRATEDCIRCUITS, Field-effect transistor, Thermal stability, 0210 nano-technology
Abstract

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (

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