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52 results on '"Fdsoi"'

1. Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Author

Sergej Makovejev, Denis Flandre, Arka Halder, Jean-Pierre Raskin, Valeriya Kilchytska, Lucas Nyssens, Babak Kazemi Esfeh, and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
Computer science, Frequency band, Nanowire, Silicon on insulator, 02 engineering and technology, Analog and RF figures of merit, 01 natural sciences, Original research, MOSFET, 0103 physical sciences, Electronic engineering, Electrical and Electronic Engineering, S-parameters, FDSOI, FinFET, Self-heating, UTBB, 010302 applied physics, self-heating, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, Characterization (materials science), TK1-9971, Logic gate, Radio frequency, Electrical engineering. Electronics. Nuclear engineering, 0210 nano-technology, Biotechnology
Abstract

This review paper assesses the main approaches in the electrical characterization of advanced MOSFETs towards their future analog and RF applications. Those approaches are shown to be different from the traditionally used ones for the assessment of the device perspectives for digital applications. Based on the original research realized by our group over the last years, advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as Fully Depleted Silicon-on-Insulator (FDSOI), FinFETs and NanoWires (NW) in a wide temperature range (from cryogenic, 4 K up to 250°C). A wide frequency band characterization (from DC up to hundred GHz range) will be positioned as a key element enabling a fair device assessment towards analog and RF applications. Importance of the “extrinsic” parasitic elements in the advanced devices is enormous, sometimes even dominating the device performance. Therefrom arises the need for a proper separate extraction and discussion of “intrinsic” versus “extrinsic” parameters.

Published
2021

2. Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

Author

Hyun-Chul Choi, Rock-Hyun Baek, Jinsu Jeong, Hyeok Yun, Seunghwan Lee, and Jun-Sik Yoon

Subjects
Materials science, neural network, Silicon on insulator, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, 14-nm node, Topology, 01 natural sciences, transistor optimization, law.invention, law, 0103 physical sciences, Machine learning, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, 010302 applied physics, TCAD, Artificial neural network, Backpropagation, FDSOI, Electronic, Optical and Magnetic Materials, Logic gate, Node (circuits), Field-effect transistor, lcsh:Electrical engineering. Electronics. Nuclear engineering, Gradient descent, lcsh:TK1-9971, Biotechnology
Abstract

In this article, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC). Using machine learning method, the neural network accurately predicted the electrical behaviors of 14-nm node FDSOI FETs. Also by using backpropagation and gradient descent method, the device structures were modified to improve on/off current ratios for high performance (HP), low operating power (LOP), and low stand-by power (LSTP) applications. These optimized structures were secured within the process range of conventional FDSOI FETs. Among the optimized parameters, drain-side spacer length ( $L_{spd}$ ), source/drain junction gradient ( $L_{sdj}$ ), and thickness of source/drain epi ( $T_{sd}$ ) showed different behaviors for each application and thickness of buried oxide ( $T_{box}$ ) was maximal in optimization results. The detailed physical analysis was conducted to evaluate these parameters for each application. The neural network based optimization was powerful and efficient while saving time and cost in device design.

Published
2020
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3. 28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

Author

Michel Haond, Valeria Kilchytska, B. Kazemi Esfeh, J-P Raskin, Denis Flandre, Nicolas Planes, and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
010302 applied physics, Materials science, Equivalent series resistance, business.industry, Transconductance, 02 engineering and technology, Liquid nitrogen, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Cutoff frequency, Electronic, Optical and Magnetic Materials, 0103 physical sciences, Materials Chemistry, Figure of merit, Optoelectronics, FDSOI, UTBB MOSFETs, Analog and RF Figures of Merit (FoM), Cryogenic temperature, Mobility, Series resistance, Electronics, Electrical and Electronic Engineering, 0210 nano-technology, Drain current, business, Cmos process
Abstract

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).

Published
2019
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4. Lambert-W Function-based Parameter Extraction for FDSOI MOSFETs Down to Deep Cryogenic Temperatures

Author

Mikael Casse, L. Contamin, B. Cardoso Paz, F. Serra di Santa Maria, F. Balestra, Gerard Ghibaudo, Christoforos G. Theodorou, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Laboratoire d'électronique et des technologies de l'Information [Sfax] (LETI), and École Nationale d'Ingénieurs de Sfax | National School of Engineers of Sfax (ENIS)

Subjects
Materials science, Lambert-W function, 01 natural sciences, law.invention, 03 medical and health sciences, symbols.namesake, MOSFET, law, Lambert W function, 0103 physical sciences, Materials Chemistry, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010306 general physics, ComputingMilieux_MISCELLANEOUS, Independence (probability theory), 030304 developmental biology, parameter extraction, 0303 health sciences, cryogenic temperature. 2/16, Condensed matter physics, Liquid helium, Scattering, Function (mathematics), Condensed Matter Physics, FDSOI, Electronic, Optical and Magnetic Materials, symbols, AND gate, Communication channel
Abstract

International audience; The applicability of the Lambert-W function-based parameter extraction methodology is demonstrated for 28nm FDSOI MOSFETs down to deep cryogenic temperatures (4.2K). The Lambert-W function enables to accurately model the inversion charge and drain current MOSFET characteristics from weak to strong inversion, while using the classical mobility law down to liquid helium temperature. The main MOSFET parameters were extracted versus temperature and gate length, showing the temperature independence of short channel effects and the strong mobility degradation at short channel length due to increased neutral defect scattering.

Published
2021
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5. A New Mixed Hardening Methodology applied to a 28nm FDSOI 32-bits DSP Subjected to Gamma Radiation

Author

J.M. Armani, Philippe Dollfus, A. Urena Acuna, I. Miro-Panades, Mariem Slimani, Armani, Jean-Marc, Laboratoire Fiabilité et Intégration de Capteurs (LFIC), Département Métrologie Instrumentation & Information (DM2I), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay-Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay, Centre de Nanosciences et de Nanotechnologies (C2N), Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay-Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), IMS laboratory, University of Bordeaux, LAAS-CNRS, University of Toulouse – Bordeaux, Laboratoire Systèmes-sur-puce et Technologies Avancées (LSTA), Université Grenoble Alpes (UGA)-Département Systèmes et Circuits Intégrés Numériques (DSCIN), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA))

Subjects
diagnosis, Integrated circuit, 01 natural sciences, 030218 nuclear medicine & medical imaging, law.invention, Compensation (engineering), performance degradation, electrical compensation, 0302 clinical medicine, law, lifetime of FDSOI integrated circuits, Safety, Risk, Reliability and Quality, nuclear instrumentation, degradation, 010302 applied physics, instrumentation, lifetime, hardening, thermal regeneration, ionizing dose, hardening electronics, gamma-rays, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Absorbed dose, Optoelectronics, ionizing radiation, Materials science, [PHYS.NEXP] Physics [physics]/Nuclear Experiment [nucl-ex], [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Radiation, [PHYS.NEXP]Physics [physics]/Nuclear Experiment [nucl-ex], 03 medical and health sciences, Reliability (semiconductor), 0103 physical sciences, Thermal, Irradiation, [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, reliability, TID, business.industry, Radiation hardening, FDSOI, [SPI.TRON]Engineering Sciences [physics]/Electronics, [PHYS.PHYS.PHYS-INS-DET] Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], business, Hardening (computing)
Abstract

International audience; This work presents the performance degradation of a 32-bit DSP fabricated with 28 nm FDSOI technology subjected to different levels of gamma radiation. A new mixed hardening methodology based on electrical compensation and thermal regeneration is applied to the irradiated devices to recover the degraded electrical characteristics induced by the total ionizing dose. The application of this new methodology seeks to extend the lifetime of FDSOI integrated circuits under high radiation conditions while keeping good reliability.

Published
2021
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6. A Review of Sharp-Switching Band-Modulation Devices

Author

Sorin Cristoloveanu, Joris Lacord, Sébastien Martinie, Carlos Navarro, Francisco Gamiz, Jing Wan, Hassan Dirani, Kyunghwa Lee, and Alexander Zaslavsky

Subjects
sharp switching, ESD, 02 engineering and technology, Review, Hardware_PERFORMANCEANDRELIABILITY, sensors, 01 natural sciences, memory, nanoelectronics, Esaki diode, Memory, 0103 physical sciences, electrostatic doping, ultrathin body, Hardware_INTEGRATEDCIRCUITS, TJ1-1570, Mechanical engineering and machinery, Electrical and Electronic Engineering, 010302 applied physics, SOI, reconfigurable device, Sensors, Mechanical Engineering, Reconfigurable device, band modulation, Nanoelectronics, 021001 nanoscience & nanotechnology, FDSOI, Electrostatic doping, Control and Systems Engineering, Band modulation, Sharp switching, 0210 nano-technology, Ultrathin body, Hardware_LOGICDESIGN
Abstract

The European authors are grateful for support from the EU project REMINDER (H2020-687931). Alexander Zaslavsky acknowledges the support of the U.S. National Science Foundation (award QII-TACS-1936221)., This paper reviews the recently-developed class of band-modulation devices, born from the recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body technologies, which have enabled the concept of gate-controlled electrostatic doping. In a lateral PIN diode, two additional gates can construct a reconfigurable PNPN structure with unrivalled sharp-switching capability. We describe the implementation, operation, and various applications of these band-modulation devices. Physical and compact models are presented to explain the output and transfer characteristics in both steady-state and transient modes. Not only can band-modulation devices be used for quasi-vertical current switching, but they also show promise for compact capacitorless memories, electrostatic discharge (ESD) protection, sensing, and reconfigurable circuits, while retaining full compatibility with modern silicon processing and standard room-temperature low-voltage operation., EU project REMINDER H2020-687931, National Science Foundation (NSF) QII-TACS-1936221

Published
2021

7. 28-nm FDSOI nMOSFET RF Figures of Merits and Parasitic Elements Extraction at Cryogenic Temperature Down to 77 K

Author

Michel Haond, Valeriya Kilchytska, Jean-Pierre Raskin, Babak Kazemi Esfeh, Denis Flandre, Nicolas Planes, and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
UTBB MOSFETs, 02 engineering and technology, Cryogenics, 01 natural sciences, RF figures of merit (FoM), Parasitic elements, 0103 physical sciences, MOSFET, Figure of merit, Parasitic extraction, Electrical and Electronic Engineering, RF Figures of Merit (FoM), 010302 applied physics, Physics, Oscillation, business.industry, cryogenic temperature, Cryogenic temperature, parasitic elements, 021001 nanoscience & nanotechnology, Cutoff frequency, FDSOI, Electronic, Optical and Magnetic Materials, Equivalent circuit, Optoelectronics, Radio frequency, lcsh:Electrical engineering. Electronics. Nuclear engineering, 0210 nano-technology, business, lcsh:TK1-9971, Biotechnology
Abstract

This paper presents detailed RF characterization of 28-nm FDSOI nMOSFETs at cryogenic temperatures down to 77 K. Two main RF figures of merit (FoM), i.e., current gain cutoff frequency ( $f_{T}$ ) and maximum oscillation frequency ( $f_{\max }$ ), as well as elements of small-signal equivalent circuit are extracted from the measured S-parameters. Increases of $f_{\textit T}$ and $f_{\max }$ by about 85 GHz and about 30 GHz, respectively, are demonstrated at 77 K. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This paper suggests 28-nm FDSOI as a good candidate for future cryogenic applications.

Published
2019

8. Process Dependence of Soft Errors Induced by Alpha Particles, Heavy Ions, and High Energy Neutrons on Flip Flops in FDSOI

Author

Kazutoshi Kobayashi, Kentaro Kojima, Mitsunori Ebara, Kodai Yamada, and Jun Furuta

Subjects
Materials science, Silicon, Silicon on insulator, chemistry.chemical_element, Substrate (electronics), 01 natural sciences, law.invention, neutron, law, 0103 physical sciences, Work function, Neutron, Soft error, Electrical and Electronic Engineering, α particle, 010302 applied physics, 010308 nuclear & particles physics, business.industry, Transistor, flip flop, Alpha particle, heavy ion, FDSOI, Electronic, Optical and Magnetic Materials, Threshold voltage, chemistry, Optoelectronics, lcsh:Electrical engineering. Electronics. Nuclear engineering, business, lcsh:TK1-9971, Biotechnology
Abstract

Soft-error tolerance depending on threshold voltage of transistors was evaluated by $\alpha $ -particle, heavy-ion, and neutron irradiation. Three chips were fabricated, one embeds low-threshold general-purpose (GP) transistors and the others embed high-threshold low-power (LP) transistors in a 65 nm fully depleted silicon on insulator (FDSOI) process. There were a few errors on LPDFFs (DFFs with LP transistors). Error probability (EP) of LPDFFs was 99.88% smaller than that of GPDFFs (DFFs with GP transistors) by $\alpha $ particles. Average cross sections (CSs) of LPDFFs by heavy ions were 50% smaller than those of GPDFFs. Average soft-error rates (SERs) of LPDFFs by neutrons were 68% smaller than those of GPDFFs. 3-D device simulations revealed that CSs of the LP and GP transistors are changed by fitting methods using the work function of the gate material and doping concentration of the substrate under the BOX layer. The difference is due to the number of carriers in diffusion and silicon thickness of the raised layer above drain and source terminals.

Published
2019

9. External Resistor-Free Gate Configuration Phase Transition FDSOI MOSFET

Author

Changhwan Shin and Jaemin Shin

Subjects
Phase transition, Materials science, steep switching devices, threshold selector, Silicon on insulator, 02 engineering and technology, 01 natural sciences, law.invention, law, 0103 physical sciences, MOSFET, Electrical and Electronic Engineering, 010302 applied physics, business.industry, Transistor, Phase transition FET, 021001 nanoscience & nanotechnology, Subthreshold slope, FDSOI, Electronic, Optical and Magnetic Materials, Threshold voltage, Logic gate, Optoelectronics, lcsh:Electrical engineering. Electronics. Nuclear engineering, 0210 nano-technology, business, lcsh:TK1-9971, Biotechnology, Voltage
Abstract

Gate configuration phase transition fully depleted silicon-on-insulator (FDSOI) metal- oxide-semiconductor field-effect transistor (MOSFET) without an external resistor is proposed using Pb(Zr0.52Ti0.48)O3 (PZT)-based threshold selector (TS). Under 1 μA compliance current condition, the PZT-based TS exhibits its threshold switching property at ~0.9 V (threshold voltage) and ~0.01 V (hold voltage) over 4 orders of current. And its off-resistance is measured as ~2.3 × 1011 Ω. The PZT-based gate configuration phase transition FDSOI MOSFET without an external resistor was fabricated by connecting the PZT-based TS to a baseline FDSOI MOSFET. It is confirmed that the fabricated external resistor-free phase transition FDSOI MOSFET can operate regardless of the aforementioned 1 μA of compliance current condition. This device has not only demonstrated the feature of ~4 mV/decade subthreshold slope at ~0.96 V of gate voltage, but it also has decreased the gate leakage current of the baseline FDSOI MOSFET by ~10 times at 0 V of gate voltage and ~320 times at 2 V of gate voltage.

Published
2019

10. Self-Heating in FDSOI UTBB MOSFETs at Cryogenic Temperatures and Its Effect on Analog Figures of Merit

Author

Jean-Pierre Raskin, Michel Haond, Arka Halder, Lucas Nyssens, Babak Kazemi Esfeh, Valeriya Kilchytska, Nicolas Planes, Denis Flandre, and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
analog figures of merit, Materials science, Thermal resistance, Silicon on insulator, 02 engineering and technology, Cryogenics, 01 natural sciences, UTBB, MOSFET, 0103 physical sciences, Figure of merit, S-parameters, Electrical and Electronic Engineering, 010302 applied physics, FDSOI, Self-heating, Analog figures of merit, business.industry, self-heating, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, Optoelectronics, lcsh:Electrical engineering. Electronics. Nuclear engineering, Radio frequency, 0210 nano-technology, business, Self heating, lcsh:TK1-9971, Order of magnitude, Biotechnology
Abstract

This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K in short-channel devices are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

Published
2020

11. 22nm Ultra-Thin Body and Buried Oxide FDSOI RF Noise Performance

Author

Ousmane Magatte Kane, Francois Danneville, P. Scheiblin, Luca Lucci, Sylvie Lepilliet, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), Advanced NanOmeter DEvices - IEMN (ANODE - IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Subjects
Materials science, Transconductance, Silicon on insulator, Context (language use), 02 engineering and technology, Noise figure, 01 natural sciences, 7. Clean energy, law.invention, [SPI]Engineering Sciences [physics], law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 010302 applied physics, business.industry, CMOS, Transistor, noise measurement, 020206 networking & telecommunications, millimeter wave, CMOS integrated circuits, FDSOI, silicon-on-insulator, millimetre wave circuits, Logic gate, Optoelectronics, low-power electronics, Radio frequency, business
Abstract

International audience; The drastic downscaling of the transistor size along with advances in material sciences allowed the development of low power CMOS technologies with competitive RF figure of merits suitable for millimeter applications. In this context, this paper presents the RF and noise characterization (up to 110 GHz) of an advanced 22 nm UTBB FDSOI technology developed by Globalfoundries. In addition to the excellent DC performance, the technology presents promising RF characteristics. Indeed, a maximum transconductance of 1.78 S/mm and a Fmax of 435 GHz are achieved. The technology also offers a state-of-the-art minimum noise figure (NFmin) of 0.45 dB at 20 GHz (with an associated Gain of 13 dB) for a drain current of 185 mA/mm.

Published
2019
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12. Back-bias impact on variability and BTI for 3D-monolithic 14nm FDSOI SRAMs applications

Author

Francois Andrieu, L. Ciampolini, G. Cibrario, F. Balestra, Joris Lacord, Xavier Garros, Perrine Batude, Laurent Brunet, A. Makosiej, D. Lattard, Bastien Giraud, Maud Vinet, Claire Fenouillet-Beranger, J.-P. Colinge, Olivier Weber, J. Cluzel, D. Bosch, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Computer science, WNM, 02 engineering and technology, 01 natural sciences, SNM, Stress (mechanics), Planar, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Static noise margin, Static random-access memory, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, variability, 020208 electrical & electronic engineering, SRAM margins, 3D-monolithic, FDSOI, Temperature instability, BTI stress, Spatial variability, Back bias, Back/Body Biasing, Voltage, Supply Read Retention Voltage
Abstract

International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltage (VDD) and back bias (Vwell) are extracted. These data evidence that the 14nm SRAM is read-limited, which could be improved by a smart back-bias management [1]. In this work we demonstrate a 50mV Static Noise Margin (SNM) variability improvement (at VDD=0.8V) by back-biasing, without additional Bias Temperature Instability (BTI) stress. Such an assist technique can be eventually leveraged at fine-grain by 3D monolithic integration, owing to local back-planes.

Published
2019
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13. Electrical Characterization of FDSOI by Capacitance Measurements in Gated p-i-n Diodes

Author

Maryline Bawedin, Jacques Cluzel, Sorin Cristoloveanu, Francois Andrieu, Carlos Navarro, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), ANR-11-JS03-0001,AMNESIA,Dispositifs Mémoires Nanométriques Innovants pour Applications Ultra Basse Consommation(2011), European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015), and European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013)

Subjects
Materials science, Capacitance, intergate coupling, Silicon on insulator, 02 engineering and technology, 01 natural sciences, fully depleted (FD), 0103 physical sciences, MOSFET, gated diode, characterization, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, threshold voltage, Diode, SOI, 010302 applied physics, business.industry, p-i-n, 021001 nanoscience & nanotechnology, FDSOI, Electrical contacts, Electronic, Optical and Magnetic Materials, Threshold voltage, Logic gate, Optoelectronics, Transient (oscillation), 0210 nano-technology, business
Abstract

International audience; The versatility of split capacitance measurements on the standard SOI gated p-i-n diodes is presented and discussed. The presence of both n + - and p + -type contacts in the same structure eliminates the floating-body and transient effects, and stands as a major advantage over the conventional MOSFETs characterization. We demonstrate the feasibility of simultaneous electrical (threshold voltage for n- and p-channels) and structural (layer thickness) parameter extraction by systematic measurements and TCAD numerical simulations.

Published
2016
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14. Multisubband ensemble Monte Carlo analysis of tunneling leakage mechanisms in ultrascaled FDSOI, DGSOI, and FinFET devices

Author

Carlos Sampedro, Asen Asenov, Vihar P. Georgiev, Andres Godoy, Toufik Sadi, Cristina Medina-Bailon, Jose L. Padilla, Francisco Gamiz, Luca Donetti, University of Glasgow, Instituto Carlos I de Física Teórica y Computacional, Department of Neuroscience and Biomedical Engineering, Aalto-yliopisto, and Aalto University

Subjects
Multissubband ensemble Monte Carlo (MS-EMC), Monte Carlo method, Gate leakage current, Silicon on insulator, 01 natural sciences, Double-gate silicon on insulator (DGSOI), 0103 physical sciences, gate leakage current, Electrical and Electronic Engineering, Quantum tunnelling, Leakage (electronics), 010302 applied physics, Physics, ta213, Direct source-to-drain tunneling (S/D tunneling), Multi-Subband Ensemble Monte Carlo, business.industry, Band-to-band tunneling (BTBT), direct Source-to-Drain tunneling, band-to-band tunneling, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, DGSOI, FDSOI, Electronic, Optical and Magnetic Materials, Logic gate, FinFET, Optoelectronics, Electric potential, business, Fully depleted silicon on insulator (FDSOI)
Abstract

openaire: EC/H2020/662175/EU//WAYTOGO-FAST Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths.

Published
2019

15. MSDRAM, A2RAM and Z2-FET performance benchmark for 1T-DRAM applications

Author

Mukta Singh Parihar, Jean-Charles Barbe, Francois Tcheme Wakam, Maryline Bawedin, Sorin Cristoloveanu, Carlos Navarro, Joris Lacord, Fransisco Gamiz, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Universidad de Granada = University of Granada (UGR), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and University of Granada [Granada]

Subjects
010302 applied physics, Hardware_MEMORYSTRUCTURES, Computer science, TCAD simulation, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Benchmark, 021001 nanoscience & nanotechnology, 01 natural sciences, FDSOI, Soi substrate, 1T-DRAM, Computational science, memory, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Benchmark (computing), Calibration, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Dram
Abstract

session Memory (12.4); International audience; In this study, we propose a benchmark of performance between three promising 1T-DRAM device structures on SOI substrate: MSDRAM, A2RAM and Z 2 -FET. For a fair comparison, TCAD simulation with the same basic calibration and typical 28FDSOI technological parameters was used. The merits and limitations of each variant are discussed.

Published
2018
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16. New NBTI models for degradation and relaxation kinetics valid over extended temperature and stress/recovery ranges

Author

Mustapha Rafik, Xavier Federspiel, David Roy, Gerard Ghibaudo, D. Nouguier, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Materials science, Scale (ratio), NBTI, Compact model Reliability, Kinetics, 02 engineering and technology, 01 natural sciences, Recovery Stress, Relaxation kinetics, Stress (mechanics), 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Vg recovery, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Safety, Risk, Reliability and Quality, Fast measurement Temperature, 010302 applied physics, Stress recovery, 020208 electrical & electronic engineering, CMOS, Mechanics, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, FDSOI, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Degradation (geology)
Abstract

International audience; In this paper we present NBTI stress and recovery effects measured on PFET devices issued from various FDSOI technologies. NBTI degradation and recovery subsequent to DC stress are measured at the μs time scale. After in-depth analysis of temperature and stress/recovery bias effects, we propose new NBTI models for degradation and recovery kinetics including temperature, Vgstress and Vgrecovery dependencies. These models are finally validated on different technologies and various experimental conditions.

Published
2018
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17. Analog RF and mm-Wave design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA

Author

Andre Juge, Salim El Ghouli, Christophe Lallement, Jean-Michel Sallese, Wladyslaw Grabinski, Laboratoire des sciences de l'ingénieur, de l'informatique et de l'imagerie (ICube), École Nationale du Génie de l'Eau et de l'Environnement de Strasbourg (ENGEES)-Université de Strasbourg (UNISTRA)-Institut National des Sciences Appliquées - Strasbourg (INSA Strasbourg), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Les Hôpitaux Universitaires de Strasbourg (HUS)-Centre National de la Recherche Scientifique (CNRS)-Matériaux et Nanosciences Grand-Est (MNGE), Université de Strasbourg (UNISTRA)-Université de Haute-Alsace (UHA) Mulhouse - Colmar (Université de Haute-Alsace (UHA))-Institut National de la Santé et de la Recherche Médicale (INSERM)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Université de Strasbourg (UNISTRA)-Université de Haute-Alsace (UHA) Mulhouse - Colmar (Université de Haute-Alsace (UHA))-Institut National de la Santé et de la Recherche Médicale (INSERM)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Réseau nanophotonique et optique, and Université de Strasbourg (UNISTRA)-Université de Haute-Alsace (UHA) Mulhouse - Colmar (Université de Haute-Alsace (UHA))-Centre National de la Recherche Scientifique (CNRS)-Université de Strasbourg (UNISTRA)-Centre National de la Recherche Scientifique (CNRS)

Subjects
low-power, Computer science, mosfet, double-gate fets, 02 engineering and technology, Integrated circuit, 01 natural sciences, law.invention, lna, law, 0103 physical sciences, MOSFET, mm-wave, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Figure of merit, transconductance efficiency, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, fdsoi, device, Electronic circuit, 010302 applied physics, utbb, analog, low-voltage, 020208 electrical & electronic engineering, Low-noise amplifier, Sizing, gm over id, rf, Phase frequency detector, Low voltage
Abstract

The state-of-the art RF and millimeter-wave first-cut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and inaccurate concepts. Moreover, the pessimistic rules of thumb proposed for older bulk technologies are no more useful and lead to overdesign. This work takes advantage of the Moderate Inversion and uses low and high frequency figures of merit to provide a convenient sizing method for a 35 GHz Low Noise Amplifier (LNA) in 28 nm UTBB FDSOI technology.

Published
2018
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18. Kink effect in ultrathin FDSOI MOSFETs

Author

H.G. Choi, Sorin Cristoloveanu, M. Bawedin, Hyungjin Park, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), TCAD team, DMR group, SK Hynix Inc, and European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016)

Subjects
Materials science, Silicon on insulator, 02 engineering and technology, 01 natural sciences, Super-coupling, MOSFET, 0103 physical sciences, Materials Chemistry, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Floating-body effect, Nonlinear Sciences::Pattern Formation and Solitons, Floating body effect, 010302 applied physics, SOI, business.industry, Kink effect, 021001 nanoscience & nanotechnology, Condensed Matter Physics, FDSOI, Electronic, Optical and Magnetic Materials, Body potential, Optoelectronics, lipids (amino acids, peptides, and proteins), 0210 nano-technology, business, Communication channel
Abstract

International audience; Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (

Published
2018
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19. A design-oriented charge-based simplified model for FDSOI MOSFETs

Author

Christian Enz, A. Pezzotta, Louis Hutin, H. Bohuslavskyi, and Farzan Jazaeri

Subjects
010302 applied physics, Physics, 020208 electrical & electronic engineering, Semiconductor device modeling, Silicon on insulator, modeling, back-gate, Charge (physics), Biasing, 02 engineering and technology, 01 natural sciences, FDSOI, Threshold voltage, simplified EKV, Logic gate, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Cmos process
Abstract

In this paper a design-oriented model for asymmetrical double-gate (ADG) MOSFETs is proposed. Including the back-gate effect into the original simplified EKV bulk model requires only one additional parameter to the existing four, and extends the simplified EKV model to FDSOI processes. This will help the designer to find the right trade-off in terms of design parameters, including the back-gate biasing. A comparison with measurement results from a 28-nm FDSOI CMOS process is provided, assessing the excellent accuracy of the proposed.

Published
2018
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20. Characterization of RF Noise in UTBB FD-SOI MOSFET

Author

Avirup Dasgupta, Chenming Hu, Yogendra Sahu, Sourabh Khandelwal, Pragya Kushwaha, and Yogesh Singh Chauhan

Subjects
device modeling, Materials science, Thermal noise, high frequency noise, Noise-figure meter, Silicon on insulator, 02 engineering and technology, Noise figure, 01 natural sciences, Noise (electronics), law.invention, MOSFET, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Flicker noise, Electrical and Electronic Engineering, 010302 applied physics, Noise measurement, business.industry, 020208 electrical & electronic engineering, Transistor, FDSOI, Electronic, Optical and Magnetic Materials, Optoelectronics, RF, lcsh:Electrical engineering. Electronics. Nuclear engineering, business, lcsh:TK1-9971, Biotechnology
Abstract

In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.

Published
2016

21. The Energy and Variability Efficient Era (E.V.E.) is Ahead of Us

Author

Simon Deleonibus

Subjects
Engineering, Distributed computing, CMOS devices, 02 engineering and technology, 01 natural sciences, Reduction (complexity), 0103 physical sciences, Electronic engineering, Electrical and Electronic Engineering, 010302 applied physics, business.industry, variability, scaling, Volume (computing), 021001 nanoscience & nanotechnology, FDSOI, Electronic, Optical and Magnetic Materials, Power (physics), Nanoelectronics, CMOS, Logic gate, energy and power consumption, FinFET, lcsh:Electrical engineering. Electronics. Nuclear engineering, 0210 nano-technology, business, lcsh:TK1-9971, Energy (signal processing), Biotechnology, Efficient energy use
Abstract

Major power consumption reduction will drive future design of technologies and architectures that will request less greedy devices and interconnect systems. The electronic market will be able to face an exponential growth thanks to the availability and feasibility of autonomous and mobile systems necessary to societal needs. The increasing complexity of high volume fabricated systems will be possible if we aim at zero intrinsic variability, and generalize 3-D integration of hybrid, heterogeneous technologies at the device, functional, and system levels. Weighing on the world energy saving balance will be possible and realistic by maximizing the energy efficiency of co-integrated low power and high performance logic and memory devices.The future of nanoelectronics will face the major concerns of being energy and variability efficient.

Published
2016

22. Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk

Author

Louis-Barthelemy Faber, Marie-Lise Flottes, Stephan De Castro, David Hely, Giorgio Di Natale, Regis Leveugle, Paolo Maistri, Bruno Rouzeyre, Athanasios Papadimitriou, Jean-Max Dutertre, Vincent Beroulle, Philippe Gendrier, Philippe Candelier, École des Mines de Saint-Étienne (Mines Saint-Étienne MSE), Institut Mines-Télécom [Paris] (IMT), Laboratoire de Conception et d'Intégration des Systèmes (LCIS), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
Materials science, Silicon on insulator, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, law.invention, Semiconductor laser theory, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Safety, Risk, Reliability and Quality, 010302 applied physics, business.industry, Laser fault injection, Nanosecond, Laser, FDSOI, Electronic, Optical and Magnetic Materials, PACS 8542, CMOS, CMOS Bulk, Picosecond, Optoelectronics, Node (circuits), business, BBICS
Abstract

International audience; Integrated circuits (ICs) laser illumination was originally used for emulation of radioactive ionizing particules effects on that devices. Today, it is also a mean for injecting faults into the computations of secure ICs for the purpose of retrieving secret data. The CMOS FD-SOI technology is expected to be less sensitive to laser fault injection than the more usual CMOS bulk technology. We report in this work an experimental assessment of the interest of using FD-SOI rather than CMOS bulk to decrease laser sensitivity. Our experiments were conducted on test chips at the 28 nm node for both technologies with laser pulse durations in the picosecond and nanosecond ranges. We also discuss the interest of using bulk current sensors along with FD-SOI technology to achieve optimal detection of laser fault injection attempts.

Published
2018
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23. Source-to-Drain Tunneling Analysis in FDSOI, DGSOI, and FinFET Devices by Means of Multisubband Ensemble Monte Carlo

Author

C. Medina-Bailon, Jose L. Padilla, Andres Godoy, Carlos Sampedro, Francisco Gamiz, and Luca Donetti

Subjects
010302 applied physics, Physics, Multi-Subband Ensemble Monte Carlo, Monte Carlo method, Silicon on insulator, direct Source-to-Drain tunneling, Context (language use), 02 engineering and technology, Electron, 021001 nanoscience & nanotechnology, DGSOI, 01 natural sciences, Engineering physics, FDSOI, Electronic, Optical and Magnetic Materials, Logic gate, 0103 physical sciences, FinFET, Electronics, Electrical and Electronic Engineering, 0210 nano-technology, Quantum, Quantum tunnelling
Abstract

The inclusion of quantum effects in the transport direction plays an important role in the extensive research of ultrascaled electronic devices. In this context, it is necessary to study how these phenomena affect different technological architectures in order to conclude which one can be the best candidate to replace standard technology. This paper presents the implementation of direct source-to-drain tunneling effect in a multisubband ensemble Monte Carlo simulator showing its influence in different structures such as fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. The differences in the potential profile and the electron distribution in the subbands for these architectures modify the number of electrons affected by this quantum mechanism and, therefore, their short-channel behavior.

Published
2018

24. Is there a kink effect in FDSOI MOSFETs?

Author

J-A. Martino, Sorin Cristoloveanu, Hyungjin Park, Maryline Bawedin, Katia R. A. Sasaki, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), University of São Paulo (USP), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015), and Universidade de São Paulo = University of São Paulo (USP)

Subjects
Materials science, Silicon, Silicon on insulator, chemistry.chemical_element, 02 engineering and technology, 01 natural sciences, law.invention, MOSFET, kink effect, law, 0103 physical sciences, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Nonlinear Sciences::Pattern Formation and Solitons, 010302 applied physics, SOI, business.industry, Transistor, Electrical engineering, super-coupling, 021001 nanoscience & nanotechnology, FDSOI, Impact ionization, chemistry, Logic gate, Optoelectronics, floating-body effect, Electric potential, 0210 nano-technology, business, Communication channel
Abstract

session poster; International audience; Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (

Published
2017
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25. Impact of access resistance on New-Y function methodology for MOSFET parameter extraction in advanced FD-SOI technology

Author

Quentin Rafhay, Gerard Ghibaudo, Antoine Cros, Jean-Baptiste Henry, Julien Rosa, STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA), CIFRE ST, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
010302 applied physics, Engineering, model, Access resistance, business.industry, Electrical engineering, Silicon on insulator, 02 engineering and technology, Function (mathematics), 021001 nanoscience & nanotechnology, 01 natural sciences, FDSOI, Logic gate, 0103 physical sciences, MOSFET, Electronic engineering, Extraction (military), parameters extraction methodology, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

session 4: Device modelling; International audience; In this work, an upgraded version of the so called New Y function MOSFET parameter extraction methodology is proposed, taking the impact of access resistance into account. This new approach emphasizes the importance of considering access resistance variation with gate bias when extracting MOSFET parameters.

Published
2017
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26. Extra-low parasitic gate-to-contacts capacitance architecture for sub-14nm transistor nodes

Author

D. Bensahel, Yves Morand, Heimanu Niebojewski, O. Rozeau, Marie-Anne Jaud, Emmanuel Dubois, C. Le Royer, Thierry Poiroux, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
Engineering, parasitic capacitance, delay, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, Capacitance, law.invention, Parasitic capacitance, self-aligned contacts, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Materials Chemistry, Parasitic extraction, Electrical and Electronic Engineering, Stepper, 010302 applied physics, business.industry, Transistor, Electrical engineering, 021001 nanoscience & nanotechnology, Condensed Matter Physics, FDSOI, Electronic, Optical and Magnetic Materials, Parasitic element, Dynamic demand, 0210 nano-technology, business, Voltage
Abstract

We investigate in this work an original contact architecture to address 64 nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment. Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations. It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography. When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances. At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10 nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width W and supply voltage VDD taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption.

Published
2014
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27. Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements

Author

Kazemi Esfeh, Babak, Kilchytska, Valeriya, Parvais, Bertrand, Planes, N., Haond, M., Flandre, Denis, Raskin, Jean-Pierre, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2017), and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
010302 applied physics, Physics, Signal processing, Cut-off frequencies, FDSOI, 3-port S-parameters, business.industry, Electrical engineering, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Cutoff frequency, Terminal (electronics), Logic gate, 0103 physical sciences, MOSFET, Hardware_INTEGRATEDCIRCUITS, Equivalent circuit, Radio frequency, 0210 nano-technology, business
Abstract

This work demonstrates that the back-gate terminal of a 28nm FDSOI MOSFET can be used up to several tens of GHz for signal processing. Furthermore, the dependence of the main RF figures-of-merit on the back gate bias are experimentally extracted using a 3-port characterization in the frequency range of 10 MHz – 26.5 GHz. We propose a small-signal equivalent circuit constructed based on 3-port measurements allowing for more complete extraction of parasitic elements comparing to the 2-ports one. The effect of back-gate bias on cut-off frequencies is demonstrated and explained in terms of its influence on the relevant parasitic elements.

Published
2017
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28. Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory

Author

Francisco Gamiz, P. Ferrari, Sorin Cristoloveanu, Ph. Galy, H. El Dirani, Pascal Fonteneau, X. Mescot, Kyung Hwa Lee, M. Bawedin, Mukta Singh Parihar, Y-T. Kim, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Universidad de Granada = University of Granada (UGR), The Korean Institute of Science and Technology, European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and University of Granada [Granada]

Subjects
low-power, Materials science, Silicon on insulator, Z2-FET, 02 engineering and technology, 01 natural sciences, law.invention, 1T-DRAM, Memory cell, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, SOI, business.industry, Electrical engineering, Sense (electronics), 021001 nanoscience & nanotechnology, Cathode, FDSOI, Anode, Capacitor, Logic gate, Optoelectronics, 0210 nano-technology, business, Dram
Abstract

session poster; International audience; We demonstrate experimentally a capacitorless IT-DRAM fabricated with 28 nm FDSOI. The Z 2 -FET memory cell features a large current sense margin and long retention time at T = 25°C and 85°C. Systematic measurements show that Z 2 -FET exhibits negligible OFF-state current at low drain/gate bias and is suitable as a low-power embedded memory.

Published
2016
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29. Improved analysis of NBTI relaxation behavior based on fast I–V measurement

Author

Xavier Federspiel, Gerard Ghibaudo, D. Nouguier, C. Ndiaye, David Roy, Mustapha Rafik, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), and Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU)

Subjects
Materials science, NBTI, Silicon on insulator, 02 engineering and technology, 01 natural sciences, Temperature measurement, Relaxation behavior, Stress (mechanics), Qualitative analysis, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, relaxation analysis, 010302 applied physics, Negative-bias temperature instability, business.industry, 020208 electrical & electronic engineering, Modeling, Fast Measurement, FDSOI, Temperature effect, Optoelectronics, Relaxation (physics), business
Abstract

session poster; International audience; In this paper, we propose a qualitative analysis of NBTI recoverable components measured on pFET devices issued from various ST Microelectronics (28nm FDSOI technology and 40nm SION or Bulk) technologies. NBTI degradation and recovery resulting from DC stress are measured at μs time scale. We observed similarities between temperature and Vg recovery dependencies on NBTI relaxation of SiON and FDSOI technologies. Then, we discuss the nature of one defect type responsible for the NBTI at early stage of relaxation.

Published
2016
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30. A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI

Author

Jacques-Olivier Klein, Yue Zhang, Mariem Slimani, Weisheng Zhao, You Wang, Hao Cai, Xiaoxuan Zhao, Lirida Alves de Barros Naviner, Laboratoire Traitement et Communication de l'Information (LTCI), Télécom ParisTech-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS), Institut d'électronique fondamentale (IEF), and Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Engineering, Fabrication, Circuit design, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Magnetic flip-flop, Robustness (computer science), 0103 physical sciences, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, Hardware_ARITHMETICANDLOGICSTRUCTURES, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Safety, Risk, Reliability and Quality, 010302 applied physics, Hardware_MEMORYSTRUCTURES, business.industry, Electrical engineering, Spin-transfer torque, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, FDSOI, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Process variation, Tunnel magnetoresistance, CMOS, Asymmetrical forward body bias, 0210 nano-technology, business, Variability analysis, Hardware_LOGICDESIGN
Abstract

International audience; Due to the process variation, Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) faces great challenges in fabrication process. Meanwhile, its neighbor CMOS is also influenced by significant process variation with the continuous technology scaling down. Both of the two effects lead to degraded performance of hybrid MTJ/CMOS circuit. This paper proposes a methodology to alleviate the impact of process variation on the performance of MTJ based applications. The methodology is presented by carrying out a novel design of non-volatile flip-flop (NVFF) using asymmetrical forward body bias (FBB) in fully depleted silicon on insulator (FDSOI). Simulation results show that the sensing errors have been almost removed by this method with the minimum size of circuit. In addition, the thermal robustness of this circuit has also been dramatically improved.

Published
2016
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31. A study of diffusive transport in 14nm FDSOI MOSFET: NEGF versus QDD

Author

Davide Garetto, Yann-Michel Niquet, Christophe Delerue, François Triozon, Denis Rideau, G. Mugny, Marco G. Pala, F.G. Pereira, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Institut Nanosciences et Cryogénie (INAC), Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Synopsys Inc., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), Archéologie des Amériques (ArchAm), Université Paris 1 Panthéon-Sorbonne (UP1)-Centre National de la Recherche Scientifique (CNRS), Laboratory of Atomistic Simulation (LSIM ), Modélisation et Exploration des Matériaux (MEM), Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Institut d’Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520 (IEMN), Ecole Centrale de Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
010302 applied physics, Physics, Condensed matter physics, Phonon, Quantum potential, Saturation velocity, Silicon on insulator, NEGF, 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, QDD, 01 natural sciences, FDSOI, mobility, 0103 physical sciences, MOSFET, Surface roughness, [PHYS.COND.CM-MS]Physics [physics]/Condensed Matter [cond-mat]/Materials Science [cond-mat.mtrl-sci], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Quantum, Saturation (magnetic), ComputingMilieux_MISCELLANEOUS, quantum transport
Abstract

session C6L-C: Advanced TCAD Developments; International audience; Drain current in Ultra-Thin Body (UTBB) Fully-Depleted Silicon-On-Insulator (FDSOI) device is investigated using Non-Equilibrium Green Function (NEGF) simulations. The effects of phonons (PH) and surface roughness (SR) on saturation velocity are studied. We analyze the current and extract quantities relevant to Quantum Drift-Diffusion (QDD) solvers, such as the quasi-Fermi level, the quantum potential and the quasi-ballistic saturation velocity. In particular, the mobility in saturation regime is discussed and an approach based on the Scharfetter-Gummel scheme is presented, bridging the gap between NEGF and QDD frameworks.

Published
2016
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32. FDSOI devices: Issues and innovative solutions

Author

Sorin Cristoloveanu, Maryline Bawedin, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015), and European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016)

Subjects
010302 applied physics, Computer science, business.industry, CMOS, band modulation, Electrical engineering, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, FDSOI, sharp switch, 1T-DRAM, MOSFET, TFET, Logic gate, 0103 physical sciences, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

session A2L-D: CMOS Scaling; International audience; In parallel to presentations documenting the performance of state-of-the-art FDSOI CMOS devices, we discuss selected physical mechanisms and emerging device architectures enabled by FDSOI technology.

Published
2016
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33. Characterization and modeling of NBTI permanent and recoverable components variability

Author

D. Nouguier, Xavier Federspiel, Gerard Ghibaudo, David Roy, Mustapha Rafik, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Engineering, DDCM, NBTI, fast Measurement, 02 engineering and technology, 01 natural sciences, Stress (mechanics), statistical analysis, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Microelectronics, Statistical analysis, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, DCM, Negative-bias temperature instability, reliability, business.industry, 020208 electrical & electronic engineering, Modeling, Stress measurement, FDSOI, Reliability engineering, Characterization (materials science), business
Abstract

session poster; International audience; In this paper we use a statistical analysis of NBTI stress and recoverable components measured on Pfet devices issued from ST Microelectronics 28nm FDSOI technology. NBTI degradation and recovery resulting from AC and DC stress are measured at μs time scale. Statistical analysis of the permanent and recoverable components are performed separately. A Dual Defect Centric Model (DDCM) accounting for these two components is also proposed.

Published
2016
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34. Theoretical investigation of the phonon-limited carrier mobility in (001) Si films

Author

Jing Li, E. Lampin, Christophe Delerue, Yann-Michel Niquet, Université Grenoble Alpes (UGA), Laboratory of Atomistic Simulation (LSIM ), Modélisation et Exploration des Matériaux (MEM), Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), ANR-13-NANO-0009,NOODLES,Modélisation de nanodispositifs pour des applications à faible consommation(2013), Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Subjects
Electron mobility, Materials science, Phonon, Remote-Coulomb-Scattering, Nanowire, General Physics and Astronomy, 02 engineering and technology, Electronic structure, Electron, 01 natural sciences, Condensed Matter::Materials Science, Condensed Matter::Superconductivity, 0103 physical sciences, Ultrathin-Body SOI, Silicon Inversion-Layers, Field Electron-Mobility, Monte-Carlo, Electronic band structure, Effect Transistors, 010302 applied physics, [PHYS]Physics [physics], Condensed matter physics, 021001 nanoscience & nanotechnology, Band-Structure, Boltzmann equation, FDSOI, Brillouin zone, Surface-Roughness, 0210 nano-technology, On-Insulator
Abstract

International audience; We calculate the phonon-limited carrier mobility in (001) Si films with a fully atomistic framework based on a tight-binding (TB) model for the electronic structure, a valence-force-field model for the phonons, and the Boltzmann transport equation. This framework reproduces the electron and phonon bands over the whole first Brillouin zone and accounts for all possible carrier-phonon scattering processes. It can also handle one-dimensional (wires) and three-dimensional (bulk) structures and therefore provides a consistent description of the effects of dimensionality on the phonon-limited mobilities. We first discuss the dependence of the electron and hole mobilities on the film thickness and carrier density. The mobility tends to decrease with decreasing film thickness and increasing carrier density, as the structural and electric confinement enhances the electron-phonon interactions. We then compare hydrogen-passivated and oxidized films in order to understand the impact of surface passivation on the mobility and discuss the transition from nanowires to films and bulk. Finally, we compare the semi-classical TB mobilities with quantum Non-Equilibrium Green's Function calculations based on k . p band structures and on deformation potentials for the electron-phonon interactions (KP-NEGF). The TB mobilities show a stronger dependence on carrier density than the KP-NEGF mobilities, yet weaker than the experimental data on Fully Depleted-Silicon-on-Insulator devices. We discuss the implications of these results on the nature of the apparent increase of the electron-phonon deformation potentials in silicon thin films. Published by AIP Publishing.

Published
2016
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35. Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET

Author

S. Ortolland, Michel Haond, E. Baylac, Thierry Poiroux, Didier Dutartre, Emmanuel Josse, R. Nicolas, R. Berthelon, Francois Andrieu, Alain Claverie, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Matériaux et dispositifs pour l'Electronique et le Magnétisme (CEMES-MEM), Centre d'élaboration de matériaux et d'études structurales (CEMES), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Chimie de Toulouse (ICT-FR 2599), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut de Chimie du CNRS (INC)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Institut de Chimie du CNRS (INC)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse III - Paul Sabatier (UT3), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut de Chimie de Toulouse (ICT), Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), and Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Engineering, Threshold voltage, SiGe, Stress analysis, Multi-finger transistor, 01 natural sciences, law.invention, Stress (mechanics), law, 0103 physical sciences, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Layout dependences, Stress profile, Stresses, MOSFET devices, Silicon alloys, 010302 applied physics, [PHYS]Physics [physics], business.industry, Transistor, Design layout, Layout effects, FDSOI, business, SiGe channels, Communication channel
Abstract

cited By 3; International audience; The introduction of SiGe channel for pMOSFETs in FDSOI technology enables to achieve high performance. However, it has been demonstrated that such a global stressor induces layouts effects. In this paper, we present an exhaustive study of layout impact on threshold voltage. Especially, dissymmetric layouts, non-rectangular active areas and multifinger transistors are investigated. We propose an analytical model based on stress profile to reproduce the layout dependences. This model reproduces the experimental data with good accuracy, whatever the shape of the active area. © 2016 IEEE.

Published
2016
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36. Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration

Author

Pierre Perreau, Michel Haond, Didier Dutartre, R Berthelon, Alain Claverie, A. Pofelski, Emmanuel Josse, Francois Andrieu, E. Baylac, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Matériaux et dispositifs pour l'Electronique et le Magnétisme (CEMES-MEM), Centre d'élaboration de matériaux et d'études structurales (CEMES), Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut de Chimie de Toulouse (ICT), Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Chimie de Toulouse (ICT-FR 2599), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut de Chimie du CNRS (INC)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Institut de Chimie du CNRS (INC)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse III - Paul Sabatier (UT3), and Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)

Subjects
Materials science, SiGe, Electrical model, Gate length, Integration, layout effects, 02 engineering and technology, Ring oscillator, Epitaxy, 01 natural sciences, Strain, Stress (mechanics), chemistry.chemical_compound, 0103 physical sciences, Electronic engineering, Layout dependences, Electrical modeling, Silicon alloys, 010302 applied physics, [PHYS]Physics [physics], Solid state devices, business.industry, Germanium, Delay reduction, 021001 nanoscience & nanotechnology, Integration scheme, Reconfigurable hardware, FDSOI, Silicon-germanium, chemistry, Logic gate, Optoelectronics, 0210 nano-technology, business, Communication channel
Abstract

cited By 0; International audience; We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows -39% mobility for 170nm narrow 2μm long channel, but +21% Ieff at Lg=20nm and gate-to-STI distance of 59nm. It is translated into a -15% delay reduction for ring oscillators of 1-finger inverters. Layout dependences are explained by physical strain measurements and reproduced by a stress-based electrical model. © 2016 IEEE.

Published
2016
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37. Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

Author

François Triozon, S. Barraud, M. Casse, G. Reimbold, Yann-Michel Niquet, Jean-Luc Rouvière, J. Pelloux-Prayer, O. Faynot, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Département Composants Silicium (DCOS), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Laboratory of Atomistic Simulation (LSIM ), Modélisation et Exploration des Matériaux (MEM), Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Laboratoire d'Etude des Matériaux par Microscopie Avancée (LEMMA ), and Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG)

Subjects
Electron mobility, Silicon, Materials science, Nanowire, Silicon on insulator, Nanotechnology, 02 engineering and technology, 01 natural sciences, MOSFET, 0103 physical sciences, Materials Chemistry, Electron-Mobility, Heterostructures, Electrical and Electronic Engineering, 010302 applied physics, [PHYS]Physics [physics], Strain (chemistry), business.industry, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Thermal conduction, Piezoresistive effect, Aspect ratio (image), FDSOI, Electronic, Optical and Magnetic Materials, MultiGate, Optoelectronics, 0210 nano-technology, business
Abstract

International audience; The effect of strain on carrier mobility in triple gate Fully Depleted Silicon On Insulator (FDSOI) nanowires (NWs) is experimentally investigated through piezoresistance measurements. The piezoresitive coefficients have been extracted and analyzed for rectangular cross-section with varying aspect ratio (width vs. height). We propose an empirical model based on mobility separation between top and sidewall conduction surfaces of the NWs, and on the carrier density calculation in the cross-section of the NWs. The model allows fitting the piezoresistive coefficients and the carrier mobility for the different device geometries. We highlight an enhanced strain effect for Trigate nanowires with channel thickness below 11 nm. (C) 2016 Elsevier Ltd. All rights reserved.

Published
2016
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38. New BIMOS transistor in 28nm FDSOI technology: Operation in 4-Gate JFET mode

Author

Sotirios Athanasiou, Ph. Galy, Sorin Cristoloveanu, STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
JFET, Computer science, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, BiCMOS, 01 natural sciences, 7. Clean energy, law.invention, Mode (computer interface), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, Bicmos integrated circuits, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Transistor, CMOS, Electrical engineering, FDSOI, Integrated injection logic, Logic gate, BIMOS transistor, Optoelectronics, business, Hardware_LOGICDESIGN
Abstract

International audience; In this paper, we introduce a new BIMOS transistor fabricated with 28nm high-k metal-gate FDSOI UTBB technology. The device is highly flexible and reconfigurable as it can be operated in MOS, Bipolar, Hybrid and 4-Gate modes. We investigate the bias conditions for JFET-like operation and show promising performance even in structures with ultrathin Si film.

Published
2015
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39. CMOS-compatible FDSOI bipolar-enhanced tunneling FET

Author

Peng Zhang, Jing Wan, Sorin Cristoloveanu, Alexander Zaslavsky, School of Engineering (Brown Engineering), Brown University, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, Heterostructure-emitter bipolar transistor, business.industry, Heterojunction bipolar transistor, Tunneling field effect transistor, Transistor, sharp switching, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, FDSOI, law.invention, tunneling field-effect transistor, law, Subthreshold swing, 0103 physical sciences, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Drain current, business, bipolar-enhanced tunneling field-effect transistor, Quantum tunnelling, Cmos compatible
Abstract

session poster; International audience; We propose and simulate a bipolar-enhanced tunneling field-effect transistor (BET-FET) with a lateral layout that is fully FDSOI compatible. Simulations calibrated to experimental TFET data show a high on-current of ION ~ 260 μA/μm at VDD = 1 V and a subthreshold swing (SS) well below 60 mV/dec over 7 decades of drain current. The mechanism involves the combination of gate-controlled sharp TFET switching with current gain from a Si/Si 1-x Ge x heterojunction bipolar transistor (HBT). An electrostatically controlled BET-FET variant with a local buried gate is also simulated.

Published
2015
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40. EDMOS in ultrathin FDSOI: Effect of doping and layout of the drift region

Author

Dominique Golanski, Christian Dutto, Sorin Cristoloveanu, Sylvie Ortolland, Antoine Litty, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
010302 applied physics, Fabrication, Materials science, business.industry, 020208 electrical & electronic engineering, Doping, Silicon on insulator, 02 engineering and technology, extended-drain, 01 natural sciences, FDSOI, MOSFET, CMOS, EDMOS, Logic gate, 0103 physical sciences, high-voltage, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Node (circuits), doping level, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

session A7L-F: Innovation Approaches for Opto and Power Devices; International audience; We have already demonstrated the fabrication of a Dual-Ground Plane Extended Drain MOSFET with 28nm FDSOI technology. The detrimental consequences of ultrathin SOI film were mitigated by back-biasing the ground planes. In this paper, we explore for the first time the device optimization in 28 nm FDSOI node by doping the drift region. This solution requires additional and dedicated process steps but is free from back-biasing schemes. Following TCAD simulations, devices have been designed and fabricated with UTBB-FDSOI technology. DC measurements indicate that even in ultrathin film (7 nm) the doping of drift region is still a lever for achieving high-voltage (5V) MOSFET with promising performance.

Published
2015
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41. Reliability of film thickness extraction through CV curves of SOI p-i-n gated diodes

Author

Sorin Cristoloveanu, Katia R. A. Sasaki, Carlos Navarro, Maryline Bawedin, Francois Andrieu, Joao Antonio Martino, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Institut d’Electronique et des Systèmes (IES), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Micro électronique, Composants, Systèmes, Efficacité Energétique (M@CSEE), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), LSI/PSI/USP - University of Sao Paulo - Brazil, Universidade de São Paulo = University of São Paulo (USP), ANR-11-JS03-0001,AMNESIA,Dispositifs Mémoires Nanométriques Innovants pour Applications Ultra Basse Consommation(2011), European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and University of Sao Paulo (Brazil)

Subjects
Materials science, Silicon, capacitance, chemistry.chemical_element, Silicon on insulator, 02 engineering and technology, Derivative, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Capacitance, Reliability (semiconductor), 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, split CV, gated diode, silicon film thickness, coupling, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Diode, 010302 applied physics, Coupling, SOI, business.industry, p-i-n, 021001 nanoscience & nanotechnology, FDSOI, chemistry, supercoupling, Optoelectronics, 0210 nano-technology, Tin, business
Abstract

session 1: Semiconductor Devices; International audience; This work aims to study the reliability of the Si film thickness extraction method based on the capacitance derivative analysis in p-i-n gated diodes. Results provided by the derivative procedure are compared to the basic capacitance method (without the derivative). The basic method yields accurate Si-film thicknesses, but it can only be applied to relatively thick body devices where the supercoupling effect does not occur. On the other hand, the use of the derivative analysis is feasible and effective in ultrathin devices. This makes the derivative procedure more suitable for the characterization of the body thickness in advanced FDSOI MOS-like devices.

Published
2015
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42. Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits

Author

Jean-Max Dutertre, G. Di Natale, M.-L. Flottes, S. de Castro, Bruno Rouzeyre, Département Systèmes et Architectures Sécurisés (SAS-ENSMSE), École des Mines de Saint-Étienne (Mines Saint-Étienne MSE), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-CMP-GC, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
Computer science, Hybrid silicon laser, Laser, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Fault (power engineering), 01 natural sciences, law.invention, Hardware security, law, Fault injection, 0103 physical sciences, MOSFET, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, NMOS logic, Electronic circuit, 010302 applied physics, business.industry, Electrical engineering, FDSOI, CMOS, 020201 artificial intelligence & image processing, business
Abstract

Among all means to attack a security dedicated circuit, fault injection by means of laser illumination is a very efficient one. The laser beam creates electrons/holes pairs along its way through silicon. Collection of these charges creates a transient current and thus may induce a fault in the circuit. Nevertheless the collection efficiency depends on various parameters including the technology used to implement the circuit. Here, Bulk and Fully Depleted Silicon on Insulator (FD-SOI) 28nm technologies are compared in terms of sensitivity against laser injection. Laser induced current measurements are performed on a ST 28nm technology bulk and FDSOI NMOS transistors. It comes out that FD-SOI structures show less sensitivity to laser injection and thus should be further explored for security dedicated circuits implementations.

Published
2015
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43. Unusual gate coupling effect in extremely thin and short FDSOI MOSFETs

Author

Young-Ho Bae, Maryline Bawedin, Sorin Cristoloveanu, Francois Andrieu, Carlos Navarro, S.-J. Chang, Yong Tae Kim, Department of Electrical Engineering [Yale University], Yale University [New Haven], Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Department of Electrical Engineering [Korea Advanced Institute of Science and Technology] (KAIST), Korea Advanced Institute of Science and Technology (KAIST), Uiduk university, Gyeongju, ANR-11-JS03-0001,AMNESIA,Dispositifs Mémoires Nanométriques Innovants pour Applications Ultra Basse Consommation(2011), European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Ducroquet, Frédérique

Subjects
Electron mobility, Materials science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Silicon on insulator, 02 engineering and technology, Coupling effects, Short-channel, 01 natural sciences, Coupling effect, 0103 physical sciences, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, 010302 applied physics, Coupling, business.industry, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, FDSOI, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Subthreshold swing, Optoelectronics, Ultra-thin film, ComputingMethodologies_GENERAL, 0210 nano-technology, business, ISBN: 978-88-9030-695-2
Abstract

Display Omitted Ultra-thin film FDSOI MOSFETs have been investigated for various film thicknesses, gate lengths, back-gate biases and temperature.High carrier mobility and excellent subthreshold swing was achieved thanks to the state-of-the-art technology.The relationship between the film thickness, temperature, and coupling effect was explored.In short-channel FDSOI device, coupling effect increases with raising temperature.In devices thinner than 5-6nm, the coupling is independent of temperature due to the minimized short-channel effects. We investigated the characteristics of state-of-the-art FDSOI MOSFETs in a wide range of temperature by focusing on the effects of the back-gate bias, Si film thickness and channel length. High device performance and remarkably reduced short-channel effect with decreasing Si film thickness are achieved in ultra-thin film SOI devices. Systematic measurements reveal an unusual coupling effect resulting from the competition between front-gate, back-gate and temperature-dependent short-channel effect. Counter-intuitively, the impact of the back-gate bias can be smaller in 5nm than in 10nm thick MOSFETs, in particular in very short devices operated at 300K.

Published
2015
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44. Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology

Author

Ph. Galy, Sorin Cristoloveanu, Sotirios Athanasiou, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
ESD protection, Materials science, Silicon, Thermal resistance, chemistry.chemical_element, 02 engineering and technology, 7. Clean energy, 01 natural sciences, law.invention, Stress (mechanics), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Metal gate, 010302 applied physics, Equivalent series resistance, business.industry, Transistor, CMOS, Electrical engineering, 020206 networking & telecommunications, FDSOI, chemistry, BIMOS transistor, Optoelectronics, business, Voltage
Abstract

session J: I/O circuits and ESD protection; International audience; The purpose of this paper is to analyze the ESD device electro-thermal behavior of BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. This evaluation is based on 3D TCAD simulations with classical physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope (AVS) method). We show how the series resistance and the thermal resistance impact the average and peak temperatures in these devices.

Published
2015
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45. Optimization of a high-voltage MOSFET in ultra-thin 14nm FDSOI technology

Author

Sylvie Ortolland, Dominique Golanski, Sorin Cristoloveanu, Antoine Litty, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Power management, LDMOS, Materials science, Silicon on insulator, back-bias, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, 0103 physical sciences, MOSFET, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Breakdown voltage, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, high-voltage MOSFET, Ground plane, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Electrical engineering, Biasing, extended-drain, FDSOI, Optoelectronics, business, ultra-thin buried oxide, Voltage
Abstract

We investigate a promising high-voltage MOSFET (HVMOS) fabricated in the leading edge 14nm Fully-Depleted Silicon-On-Insulator technology (FDSOI). We focus on a variant of the Extended-Drain MOSFET (EDMOS) on SOI which features Ultra-Thin Body and Buried oxide (UTBB) and Dual Ground Plane configuration (DGP). The independent biasing of two different ground planes located under the device enables, without film doping, to control separately the electrostatic properties of the channel and the drift regions. Electrical characteristics such as breakdown voltage and specific on-resistance are explored for different layout geometries and backgate voltage. Encouraging results of the DGP EDMOS in 14nm FDSOI are presented for 5V power management.

Published
2015
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46. Impact of back plane on the carrier mobility in 28nm UTBB FDSOI devices, for ESD applications

Author

Sotirios Athanasiou, Sorin Cristoloveanu, Ph. Galy, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Coupling, Mobility, Electron mobility, Materials science, business.industry, Doping, Transistor, CMOS, ESD, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, FDSOI, Threshold voltage, law.invention, Backplane, law, 0103 physical sciences, Optoelectronics, Work function, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

session poster; International audience; We present measurements and parameter extraction performed on 28nm UTBB FDSOI MOSFETs with two different Back Plane configurations (p-type and n-type BP). The change in BP doping and work function affects directly the back-channel characteristics and indirectly, via interface coupling, the front-channel properties. We investigate the parameters relevant for the design of ESD protection devices: threshold voltage shift and electron mobility in long and short transistors.

Published
2015
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47. BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology

Author

Ph. Galy, Sotirios Athanasiou, Sorin Cristoloveanu, STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
ESD protection, Materials science, Silicon, chemistry.chemical_element, 02 engineering and technology, 7. Clean energy, 01 natural sciences, law.invention, Stress (mechanics), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Metal gate, 010302 applied physics, business.industry, Transistor, CMOS, Electrical engineering, 020206 networking & telecommunications, FDSOI, chemistry, BIMOS transistor, Optoelectronics, business
Abstract

session 2: POwer Devices and ESD Protection; International audience; The purpose of this study is to evaluate the ESD protection behavior using BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. Using as a reference our measurements in hybrid bulk structures we extend the BIMOS design towards the ultrathin silicon film. Evaluations are done based on 3D TCAD simulation with standard physical models using ACS method and quasi-static DC stress (AVS method).

Published
2015
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48. Modeling study of the mobility in FDSOI devices with a focus on near-spacer-region

Author

G. Mugny, Benoit Sklenard, F.G. Pereira, Davide Garetto, Clement Tavernier, Marco G. Pala, François Triozon, Gaspard Hiblot, Denis Rideau, O. Nier, STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Synopsys Inc., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), ANR-13-NANO-0009,NOODLES,Modélisation de nanodispositifs pour des applications à faible consommation(2013), and European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013)

Subjects
Electron mobility, Materials science, Silicon, chemistry.chemical_element, 02 engineering and technology, Poisson-Schrödinger, 01 natural sciences, Kubo-Greenwood, 0103 physical sciences, Diffusion (business), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Quantum, Quantum tunnelling, 010302 applied physics, Condensed matter physics, business.industry, Doping, Solver, 021001 nanoscience & nanotechnology, QCDD, FDSOI, mobility, chemistry, transport, Optoelectronics, 0210 nano-technology, business, Focus (optics)
Abstract

International audience; We have studied the mobility in the FDSOI devices as a function of silicon thickness, doping, surface orientation and applying different back biases. This study is also done in the near-spacer-region that is partially inverted. Simulations have been obtained with a self-consistent Poisson-Schrödinger which provides a precise energy distribution of carriers and, allied to a Kubo-Greenwood carrier mobility solver, performs a quantum corrected drift diffusion (QCDD) model, capable of capturing non local effects on transport (tunneling) and mobility (influence of geometry).

Published
2015
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49. Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10nm node

Author

Jean-Charles Barbe, Francois Andrieu, S. Morvan, Gerard Ghibaudo, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Electron mobility, Materials science, Silicon, Silicon on insulator, chemistry.chemical_element, 02 engineering and technology, Nitride, 01 natural sciences, law.invention, Stress (mechanics), Embedded, Strain transfer, law, 0103 physical sciences, Materials Chemistry, Wafer, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, business.industry, sSOI, Transistor, Electrical engineering, 021001 nanoscience & nanotechnology, Condensed Matter Physics, buried SiGe, FDSOI, Electronic, Optical and Magnetic Materials, chemistry, Booster (electric power), Optoelectronics, 0210 nano-technology, business
Abstract

International audience; This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3 GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10 nm node. The strain induced in the channel by the edge relaxation of an embedded buried SiGe layer is compared to strained Silicon-On-Insulator (sSOI) wafers and strained nitride layer for Fully Depleted Silicon-On-Insulator (FDSOI).

Published
2014
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50. Low temperature characterization of 14nm FDSOI CMOS devices

Author

Ming Shi, Mireille Mouis, Gyu Tae Kim, Minju Shin, Gerard Ghibaudo, Emmanuel Josse, Antoine Cros, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), School of Electrical Engineering [Korea University], Korea University [Seoul], STMicroelectronics [Crolles] (ST-CROLLES), and European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012)

Subjects
010302 applied physics, Mobility, parameters, Materials science, business.industry, Subthreshold conduction, Scattering, Phonon, Good control, 02 engineering and technology, Low temperature characterization, 01 natural sciences, FDSOI, 020202 computer hardware & architecture, Characterization (materials science), CMOS, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Communication channel
Abstract

International audience; A detailed characterization of low temperature operation of n and p MOS devices from 14nm FDSOI CMOS technology has been conducted. The transfer characteristics measured between 77K and 300K exhibit very good performance for effective gate lengths down 15nm, emphasizing the very good control of short channel effects and subthreshold behavior. Moreover, the temperature dependence of the low field mobility clearly indicates that, for long devices, it is limited by phonon scatterings whereas, for sub 100nm gate lengths, the mobility is significantly degraded and almost independent with temperature. This feature is attributed to scattering by neutral defects, which are originated from source and drain process and extending over several tens of nm along the channel.

Published
2014
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