79 results on '"Travaly, Y."'
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2. Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration
3. Variation in process conditions of porogen-based low- k films: A method to improve performance without changing existing process steps in a sub-100 nm Cu damascene integration route
4. Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures
5. Air gap formation by UV-assisted decomposition of CVD material
6. Stress corrosion of organosilicate glass films in aqueous environments: Role of pH
7. Extent of plasma damage to porous organosilicate films characterized with nanoindentation, x-ray reflectivity, and surface acoustic waves
8. Thermomechanical properties of thin organosilicate glass films treated with ultraviolet-assisted cure
9. Materials characterization of WN xC y, WN x and WC x films for advanced barriers
10. Surface properties restoration and passivation of high porosity ultra low- k dielectric ( k ∼ 2.3) after direct-CMP
11. Short-ranged structural rearrangement and enhancement of mechanical properties of organosilicate glasses induced by ultraviolet radiation
12. A theoretical and experimental study of atomic-layer-deposited films onto porous dielectric substrates
13. A novel approach to resistivity and interconnect modeling
14. Nucleation, growth, and aggregation of gold on polyimide surfaces
15. Challenges in the implementation of low-k dielectrics in the back-end of line
16. Characterization of atomic layer deposited nanoscale structure on dense dielectric substrates by X-ray reflectivity
17. Study of thermal stability of nickel silicide by X-ray reflectivity
18. Challenges for structural stability of ultra-low- k-based interconnects
19. Impact of material/process interactions on the properties of a porous CVD-O 3 low-k dielectric film
20. The impact of the density and type of reactive sites on the characteristics of the atomic layer deposited WNxCy films.
21. Interface characterization of nanoscale laminate structures on dense dielectric substrates by x-ray reflectivity.
22. The impact of the density and type of reactive sites on the characteristics of the atomic layer deposited W[N.sub.x][C.sub.y] films
23. Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers.
24. Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications.
25. Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's.
26. Integration challenges of Cu pillars with extreme wafer thinning for 3D stacking and packaging.
27. A novel concept for ultra-low capacitance via-last TSV.
28. 300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications.
29. Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
30. Post-dicing particle control for 3D stacked IC integration flows.
31. 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding.
32. Time and temperature dependence of early stage Stress-Induced-Voiding in Cu/low-k interconnects.
33. 3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV).
34. TSV metrology and inspection challenges.
35. Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping.
36. Role of dielectric and barrier integrity in reliability of sub-100 nm copper low-k interconnects.
37. Minimizing plasma damage and in situ sealing of ultralow-k dielectric films by using oxygen free fluorocarbon plasmas.
38. Impact of material/process interactions on the properties of a porous CVD-O3 low-k dielectric film
39. Thermal stability of copper Through-Silicon Via barriers during IC processing.
40. Enabling Cu-Cu connection in (dual) damascene interconnects by selective deposition of two different SAM molecules.
41. 3D technology roadmap and status.
42. Link between silica-metal agglomeration and high porosity ultra-low k scratch formation during Chemical Mechanical Polishing.
43. Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure.
44. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections.
45. Key factors to sustain the extension of a MHM-based integration scheme to medium and high porosity PECVD low-k materials.
46. The critical role of the metal / porous low-k interface in post direct CMP defectivity generation and resulting ULK surface and bulk hydrophilisation.
47. Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node.
48. Understanding integration damage to low-k films: mechanisms and dielectric behaviour at 100kHz and 4GHz.
49. Surface acoustic waves as a technique for in-line detection of processing damage to low-k dielectrics.
50. Low-damage damascene patterning of SiOC(H) low-k dielectrics.
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