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We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations. Index Terms--65 and 90 nm, low voltage, measurement structure, read current, SRAM, variation, write trip voltage.

This paper describes the design and VLSI implementation of a highly efficient, single-port SRAM-based deblocking filter. It can achieve 204 cycles/macroblock throughput for H.264/AVC real-time decoding. Several deblocking filter designs in the literature have been compared and the possibility of realizing them in a pipeline is studied. Eventually we came up with a completely new design which has a five-stage pipeline with gated clock to increase system throughput while reducing power. Data hazards and structure hazards, which are the two most critical issues for a pipelined filter, are analyzed and resolved. Efficient memory organization for both on-chip SRAM and transposition buffers is employed. By using innovative hybrid edge filtering sequence and out-of-order memory update scenario, we obtain zero stall cycle in normal pipeline flow, making the best out of a pipelined architecture. Compared with existing designs, our design achieves at least 18% clock cycle reduction, as well as 20% lower power consumption owing to its efficient pipeline and memory architecture. The total gate count is comparable to other designs in literature without using any expensive two-port or dual-port on-chip SRAMs. Index Terms--Deblocking filter, hazard, H.264/AVC, macroblock, pipeline, SRAM, throughput.

An efficient infrastructure is described for characterizing the various types of variation in transistor characteristics. The impact of the variability on static random access memory (SRAM), analog and digital circuit blocks used for designing system-on-chip is examined.

ROM cell architectures are proposed that have roughly 20% greater storage density in the cell array compared to that of a conventional ROM. Increased density is achieved by exploiting the multiple interconnect layers now available in common logic processes and by using multiple ROM cell types in combination. The storage density of arrays of these hybrid ROM cells increases further as more interconnect layers become available. In addition, a new SRAM-ROM architecture is presented that capitalizes on these techniques to add ROM capability to a conventional SRAM cell with no additional transistors in the memory cell and little or, in some cases, no impact on the cell area. Index Terms--Memory architecture, multiple bitlines (BLs), read-only memory, ROM, SRAM, SRAM-ROM, stacked BLs.

A low-power embedded SRAM for a large range of applications has been implemented in a standard digital 0.18-1[micro]m process. The leakage current in the cells is reduced by using a source-body bias not exceeding the value that guaranties safe data retention, and less leaking nonminimum length transistors. Locally short-circuiting this bias, speed and noise margin loss in active mode is avoided, especially for low supply voltages. The bias is generated internally at the carefully designed equilibrium between cell, switch, and diode limiter leakages averaged over the array. The leakage of the full SRAM, including an optimized periphery, is reduced more than 20 times. Used in an industrial RF transceiver, the measurements confirm its performances. Index Terms--CMOS memory, limiting, low leakage, low power, source bias, SRAM, subthreshold current.

The static random acces memory (SRAM) array discussed in this brief is based on a four-transistor SRAM cell. A new method of writing the cell together with an associated array structure is proposed. The advantages are a significant reduction in power and an increase in cell reliability over previous designs. The noise margin of the cell under various conditions is investigated, as this is an effective method of designing the control mechanism of the cell. Index Terms--Reduced-area static random acces memory (SRAM), static noise margin.

A loadless complementary metal-oxide semiconductor (CMOS) four-transistor (4T) cell for very-high-density embedded static random-access memory (SRAM) applications is described.

The effect of a gate-all-around thin-film transistor (GAT) with a lightly doped drain structure on the reduction of the off-current is studied. The off-current of the GAT is found to be almost the same as that of a single-gate TFT with an LDD structure although the GAT's channel area is about twice as big as that of the SGT. The suppression mechanism of the individual performance variations in the GAT is also investigated by thinning the channel poly-Si.

This paper reports on the ellipsometric monitoring of SRAM gate patterns in KrF lithography. Results showed that ellipsometry is practical for monitoring repetitive patterns. A multivariable regression analysis was applied to predict gate lengths by using ellipsometric parameters. A good agreement (3[Sigma] = 8.7 nm) between the measured width by CD-SEM and the predicted ones was achieved. Standard deviation of the predicted width (repeatability) was 0.5 nm. This suggests that ellipsometry is superior to CD-SEM in arriving at the average values.

An asymmetric memory cell, a single-bit-line static random access memory cell, was designed using a complementary thin-film transistor (C-TFT). The structure of the C-TFT was constructed with n-channel and p-channel TFTs which share the same gate. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4 micrometer design rules. The cell was found to be capable of stable read and write operations with further decreases cell size.

The role of neutron-induced soft errors (SE) in logic applications is examined through an experimental and analytical study of neutron-induced SE in sub-half-micron complementary metal oxide semincoductors (CMOS) SRAM and Latch circuits. Findings show that the cosmic ray neutrons affect CMOS circuits at ground level and SE rates (SER) in Latch circuits were dominated by neutrons. Moreover, neutron-induced SER in CMOS SRAM were on the same order as alpha-induced SER.

The radiation hardness (RadHrd) of semiconductor devices is important in space, military, nuclear power plant and high energy physics detector applications. The RadHrd test of static random-access-memory (SRAM) has been undertaken using the Co-60 gamma ray and does-to-failure parameter. The number of error-bytes vs dose, was found to provide a clear dose-to-failure. Test conditions of dose rate, temperature and power supply voltage have to be specified to ensure meaningful test results.

A closed-form propagation delay expression developed for the complementary metal-oxide semiconductor static random access memory (SRAM) chip predicts delay time for high density, high speed SRAM's with computational ease and sufficient accuracy. The model is based on a delay approximation for a SRAM cell capacitively loaded with multilayer interconnections and hence, can be extended to branched transmission lines. The expression-predicted absolute maximum error is smaller than 4.8% in comparison with actual measurements.

A high-performance, quadruple well, quadruple polysilicon BiCMOS technology for the fast 16 Mb SRAM's has a split word-line bitcell configuration with two self-aligned contacts and four polysilicon levels and yields cell areas of 8. 61 square micrometers and 7.32 square micrometers with I-line and deep UV lithographies, respectively. The quadruple-well structure enhances soft error rate and helps optimize the bipolar and MOSFET performances. The BiCMOS technology uses MOSFET transistors for gate polypitch, thin-film transistor for increase in bitcell stability and a double polysilicon transistor.

The SEU/SRAM is a 4-kbit static random access memory (SRAM) designed to detect single-event upsets (SEU's) produced by high-energy particles, either in space or on the ground. This device was used to determine the distribution of the memory cell spontaneous flip potential. The variance in this potential was determined to be due to the variation in the threshold voltage of one of the n-FET's found in the memory cell. For a 1.2-[[micro]meter] CMOS process, the standard deviation of the n-FET VT was found to be 8 mV. This structure provides substantial statistical data; 4096 data points are measured. Using cumulative distribution and residual plots, outlier cells, such as stuck cells and nonnormally distributed cells, are easily identified.

The effects of multilayer interconnections on a megabit static random access memory (SRAM) chip's performance are modelled and analyzed. SRAM chip performance parameters include dissipation delay, speed, power dissipation and noise. Megabit SRAMs are used in computer workstations and high-speed test systems.

A self-aligned landing pad structure is employed to replace a single-polysilicon non-self-aligned bipolar transistor in a 0.5-micrometer bipolar-complementary-metal-oxide-semiconductor (BiCMOS) technology with its double-polysilicon emitter-base self-aligned counterpart. The substituiton resulted in a moderate rise in complexity for theprocess technology used in fabricating 4-Mb static random access memory circuits. It also led to enhanced bipolar transistor performance.

An experiment to quantify the properties of n+-p-n+ polysilicon loads used to minimize the size of static random access memory cells is presented. It describes the dependence of the polysilicon load resistance on the fixed positive charges and gate oxide thickness of a related thin film transistor. This dependence results in a drop of the polysilicon loadresistance after exporsure to post-metallization anneal at low temperatures.

A stacked-complentary metal oxide semiconductor technology for realizing high-density static random access memory cells is presented. With the technology, a static noise margin rise and cell size decrease is attributed to a boost in the on-current of the thin film transistor load. The enhanced performance of the thin film transistor load is caused by the solid phase growth fabrication method that results in larger grains of the polysilicon film.

A new low-power and high-stability static random access memory (SRAM) technology has been developed which uses laser recrystallized p-channel silicon-on-insulator metal oxide semiconductor field effect transistors. Previous tests using the technology have generated 256-kilobyte SRAM. The technology improves stand-by power dissipation and cell stability. Parasitic capacitance is also reduced and results in faster large scale inegration.

Advances in 0.5 micrometer bipolar complementary metal oxide semiconductor (BiCMOS) technology are reported. In the study, the process for fabrication of speedy 4-Mb static random access memory bit cells is presented. It makes use of three polysilicon layers to form a bit cell consisting of four transistors whose size is less than 20 micrometers. Meanwhile, a WSi(sub x) polycide emitter n-p-n transistor with an area of 0.8 x 2.4 square micrometer and maximum cutoff frequency at 14 GHz is also discussed.

A study of deep depletion channel shielding, a process used for dynamic write inhibition (DWI) of nonvolatile semiconductor memories, is presented. Applied mainly to silicon nitride oxide semiconductor and metal nitride oxide semiconductor memory cells, its theory was further expanded through a new equation for the transient reaction of the surface voltage in DWI. The investigation also measured the return to normal speed for devices under DWI condition.

The design and fabrication of a 16-kb static random access memory (SRAM) is presented. The SRAM has a triple-level metal interconnection that lowers the wiring length and chip size, thus resulting in increased speed, higher yield and a power dissipation of less than 2 W for the temperature range between 25 to 100 degrees Celsius. The process technology responsible for the enhanced performance of the device is also described, together with its unique features.

The fabrication and characterization of bottom gate thin-film transistors (TFT) and TFT static random access memory (SRAM) cells with diode and metal contacts were described. It was found that the parasitic diode contact in the bottom gate TFT SRAM cell limits its high node charging current. The charging of 15fF load capacitor to 0.1-0.2 V below V(sub cc) took about 0.65 ms. The adverse effect was circumvented in the metal contact TFT SRAM cell whose charging to full V(sub cc) is seven times faster.

Rapid thermal contact annealing was found damaging to the threshold characteristics of thin-film transistors (TFT's) but, it can improve the maximum transconductance. It was also observed that at higher rapid thermal contact annealing temperature, more degradations on the characteristics of the TFT's will be observed. Low-temperature anneal in H2/N2 gas ambient was recommended for recovery of these degradations.