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In this paper, a novel cut-off degradation of output current induced by high fluence neutron radiation is investigated for high-voltage silicon-on-insulator lateral double-diffused MOSFET (HV SOI LDMOS). Unlike low/middle fluence, severe current collapse occurs at low drain voltage. Combining experiments and energy band analysis, we reveal that a secondary charge removal effect leads to cut-off degradation, which is closely related to the field enhancement and high-density defects at high neutron fluence. Although the gate channel can be turned on after radiation, below drain threshold voltage (VDT), electron drift is blocked by a potential barrier caused by the local space charge region with low trap occupation rate, rather than the global impact at low fluence. In addition, the influences of structural parameters on the cut-off degradation and VDT are studied to guide the rad-hardening design of HV SOI LDMOS.

A lateral power device with complementary homogenization field structure (C-HOF) is proposed and experimentally proved in this letter. The C-HOF is formed by introducing a P-type metal insulator semiconductor (P-MIS) on the N-MIS. The complementary P/N-MIS and the PN junction between them ensure the homogenized field ${E}_{\text {hof}}$ distributions and the high breakdown voltage ${V}_{\text {B}}$ in higher doping. Based on the C-HOF mechanism, experiments were performed, which demonstrated that a significantly increased N-drift doping dose up to 6.8 $\times \,\,10^{{12}}$ cm−2 can be realized in the C-HOF device. A measured low specific on-resistance ${R}_{ {{\scriptscriptstyle \text{ ON}}},\text {sp}}$ of 19.7 $\text{m}\Omega \cdot $ cm2 was observed in the C-HOF device under a ${V}_{\text {B}}$ of 426 V, realizing a high figure of merit $FOM = {V}_{\text {B}}^{{2}}/{R}_{ {{\scriptscriptstyle \text{ON}}},\text {sp}}$ of 9.21 MW/cm2 and a reduction of 42.8% when compared with the theoretical value of the triple RESURF technology under the same ${V}_{\text {B}}$ .

The analytical model and mechanism of homogenization field (HOF) for lateral power devices is developed in this article. The HOF structure features periodical voltage sustaining cells connected in series from source to drain, which introduces the periodic field modulation to realize the 3-D homogenization of electric field. In the model, the periodic electric field distribution of the HOF structure is obtained by solving the Poisson’s equation in one half HOF-cell. Then, a design formula is deduced by considering the optimal field distribution. Two lateral double-diffused metal–oxide semiconductor (LDMOS) devices using the HOF structure were fabricated to demonstrate the analytical model. The analytical model is in good agreement with both the simulations and experiments. In the experiments, a low $R_{ \mathrm{\scriptscriptstyle ON},sp}$ of 53.3 $\text{m}\Omega \cdot $ cm2 was realized under a high ${V}_{B}$ of 669.5 V, achieving a HOF LDMOS with high figure of merit FOM $= {V}_{B}^{2}/{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ of 8.41 MW/cm2.

Total-ionizing-dose (TID) radiation response on unclosed edge termination is investigated for high voltage silicon-on-insulator (SOI) laterally diffused metal–oxide–semiconductor (LDMOS) in this article. Radiation-induced dual-channel leakage current model is proposed to reveal the mechanism of leakage current generation at OFF-state. Radiation causes a mass of positive oxide trapped charges generated in field oxide (FOX) layer and buried oxide layer. Owing to the P-SOI layer with significantly low doping concentration, two inversion channels are formed at the surface and bottom in the edge termination region, which provides parallel conduction paths. Electrons from the source N+ are pulled down and flow along the bottom channel while punchthrough occurring. The radiation-induced leakage current could be suppressed by thinning FOX layer, increasing the doping concentration of the P-SOI layer, and thickening the SOI layer.

The global region normalization (GRN) method is proposed to optimize the lateral superjunction (SJ), in this article. The GRN features normalizations in the global doping range of the SJ from zero to the maximum doping concentration ${N}_{\text {max}}$ that was theoretically determined by the pillar width ${W}_{\text {SJ}}$ . Then the optimization covers all the possible design points of the SJ. For the SJ with given ${W}_{\text {SJ}}$ and pillar length ${L}_{\text {SJ}}$ , the specific ON-resistance ${R}_{\text {on,sp}}$ and breakdown voltage ${V}_{\text {B}}$ are normalized in the global region of the doping concentra- tion ${N}_{\text {SJ}}$ . With the GRN method, the global normalization function ${f}_{\eta }$ is deduced to reflect the quantitative variation trend of ${R}_{\text {on,sp}}$ - ${V}_{\text {B}}$ and a design formula of the optimized ${N}_{\text {SJ}}$ is presented. Furthermore, lateral SJ devices were fabricated according to the formula. The measured ${R}_{\text {on,sp}}$ values of the SJ devices are reduced by almost 35% when compared with the theoretical limit of the triple RESURF device in a voltage range of 100–400 V. The experiments also reveal that the measured net ${R}_{\text {on,sp}}$ of the SJ region approaches the ${R}_{\text {on.sp}} \propto {V}_{\text {B}}^{{1.03}}$ relationship.

This article proposes a novel ultralow specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$ ) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich n-p-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter $\Delta {L}$ in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low ${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$ of 78.3 $\text{m}\Omega \cdot $ cm2 and high breakdown voltage (BV) of 795 V, and the experimental ${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$ is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on ${L}_{d} = 67 \mu \text{m}$ , which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.

Recently, Shu et al. published “Numerical and Experimental Investigation of TID Radiation Effect on the Breakdown Voltage of 400 V SOI NLDMOS.” This short article is an extension of that earlier article. The breakdown voltage of 400-V silicon-on-insulator n-channel laterally diffused metal–oxide semiconductor field-effect transistors with different drift region lengths are examined after exposure to total ionizing dose. The variation observed is analyzed using technology computer-aided design simulation.

A novel Homogenization Field Technology (HOFT) in lateral power devices is proposed and experimentally proved in this letter. By introducing the periodically discrete metal insulator semiconductor (MIS) structure, which realizes periodic equal potential and self-charge balance, the HOFT obtains almost uniform surface and bulk electric field distributions in the voltage sustaining layer. Therefore, the new device harvests both higher breakdown voltage V B and lower specific on-resistance R on,sp than those of the conventional reduced surface field (RESURF) technology in much higher and wider doping dose range. The experiment of the HOFT device realized a V B of 672 V and a R on,sp of 56.7 $\text{m}\Omega ~\cdot $ cm2 under a high doping dose of $5.6\times 10^{{12}}$ cm−2, which represents a reduction of 33.8% when compared with the theoretical value of the triple RESURF technology.

A novel self-modulated superjunction lateral double-diffused MOSFET (SM-SJ LDMOS) is proposed and experimentally realized in this letter. When a SJ is introduced into a lightly doped N-drift region, the 3-D depletion regions appear surrounding the P-pillars. This 3-D junction field effect transistor (JFET) effect decreases the current paths in both N-pillars and N-drift, causing a largely increased specific on-resistance ${R} _{\text {on,sp}}$ especially for the SJ with a narrow cell pitch. To suppress the inherent 3-D JFET effect, the SM-SJ structure is proposed by replacing the P-pillars with a series of P-islands. These P-islands with linearly reduced lengths modulate the surface electric field to increase the breakdown voltage ${V} _{{\text {B}}}$ while the N-drift areas between P-islands weaken the 3-D JFET effect to reduce ${R} _{\text {on,sp}}$ . Compared with the conventional SJ device, the measured ${V} _{\text {B}}$ of the SM-SJ LDMOS is increased by 53.1% from 260 V to 398 V with ${R} _{on,sp}$ reduced by 22.3% from 35.4 $\text{m}\Omega ~\cdot $ cm2 to 27.5 $\text{m}\Omega ~\cdot $ cm2.

In this article, the total ionizing dose (TID) effect is investigated in the 30-V split-gate trench (SGT) Vertical double diffused MOSFET (VDMOS). The complex trench structure, including gate oxide, split-gate oxide, and isolation oxide, is carefully studied to reveal the degradation mechanisms. Due to the multioxidation and annealing processes, the trench structure suffers serious oxide defeats. The analytical result shows a larger trapping efficiency ( ${f}_{{\text {ot}}}$ ) compared to the planar gate technology, leading to significant ${V}_{{\text {th}}}$ shifts and subthreshold leakage. Meanwhile, irradiation-induced trapped charges in the split-gate oxide have a great influence on the electric field profile in bulk, which gives rise to breakdown voltage (BV) degradation. The experimental result shows that BV presents a gradient descent and drops to as low as 14 V at 100 krad(Si). Through TCAD simulation and analytical calculation, these TID responses are evaluated, and three approaches have been proposed for the radiation hardness of SGT VDMOS.

The electrical characteristics of silicon-on-insulator (SOI) n-channel laterally diffused metal oxide semiconductor field effect transistors (NLDMOSFETs) are examined after exposure to the total ionizing dose (TID). The devices are partially radiation hardened in that the gate oxide (GOX) and the field oxide (FOX) have undergone a hardening process, but not the buried oxide (BOX). Two bias conditions, OFF-state and all terminals grounded, during irradiation are examined. The irradiated device shows that the OFF-state leakage current ( $I_{L}$ ) of these devices increases with the accumulated dose. The physical mechanisms for the $I_{L}$ are analyzed by technology computer-aided design (TCAD) simulation. The OFF-state leakage current ( $I_{L}$ ) can be explained due to the effects of radiation-induced trapped charge at the BOX silicon interface.

A shield gate trench MOSFET (SGTMOS) featuring narrow gate (NG) architecture and low-k dielectric layer (LDL), namely NL-SGTMOS, is proposed in this letter. By eliminating the middle portion of gate polysilicon without additional mask, and employing LDL between control gate and the grounded field plate (FP), the NL-SGTMOS can greatly reduce parasitic gate-to-plate capacitance induced by the FP, which is a common issue in conventional SGTMOS structure. T-CAD simulations and experiments are performed for evaluations of the proposed device. The fabricated 1-mm2 device (only with NG) achieved on-resistance of 4.57 $\text{m}\Omega $ and gate charge of 7.46 nC at gate voltage of 10 V, which show progressive performance among other existing technologies.

A novel high trigger current NPN transistor (HTC-NPN) with excellent double-snapback performance is developed in $0.5\mu \text{m}$ Bipolar CMOS DMOS (BCD) technology. A new floating N+ (FN) layer fabricated in drift-region not only induces two-stage snapback, but also achieves high trigger current ( ${I}_{\text {tr}}$ ) to provide ESD protection for high-voltage (HV) output port without being accidentally triggered on and latch-up like. The operational mechanism and the applied range of the HTC-NPN are discussed in detail, and the double-snapback process induced by the FN is explained via T-CAD simulation as well. From transmission line pulse (TLP) tested results, the proposed HTC-NPN achieved high ${I}_{\text {tr}}$ up to 1.5 A and controllable double-snapback characteristic, thus matching load line from HV output circuit well.

A lateral double diffused metal oxide semiconductor transistor with the semi-superjunction (semi-SJ LDMOS) is optimized based on the normalized current-carrying capability (CC) and experimentally realized in this letter. The device is fabricated based on an optimized equivalent substrate and the semi-SJ is introduced near the source. The semi-SJ increases the local doping concentration in the N regions meanwhile reduces the current path area and carrier mobility, resulting in the variation of CCs before and after the introduction of the semi-SJ. The normalized CC factor $\eta _{\text {C}}$ is proposed to evaluate this variation, with which the minimum specific on-resistance ${R} _ {\text {ON}, \text {sp}}$ is predicted by the condition of $\eta _{\text {C}}= {1}$ . The experiments of the semi-SJ LDMOS exhibit a minimum ${R} _ {\text {ON}, \text {sp}}$ of 25.5 $\text{m}\Omega \cdot $ cm2 under a breakdown voltage ${V} _{{\text {B}}}$ of 464.3 V. This represents a reduction in ${R} _ {\text {ON}, \text {sp}}$ by 37.7% when compared with the theoretical ${R} _ {\text {ON}, \text {sp}}$ of triple RESURF devices.

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a $0.17~ {\mu }\text{m}$ SOI layer with a source field plate covering the full drift region. Low specific on-resistance ${R} _{\text {on,sp}}$ is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage ${V} _{\text {B}}$ of 960 V with a superior figure of merit (FOM $= {V} _{\text {B}}{^{\text {2}}} / {R} _{\text {on,sp}}$ ) of 5.98 MW/cm2 when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

Breakdown voltage (BV) shifting behavior induced by total-ionizing-dose (TID) irradiation is investigated for high-voltage SOI LDMOS, in this letter. The BV increase caused by irradiation is present for the first time, and the degradation mechanism is revealed by modeling and simulation. Irradiation-induced electric field modulation exerts an impact on the competition between the lateral BV and vertical BV and results in BV shifting. The dielectric field is enhanced by irradiation-induced positive oxide trapped charges in the BOX layer, which is responsible for the BV increasing after irradiation. A TID radiation hardening approach is proposed so that the lateral BV is required to be properly higher than vertical BV instead of pursuing equality.

A small-size vertical device with field plate is designed and experimentally realized in this paper. The modulation effect of the field plate causes an enhanced bulk electric field (ENBULF) and improves the breakdown voltage ${V}_{\textsf {B}}$ . A 2-D electric field model is developed to give the ENBULF condition corresponding to the maximum ${V}_{\textsf {B}}$ and the optimal specific ON-resistance ${R}_{ \mathrm{ON},\textsf {sp}}$ . Based on the model, the minimum figure of merit (FOM) (gate charge ${Q}_{\textsf {g}}\times \mathrm{\scriptstyle ON}$ -resistance ${R}_{ \mathrm{ON}}$ ) is discussed for a typical ENBULF device, i.e., the shield-gate vertical double diffused metal–oxide–semiconductor (SG-VDMOS). The calculated results are in good agreement with the simulations. Furthermore, a 35-V SG-VDMOS is analytically designed and experimentally implemented, which obtains a ${R}_{ \mathrm{ON},\textsf {sp}}$ of 4.4 $\text{m}\Omega \cdot \textsf {mm}^{2}$ and a gate to drain charge ${Q}_{\textsf {gd}}$ of 11.3 nC, respectively. The experiment realizes the minimal FOM and a ${R}_{ \mathrm{ON},\textsf {sp}}$ reduced by 28.6% when compared with the conventional “silicon limit.”

The minimum specific ON-resistance $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semisuperjunction (semi-SJ) device is realized in this paper. Based on the similar SJ optimization method in our previous works, the minimum $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ of the semi-SJ is searched by optimizing both the semi-SJ and the N-buffer regions. The proposed design formulas give the optimized doping concentration $\text{N}_{\textsf {SJ}}$ of the semi-SJ region, doping concentration $\text{N}_{\textsf {B}}$ , and length $\text{L}_{\textsf {B}}$ of the N-buffer region, respectively. As examples, 1000- and 1500-V semi-SJ devices are designed with the formulas. The calculated results are in a good agreement with the simulations. The comparisons between the simulations and the existing experiments demonstrate that the optimization in this paper realizes lower $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ under the same breakdown voltage $\text{V}_{\textsf {B}}$ even with a shorter SJ length.

A novel superjunction (SJ) lateral double-diffused MOSFET (>950 V) with a thin layer SOI combining the advantage of low specific on-resistance ${R}_{\text {on,sp}}$ of the SJ and the high breakdown voltage ${V}_{\text {B}}$ of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced ${R}_{\text {on,sp}}$ without sacrificing ${V}_{\text {B}}$ . Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high ${V}_{\text {B}}$ . The experimental results exhibit a ${R}_{\text {on,sp}}$ of 145 $\text{m}\Omega \cdot $ cm2 with a ${V}_{\text {B}}$ of 977 V. This represents a reduction in ${R}_{\text {on,sp}}$ by 18.1% when compared with the theoretical ${R}_{\text {on,sp}} \propto {V}_{\text {B}}^{{2.5}}\vphantom {^{^{^{^{}}}}}$ “silicon limit”.

3-D edge termination design and analytic model for specific on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}})$ versus breakdown voltage (BV) of a 700-V triple reduced surface field lateral double-diffused MOSFET (LDMOS) with n-type top layer are presented in this paper. To eliminate the premature avalanche breakdown induced by the electric field crowding and the local charge imbalance in the transition region of the source-centered edge termination structure, 3-D numerical simulations and experiments are performed to investigate two crucial parameters ${L}_{1}$ and ${L}_{2}$ in the layout of the transition region. It is observed that optimal electric field distribution is obtained and breakdown positions are transferred to the active region at ${L}_{1} = 30~\mu \text{m}$ and ${L}_{2} = 1~\mu \text{m}$ . On the other hand, an analytic model is developed to describe the relation between ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV, which is obtained as ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}} = 5.93 \times 10^{-6} \times 22({T}/298)^{1.7} \times \text {BV}^{2}$ and theoretically verifies that the fabricated device has achieved optimized ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV. Compared with our previous paper, the LDMOS experimentally demonstrated improved performance with ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 86.49 $\text{m}\Omega ~\cdot $ cm2 and BV of 805 V, which is leading performance for the 700-V applications in published data.

The global optimization of the balanced symmetric vertical superjunction (VSJ) device is proposed based on the R-well model for the first time to realize the unique minimum specific on-resistance $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {min}}}$ . The R-well model, which is originated from our previous VSJ mode theory, shows the relationship between $R_{{\mathrm{\scriptscriptstyle ON}}}$ and the doping concentration N under the given pillar width W and breakdown voltage $V_{B}$ . The global $R_{{\mathrm{\scriptscriptstyle ON}}}$ optimization is realized to obtain the design formulas of N and the pillar length $L_{d}$ . The calculated results are in good agreement with the simulations. It is demonstrated from the comparisons with the simulations and the existing experiments that the optimization in this paper realizes the unique $R_{{on,\mathrm {min}}}$ with a relationship of $R_{{\mathrm{\scriptscriptstyle ON}}}\propto V_{B}^{1.03}$ . The R-well model is also universal for other $R_{on}$ optimizations.

The optimization methodology of the minimum specific ON-resistance $R_{\mathrm{\scriptscriptstyle ON},\textrm {min}}$ for the lateral superjunction device is proposed based on the concepts of charge and potential electric fields in this paper. From the $R_{\mathrm{\scriptscriptstyle ON},\textrm {min}}$ method, a new relationship between $R_{\mathrm{\scriptscriptstyle ON}}$ and breakdown voltage $V_{B}$ is developed, and the analytical formulas are obtained to directly give the doping concentration $N$ and the drift length $L_{d}$ . The calculated results, including the 800 and 1600 V examples, are in good agreement with the simulations. The optimized designs are also compared with the existing experimental and simulated data. It is shown that $R_{\mathrm{\scriptscriptstyle ON}}$ from the proposed optimization method is minimum, and the methodology of $R_{\mathrm{\scriptscriptstyle ON},\textrm {min}}$ is universal.

A 700 V dual-buried-layer n-channel lateral double-diffused MOSFET (DB-nLDMOS) based on substrate termination technology (STT) is presented and experimentally demonstrated in this paper. The termination region is well analyzed and designed to avoid the premature avalanche breakdown caused by the curved junction. The 2-D and 3-D numerical simulations have been performed to optimize the three key parameters of $\Delta L_{1,}\Delta L_{2,}$ and $\Delta L_{3}$ which impact on breakdown voltage (BV) greatly in the termination region. The simulation results show that the electric field peak is reduced and premature avalanche breakdown is avoided at the curved abrupt p-well/n-well junction with the STT. The experimental results demonstrate that low $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}}$ of 105.6 $\text{m}\Omega \cdot {\mathrm{ cm}}^{2}$ based on $L_{d}$ and high BV of 788 V are achieved by the DB-nLDMOS.

A new relationship between the specific ON-resistance $R_{\mathrm{\scriptscriptstyle ON}}$ and breakdown voltage $V_{B}$ for the balanced symmetric superjunction (SJ) device is presented to produce the lowest $R_{\mathrm{\scriptscriptstyle ON}}$ for a given $V_{B}$ . The design formulas, including the doping density NW and the drift length $L_{d}$ , are given for both the nonfull depletion (NFD) and the full depletion SJ devices with an introduction of the normalized $V_{B}$ factor $\eta $ . For the NFD SJ MOSFET, an $R_{\mathrm{\scriptscriptstyle ON}} \propto V_{B}^{1.03}$ relationship is obtained. The analytical results show good agreement with the numerical results.

An ultralow turn-OFF loss ( ${E} _{\mathrm{\scriptscriptstyle OFF}}$ ) silicon-on-insulator lateral insulated-gate bipolar transistor with a p-buried layer (PB SOI LIGBT) is first proposed. A universal ${E} _{\mathrm{\scriptscriptstyle OFF}}$ model during inductive load turn-OFF is set up, which reveals that low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ can be achieved by reducing the total integral current charges, reducing the average anode voltage in the first phase and increasing the charge factor ${k}$ . Due to the large capacitance effect and extra hole extraction path induced by the PB, the three ideas for low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ are demonstrated in the PB SOI LIGBT. Simulation results show that the PB SOI LIGBT can achieve an 85% lower ${E} _{\mathrm{\scriptscriptstyle OFF}}$ compared with the conventional SOI LIGBT based on 6- $\mu \text{m}$ SOI layer. Furthermore, the proposed ${E} _{\mathrm{\scriptscriptstyle OFF}}$ model can be applied to all the IGBTs, and it reveals the mechanism of low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ of the IGBT with a superjunction structure during inductive load switching.

An analytical model for a novel triple reduced surface field (RESURF) lateral double-diffused metal–oxide–semiconductor (LDMOS) field-effect transistor with a low on-resistance n-type top (N-top) layer is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF LDMOS is presented by solving the 2-D Poisson’s equation, which can also be applied in single, double, and conventional triple RESURF structures. The vertical and lateral breakdown voltages are formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of the N-top layer ( $Q_{\textrm {ntop}}$ ) is derived which can give a guidance for the dose of N-top layer. The triple RESURF LDMOS with a low on-resistance N-top layer is designed and manufactured according to the analytical model. All the analytical results can be well verified by numerical and measured results, showing the validity of the presented model.

The Backgate (BG) effect on specific ON-resistance ( $R_{{{\mathrm{{\scriptscriptstyle ON}},\rm sp}}})$ and breakdown voltage (BV) for the thin layer Silicon On Insulator (SOI) field p-channel lateral diffusion MOS (pLDMOS) are investigated in this paper. BG-induced dual conduction mode for the thin layer SOI field pLDMOS is revealed, which includes drift and accumulation conduction. Hole accumulation layer induced by BG voltage ( $V_{\rm BG})$ provides extra charges, resulting in a $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ reduction. An expression of equivalent $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ is given to describe the dependence of $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ on $V_{\rm BG}$ . Simultaneously, $V_{\rm BG}$ impacts strongly on BV, inducing three breakdown mechanisms: surface breakdown, bulk breakdown, and punchthrough breakdown. For surface breakdown, a positive linear dependence of BVs on $V_{\rm BG}$ is given with consideration to multiple $_{_{}}$ field plates (MFP). BV of −366 V and $R_{{{\mathrm{{\scriptscriptstyle ON}},{\rm sp}}}}$ of $7.5~\Omega \cdot $ mm $^{2}$ for the thin layer SOI field pLDMOS are achieved experimentally at $V_{\rm BG} = -200$ V.

A novel vertical field plate (VFP) lateral device with ultralow specific on-resistance (RON,sp) is proposed in this paper. The VFP surrounded by oxide is inserted in the bulk of the drift region. Compared to the surface local depletion of the conventional lateral field plate (LFP), the depletion layer of the VFP expands to the bulk of the drift region, which enhances the bulk electric field. Therefore, ultralow RON,sp is realized in the VFP device due to high drift-region doping (Nd) and short cell pitch. An analytical FP model is developed to describe the behavior of the VFP, in which the breakdown voltage (BV) and Nd are found to be proportional to the FP factor k. Then the uniform-doped VFP laterally diffused MOSs and the step-doped VFP laterally diffused MOS are proposed. The optimized device exhibits a BV of 945 V and a RON,sp of 34 mΩ·cm2 which are superior to those of similar devices and the silicon limit.

The equivalent substrate (ES) model and the accordant optimized structure for the lateral super junction (LSJ) device are proposed in this paper. The ES, defined as the combination of the depleted substrate under the reverse voltage and the charge compensation layer (CCL) in the substrate, is treated as a whole to analyze the modulation impact of the compensation electric field ΔE on the total electric field of the LSJ. The analytical formulas for the surface electric field profiles of the LSJ are deduced from the 3-D Poisson equation and the Green function. The ES model reveals the essence and the suppression of the substrate-assisted depletion effect in the LSJ, from which the optimized substrate conditions are achieved. The optimized substrate condition allows the LSJ device featuring a similar breakdown voltage to that of the vertical super junction. Then four typical doping concentrations of the CCLs with four different compensation electric field strengths ΔEs are compared. The developed novel device with optimized CCL delivers a breakdown voltage of 301 V, realizing 157% improvement compared with the conventional LSJ with Ld=15 μm, which shows a superior performance to the LSJ devices reported. It is noteworthy that the ES model can also be used to analyze other LSJs.

A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R on,sp ) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R on,sp and high BV of above 730 V are achieved by the JITR LDMOS. R on,sp of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV 2 /R on,sp ) in comparison to the published SJ LDMOS.

A band-to-band tunneling injection insulated-gate bipolar transistor (IGBT) featuring a tunnel junction as the collector p-n junction is proposed. The tunnel junction injects not only holes into the n-drift region by diffusion when it is forward biased but also electrons by band-to-band tunneling when it is reverse biased. Thus, the proposed device shows the output characteristics of a reverse conducting IGBT (RC-IGBT). Compared with the conventional RC-IGBT, which is prone to current concentration, the proposed device conducts current uniformly in both forward and reverse conducting states, which are favorable to the increase in conducting capability and the reduction in the reverse recovery peak current. During the reverse recovery, the electrons extracted from the drift region to the collector induce the hole injection into the drift region, which leads to the soft reverse recovery of the built-in diode. In addition, the technological ease of fabrication (no backside photolithography) is another attraction of the proposed device.

A novel 300-V high-side thin-layer-SOI field pLDMOS adopting field implant (FI) technology and multiple field plates (MFPs) has been developed. Breakdown mechanisms of back gate (BG) punchthrough and avalanche breakdown for highside thin-layer-SOI field pLDMOS are investigated by setting up an analytic model, simulating, and verifying experimentally. Shallow junction depth of p-field achieved by the proposed FI technology attenuates BG punchthrough effect; premature surface avalanche breakdown can be avoided by using MFPs. High-side field pLDMOS with a breakdown voltage (BV) of 340 V is experimentally realized on a 1.5-μm -thick SOI layer and successfully applied in a 200-V high-voltage switching IC.

An ultralow specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) power lateral MOSFET is proposed. The MOSFET features double trenches: an oxide trench in the drift region and a trench gate extended to the buried oxide (BOX) (SOI DT MOSFET). First, the oxide trench causes multiple-directional depletion, which leads to electric field reshaping and an enhanced reduced surface field effect in the SOI layer. The electric field distributions in the SOI and BOX are thus improved. The oxide trench also increases the electric field strength in the x-direction due to the lower permittivity of oxide than that of Si. Both increase breakdown voltage (BV). Second, the trench makes the drift region folded in the y -direction, resulting in reduced cell pitch and Ron,sp. Third, the trench gate extended to the BOX further reduces Ron,sp by widening the vertical conduction area. The BV of the DT MOSFET increases from 91 V of the conventional SOI LDMOS to 233 V at a half-cell pitch of 6.5 μm, and the Ron,sp decreases from 5.1 to 3.3 mΩ·cm2.

Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the proposed structure, ionized donors in n-islands enhance the bottom-interface electric field of the SOI layer from 10 V/mum in the conventional devices on p-SOI layer to 27 V/mum, resulting in enhancement of the BOX electric field EI from 30 to 82 V/mum. Moreover, holes located between the depleted n-islands help to increase EI as well. Both improve the blocking capability of the device. A 660-V SOI LDMOS is obtained, in which the implanted n-type drift region, along with the n-islands on a p-type SOI layer, realizes the self-isolation in HVIC.