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A depletion MOS controlled (DMC) current regulator diode (CRD) based on bipolar carrier transport mechanism is proposed and experimentally demonstrated in this paper. Compared with the conventional CRD based on unipolar junction field effect transistor, DMC CRD features a highly doped p-type substrate. On the one hand, the P+ substrate provides hole injection, which makes the output characteristics of DMC CRD resemble a PIN rectifier when operating in the linear region with a small anode voltage. Accordingly, DMC CRD gets a large slope of output characteristic to realize a lower knee voltage (VK) in comparison to the conventional CRD for a same anode current. On the other hand, the P+ substrate and N-type epitaxial layer can form a reverse PN junction to withstand a high reverse breakdown voltage, which allows DMC CRD to be applied in AC circuit. The initial experimental result demonstrates that a low VK of 1.2 V and a high reverse breakdown voltage (BVR) above 250 V are achieved in a 30-mA-level DMC CRD.

This paper proposed a novel integrated low capacitance transient voltage suppressor (ILC-TVS) for system-level Electrical Over Stress or Electro-Static discharge (EOS or ESD) protection. Compared with the regular TVS, the new one can be fabricated using standard bipolar technology and also possesses the good system-level ESD robustness. By a newly-proposed anode extension technology (AET), the input common-mode capacitance at "0 bias" state is suppressed from 0.78 pF down to 0.65 pF, which realizes the smoother capacitance curve with bias voltage increasing from 0~5 V. According to the standard EOS/ESD tests, the novel ILC-TVS gets the IEC 61000-4-5 EOS peak current (I PP ) of 5.26 A and endures the IEC 61000-4-2 contact mode ESD stress of ± 11 kV. Therefore, the ILC-TVS can provide robust ESD protection for high-speed data interface by on-chip or off-chip design.

In this work, a high-voltage (HV) junction field effect transistor (JFET) with voltage class extended to 800 V is proposed, which obtains a satisfactory on-state breakdown voltage (ON-BV) performance. For the traditional HV JFET, ON-BV is much lower than OFF-BV, which cannot meet the requirement for the application of high voltage start-up circuit. In pursuit of a high ON-BV and making it close to OFF-BV, a dilute-doped resistance region is introduced in the HV JFET to mitigate space-charge-modulation (SCM) effect without additional mask and area. By appropriately increasing the dose of Deep N-Well (DNW), ON-BV can be further increased without degrading OFF-BV. At last, the proposed JFET obtains a high OFF-BV of 900 V and a high ON-BV of 965 V without sacrificing the competitive current capacity above 0.11 mA/μm. Besides, the mechanism of power loss (P LOSS ) induced by substrate current (I SUB ) and gate current (I Gate ) during charging process is also revealed, which is associated with SCM. Benefit by the mitigation of SCM, I SUB +I Gate is reduced significantly in the proposed structure.

The distribution of radiation induced positive oxide trapped charges (N ot ) in buried oxide (BOX) with different applied electric fields for high-voltage (HV) SOI LDMOS is investigated. In contrast to the traditional model which depends upon N ot buildup near the interface that the field line points to, the verified experimental results in this work indicated that there are still a non-negligible set of N ot generated in SOI/BOX interface even if the electric field plays a negative role (field line perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX). The improved model on BOX damage induced by TID considering this set of N ot and its saturation effect is proposed and adopted in accurate simulated analysis to predict the post-irradiation device behavior. The mechanism of HV SOI LDMOS degradation during irradiation is also revealed. The radiation hardening LDMOS in this work keeps breakdown voltage above 120 V at D=500 krad(Si).

A new narrow gate (NG) trench MOSFET with stepped field plate (SFP) and polysilicon bridge (PB), named NSP-MOSFET, is proposed and discussed in this paper. The SFP can smooth electric field profile along trench, thus improving doping concentration of epitaxial layer and reducing specific on-resistance (R ON,SP ). The NG reduces parasitic gate capacitance and gate charge (Q G ). In addition, the PB can partly offset the increase of internal gate resistance induced by the NG. T-CAD simulations are performed to evaluations of fundamental performances. Benefiting from structural improvements, the proposed device obtains about 22 % and 9.5 % reductions in R ON,SP ×Q G compared with conventional trench MOSFET and SFP trench MOSFET, respectively.

A novel low gate charge $(\mathrm{Q}_{\mathrm{g}})$ vertical power MOSFET (VDMOS) based on high-doped pinch-off region and stepped trench shield gate is proposed in this work. The easy-depleted pinch-off region not only functions as a series depletion capacitance connected to the drift region, but also introduces lateral coupling effect with P-body and shield plate. Combination of the two leads to a great reduction in $\mathrm{C}_{\mathrm{gd}}$ . Besides, the metal plug of trench shield gate realizes an integrated Schottky contact without additional area, improving reverse recovery performance. Simulation and modeling are presented to evaluate the $\mathrm{C}_{\mathrm{gd}}$ shielding effect and reveal internal mechanism. Compared with conventional shield gate trench (SGT) device, $\mathrm{Q}_{\mathrm{gd}}$ and $\mathrm{Q}_{\mathrm{g}}$ are reduced by 65% and 59%, and $R_{on,sp}\cdot \mathrm{Q}_{\mathrm{g}}$ achieves a decrease of 53%.

A novel dielectric termination technology (DTT) is proposed and experimentally demonstrated in this paper. The proposed DTT shows a 3-D structure with the fingertip region surrounded by the equal-potential trench dielectric rings. The potential difference $\Delta V$ between every two adjacent rings is clamped as a constant of $\Delta V = V_{\mathbf{B}}/\mathrm{N}$ with $\mathrm{V}_{\mathbf{B}}$ and N being the breakdown voltage and ring number. The electric field lines in the DTT structure are all ended at the adjacent equal-potential rings. So the curvature effect is suppressed and a uniform surface electric field is realized in the DTT structure. Based on the equal-potential principle, the ring interspace can be further reduced to obtain a voltage sustaining length $\mathrm{L}_{\mathbf{T}}$ in the DTT shorter than the drift length $\mathrm{L}_{\mathbf{d}}$, even realize a full-dielectric termination. In the experiments, the $\mathrm{L}_{\mathbf{T}}$ of DTT varies from 38 $\mu$m to 25 $\mu$m with the same $\mathrm{L}_{\mathbf{d}}$ of 35 $\mu$m. The tested $\mathrm{V}_{\mathbf{B}}$ is a constant of 600 V, which realizes a maximum average electric field of 24 V/$\mu$m in the DTT region and a termination factor $\mathrm{k}_{\mathbf{T}} = L_{\mathbf{T}}/\mathrm{L}_{\mathbf{d}}$ of 0.714. The $\mathrm{k}_{\mathbf{T}}$ of DTT is reduced by about 52.4% to 71.4% when compared with the $\mathrm{k}_{\mathbf{T}}$ values of the typical reported conventional JTT structures.

Hot-hole induced burnout phenomenon in a high-voltage triple reduced surface field (RESURF) LDMOS with sandwich N-P-N layer is investigated in this work. The sandwich N-P-N structure is employed in the drift region of LDMOS to obtain a further optimized trade-off between specific on-resistance (R$_{on,sp}$) and breakdown voltage (BV). However, experimental results show that the BV drops in the off-state with a period time of 2.7 s and the device burns out. To solve this problem, the corresponding burnout mechanism is analyzed and its countermeasure is proposed and demonstrated by simulation and experiment. As a result, a competitive performance with a low R$_{on,sp}$ of $32.38 \mathrm{m}\Omega \cdot cm^{2}$ and a high BV of 535 V without burnout is achieved for the triple RESURF LDMOS with sandwich N-P-N layer.

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with three-dimensional floating vertical field plate (3-D F-VFP) is proposed in this paper. The 3-D F-VFP LDMOS features a discrete pillar-type VFP array through the N-type drift region and the VFP pillars with the same distance from the source are connected to each other to realize the equal potential. In the off-state, the potential along the drift region are pinned by the series of equal-potential F-VFP rings and a new full-region depletion mode is introduced into the bulk of the device. Therefore, the highly doped drift region is depleted by the 3-D F-VFP, establishing a self-adaptive charge balance inside the drift region. In the on-state, the current flows through the gaps among all the F-VFP pillars, preventing the long current path and reducing the on resistance $\boldsymbol{R}_{\mathbf{on}}$ . A 3-D F-VFP LDMOS is experimentally implemented, which obtains a breakdown voltage $\boldsymbol{V}_{\mathbf{B}}$ of 630 V and a $\boldsymbol{R}_{\mathbf{on}}$ of $344.8\ \mathbf{\Omega}$ compared with 550 V and $722.5\ \mathbf{\Omega}$ of the device without the F-VFP. The measured saturation current of the 3-D F-VFP LDMOS is more than 4.5 times of that of the device without F-VFP.

The electrical characteristics variations of 400V SOI NLDMOS after exposure to total dose irradiation are discovered. The mechanisms of these variations are analyzed and confirmed by TCAD simulations.

The coupling effect between the motion error and the topography results in quality degradation of the airborne SAR image. An autofocus algorithm based on topography searching is proposed to improve the focusing quality. It adjusts the target height to compute the motion compensation amount, and then selects the one with the best focusing quality as the final result. The algorithm is implemented by a block-by-block scheme to process the coarse-focused image, so the focusing quality of the whole image can be proved. The proposed algorithm is validated by simulation results.

To realize the minimum specific on-resistance R on, sp of the lateral superjunction (SJ) devices, the low resistance characteristic of the SJ should be adequately used and the adverse influence of substrate-assisted depletion (SAD) effect on the breakdown voltage V B should be eliminated. From our previous equivalent substrate (ES) model, the SAD effect is completely suppressed if the ES is optimized. In this paper, the balanced symmetric SJ satisfying the optimized ES condition is defined as the ES-SJ. Based on the ES-SJ concept, the non-full depletion (NFD) mode of the lateral SJ is proposed and experimentally realized for the first time. In the experiments, the optimized ES is obtained by a linearly doped charge compensation layer (CCL) with a field plate covering the full drift region and the NFD SJ is implemented with a narrow width of 0.8 μm by implanting the SJ region thrice. The measured results exhibit a R on, sp of 30.9 mΩ·cm2 with a V B of 477 V, which obtains a reduction in R on, sp by 67.8% when compared with other SJ devices under the similar V B .

Total Ionizing dose effect induced current degradation for 300V SOI NLDMOS is investigated in this paper. The degradation mechanism of conduction drain current at on-state and leakage current at off-state is revealed by simulation and experiment. The conduction current increasing is ascribed to the reduction of the on-resistance by trapped charges in multiple interfaces. The leakage current increasing is ascribed to the weak inversion layer under filed oxide layer induced by trapped charges. Experiment result shows the annular termination structure benefits to suppress the degradation of leakage current.

Total-ionizing-dose radiation response for 600V ultra-thin layer SOI LDMOS transistor is investigated. Radiation conduction modulation model is proposed to reveal the degradation mechanism of conduction current and breakdown voltage. Multi-interface irradiation damage cause positive net trapped charge, which reduces on-resistance equivalently and enhance conduction current. Meanwhile, they suppress the depletion in the drift region at off-state and then decrease breakdown voltage. Based on the model, irradiation induced net trapped charge density are extracted to evaluate the irradiation damage in drift region.

A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (I esd ) path to improve the holding voltage (V h ) and failure current (I t2 ). The relation between V h and base-concentration (N b ) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing V h by changing N b . The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the I ESD distribution and V h . The longer ESD current path improves the V h by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the I t2 . DC and dynamic TLP simulation results show the V h = 5.3 V of proposed SCR is achieved with a higher failure current (I t2 ) of 1.68e-2A/μm.

A novel DTI double RESURF LDMOS with P-sink layer is presented and experimentally demonstrated in this paper. The novel structure features a P-sink layer around the bottom of deep trench, which is formed with the Deep N-type Well (DNW) after the process of high temperature driving in. The highly doped P-sink layer restrains the extension of depletion region along the horizontal direction, improving the isolation performance. According to the simulation results, the surface electric field peak of the proposed DTI LDMOS is reduced by 35 % due to the enhanced depletion effect of P-sink layer. Meanwhile, the concentration of DNW and P-top region are increased, thus the R on, sp is decreased. Furthermore, the isolation region area is reduced significantly so that the chip size will be minimized. The LDMOS with R on, sp of 96.2 mΩ·cm2 and BV of 758 V is experimentally achieved, which breaks the conventional R on, sp -BV silicon limit of double RESURF technology.

This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (R on, sp ) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (R on, sp ) by shortening the current flow path and smooth the surface electric field. Meanwhile P-buried layer is introduced to assist depletion and enhance the charge density of drift region, which reduces R on, sp further and keep higher breakdown. The R on, sp of proposed USTI-LDMOS devices is very competitive, 18V LDMOS has BV DSS =27V and R on, sp =7.1 mΩ·mm2; 20V LDMOS has BV DSS =30V and R on, sp =8.8mΩ·mm2; 30V LDMOS has BV DSS =42V and R on, sp =14.5mΩ·mm2; 40V LDMOS has BV DSS =52V and R on, sp =20.5mΩ·mm2.

This paper presents three-dimensional (3-D) edge termination design of a 700-V triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with n-type top (n-top) layer. It is found that breakdown characteristics deterioration related to the electric field crowding and the local charge imbalance in the edge termination. The two crucial parameters L P and L 2 in the layout of the transition region of the edge termination were studied by 3-D numerical simulations and experiments to overcome these issues. As implantation dose of n-top layer (D ntop ) increases from 0.8 × cm−2 to 1.2 × cm−2, progressive performance with Fs from 805 V to 711 V and R on, sp from 86.49 mΩ· cm2 to 80.56 mΩ·cm2 is experimental obtained and the novel LDMOS demonstrates maximum figure of merit (FOM) in the latest existing 700-V LDMOS technologies.

A low turnoff loss (Eoff) silicon-on-insulator lateral insulated gate bipolar transistor with p-buried layer and double gates (DG-PB SOI LIGBT) is proposed. The proposed LIGBT features a p-buried layer (PB) in the n-drift region and an additional trench gate. Due to the large capacitance effect and hole extraction path induced by PB, larger number of the carriers is removed under low anode voltage (VA), which contributes to a fast turnoff and low turnoff loss (Eoff). What's more, the double gates (DG) structure can reduce the overall stored carriers in the on-state, further improving the Eoff ∼ Von tradeoff. Simulation results show that the DG-PB SOI LIGBT can achieve an 83 % lower Eoff compared with the conventional SOI LIGBT at the same Von of 1.05 V.

NBTI of BOX layer induced degradation for thin layer SOI field p-channel LDMOS is investigated by experiment, modeling and simulation. Decrease in drain current (Id) under high negative BG voltage (VBG) stressing is observed, which is ascribed to the positive fixed oxide charge and interface charge in BOX layer induced by NBTI. The NBTI conduction modulation model is proposed to elevate the positive charge density (ΔQp) generation in the BOX layer. The total on-resistance is enhanced because of hole concentration in the accumulation layer reduced by the positive charges. Simulated Id shift with applying the corresponding ΔQp in the BOX layer shows a good fitting with the measured result. Meanwhile, ΔQp in the BOX layer relaxes the electric field peak at the p-drift/n-well junction on the SOI/BOX interface, which is responsible for breakdown voltage (BV) increasing.

An area-efficient matrix-driving circuit in power IC with 96 outputs is proposed. The conventional circuit structure used the same logic control unit and high-voltage level shifter in each driving channel. By using matrix-driving circuit for the same output function, compared with the conventional circuit design with 96 sets of logic control unit and level shifters, the proposed IC can be utilized with only 22 sets. The chip size is reduced significantly by 42%.

A 200-V SOI p-channel pLDMOS with thick gate oxide layer is presented in this paper. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The field implant (FI) technology is adopted to eliminate channel discontinuity at the bird's beak region. The influences of key parameters on on-state breakdown voltage (BV ON ) and off-state breakdown voltage (BV off ) of the SOI pLDMOS are discussed. The SOI pLDMOS with BVoff of −240 V is experimentally realized, and is successfully applied to HV driving IC.

A novel high-voltage (HV) thick layer silicon-on-insulator (SOI) field p-channel lateral double-diffused metal-oxide semiconductor (pLDMOS) with single trench isolation is developed for HV switching IC based on 11-µm-thick silicon layer and 1-µm-thick buried oxide layer. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The deep trench is adopted to realize the compatibility between HV pLDMOS and LV CMOS. The device parameters T, Y for the HV SOI field pLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage (BV). The HV SOI field pLDMOS with a BV over 200V is experimentally realized and successfully applied to a 96-bit output driver integrated circuit (IC).

In this paper, the effect of field implantation (FI) on off-and on-state characteristics for thin layer SOI field P-channel LDMOS (FPLDMOS) is investigated. FI effect mechanisms are revealed by modeling, simulating, verifying experimentally. The channel discontinuity gives rise to current step in output curve due to strong electric field and impact ionized generation. Back gate (BG) punch-through breakdown weakens severely block capability. Process parameters for FI technology are optimized to avoid channel discontinuity and BG punch-through breakdown. The rugged thin layer SOI FPLDMOS with channel continuity and punch-through breakdown voltage of −329 V is realized experimentally, and successfully applied in 200-V switching IC.

A vertical current regulator diode (CRD) with trench cathode based on double epitaxial layers is proposed and experimentally demonstrated. Double epitaxial layers structure is induced not only to achieve high breakdown voltage (V B ) but also to improve the saturation characteristics. Long-channel is realized by implanting boron after trench etching, which further improves the IV characteristics. Experimental results show that the proposed CRD presents well IV characteristics and a high V B above 200 V. What's more, the CRDs of different regulating current levels are achieved in the smallest device size of 470 × 470 μm2 among all the reported CRDs with the same application voltage for LED lighting.

A 700 V self-ISO (isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) without epitaxy is proposed in this paper. By separately implanting deep junction NWELLs, drift region of low doping concentration in neck region is achieved. This alleviates the concentration of the electric field and avoids premature avalanche breakdown around the bird's beak. Furthermore, introduction of triple RESURF (reduce surface field) technology and optimal device sizes benefit for ultra-low R on,sp (specific on-resistance). Finally, this ISO DB-nLDMOS is experimentally integrated in a 700 V BCD process platform. Testing results show that proposed device achieves 780-V BV ds , 10.4-Ω·mm2 R on,sp and 20-V floating voltage of source electrode.

Integrated in a 0.35 μm 700 V BCD process platform, ultra-low Ron, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which Ron, sp are 11.5 Ω·mm2 and 11.2 Ω·mm2, respectively. Utra-low Ron, sp benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.

An ultra-low specific on-resistance (Ron, sp) high voltage trench SOI LDMOS based on the enhanced bulk field (ENBULF) concept is proposed. The key feature of this new device is heavily doped N/P pillars parallel to the trench oxide layer. The bulk electric field of the trench LDMOS is enhanced both in the dielectric and the silicon layer by using the N/P pillars. Firstly, the highly doped N/P pillars introduce two new electric field peaks in the bulk of the drift region, which enhances the bulk electric fields both under the drain and source. Secondly, the additional electric field of the trench oxide layer is produced by N/P pillars, leading to a shrink of the drift area. Thirdly, the enhanced dielectric layer field (ENDIF) effect of the BOX layer occurs self-adaptively with different thicknesses of the BOX layer. Combining the trench and SJ technologies, the cell pitch is reduced and the optimized doping concentration of the drift region is increased. The Ron,sp is therefore reduced efficiently. The 2-D analytical model of the ENBULF LDMOS is developed to guide the design of the novel device. Based on the model and the simulation, the ENBULF LDMOS exhibits a offstate BV of 684 V and a Ron, sp of 48.5 mΩ·cm2. The new device breaks through the silicon limit in a wide applied voltage levels.

Super junction (SJ) concept is attractive for power devices because of its advantage for improving the tradeoff between the breakdown voltage (BV) and the on resistance (R on ). It is an acknowledged wish to apply the SJ concept to LDMOS for the power integrated circuits (PICs). However, the conventional SJ LDMOS is no practical due to the influence of the fabrication process, charge imbalance, and junction termination, etc. This paper introduces the key technologies for the SJ LDMOS based on our researched SJ device named SLOP (Surface Low On-resistance Path) LDMOS, aiming to offer applicable lateral SJ device for the PICs.

Lateral Double Diffusion MOSFET is widely used due to its excellent properties. However, the contradictory between on-resistance and breakdown voltage (BV) is proved to be the technical bottleneck of optimizing power devices. On one hand, technologies such as REduce SURface Filed (RESURF), Field Plate and Variation of Lateral Doping are applied to enhance the breakdown characteristics of power devices. On the other hand, due to the limits of silicon material, to reach a higher breakdown voltage, the on-resistance must be set higher. The proposed structure, comparing with conventional structure, exhibits a higher breakdown voltage property while keeping the on-resistance invariant.

We investigated the impact of field plate of PLDMOS in thick film SOI with due consideration to gate field which is connected to gate electrode. SOI PLDMOS is employed in the level shifters and multi-output stage in scan driver for PDP. We have simulated the current capability, the saturate current of gate field plate(GFP) structure has obtained about 30% larger than source field plate(SFP), and has better thermal effects. GFP structure in our fabricated IC is experimentally realized with the device width of 1200μm, the current drivability can reach 400mA in output stage.

A 300 V thin layer SOI nLDMOS based on reduced surface electric field (RESURF) and multiple field plates (MFP) is proposed in this paper. RESURF principle and MFP technology are adopted to modulate the electric field distribution and improve the breakdown voltage (BV). Device structure parameters are discussed to achieve a trade-off between breakdown voltage and on-resistance. Compared with conventional structures, the achieved 300 V nLDMOS not only owns high BV, but also possesses a simple manufacturing process and a low cost.

A novel HV thin layer SOI technology based on 1.5-µm-thick silicon layer for negative HV power supply has been first proposed. HV field nLDMOS with thick gate oxide, HV pLDMOS with thin gate oxide and LV CMOS are compatible with shallow trench isolation. Gate and source field plates are adopted to improve the breakdown characteristics of HV field nLDMOS since it doesn't meet SOI RESURF criterion. N-field with shallow junction depth is introduced to eliminate channel discontinuity around the “beak” region at the source side of HV field nLDMOS and avoid punch-through breakdown induced by BG effect of HV field nLDMOS. The influences of key parameters on breakdown mechanism are discussed and optimal parameters are obtained to achieve well characteristics of HV field nLDMOS for negative HV power supply. A negative HV switching IC using the proposed thin layer SOI technology shows that both the rise and fall times of the output stages are less than 50 ns under the negative supply voltage of −100 V and the load capacitance of 5000 pF.

Green society is the society that human and nature develop together harmoniously. It is a concrete manifestation of sustainable development society. Green campus is an important component of green society. Building a green campus not only benefits the school's standard management and sustainable development, but also is the practice of the Party's inherent requirement of the Scientific Development and is to meet the actual needs of China's national conditions. This article firstly introduces the topography and the geomorphology of the new campus of Hunan University of Technology and Science, secondly analysises on the feasibility of carrying out green construction, thirdly focuses on water source heat pump air conditioning system, ecological sewage disposal system and drinking water system. Finally, it advises some effective measures to improve those, and makes some effective forecasts for reference.

Time-frequency transform is applied into InISAR for multiple moving targets imaging. By means of interferometric processing to range-Doppler images, the range-azimuth image can be derived from the interferometric phase. The restriction of millimeter-wave (MMW) phase wrapping is solved by multiple baseline.

With the increase of service time, more and more attention has been paid on the long-term performances of silicone rubber (SR) composit insulator. After analyzing the characteristics of ageing process of domestic composite insulators in service, we put forward an improved method of 5 000 h multi-factor accelerated artificial ageing test based on IEC 5 000 h Multi-factor aging test method. This method is planned to more reasonably simulate the pollution process of composite insulators in the industrial inland pollution environment that contains heavy ESDD & NSDD contaminants, which can represent most domestic pollution environment, The melioration of the new method comprised prolonging the time of ageing factors. This method not only can satisfactorily rank performances of composit insulators and screen composit insulators, but also can successfully simulate environmental characteristics in service.

In order to measure center of gravity of payload rack, a method is put forward to solve this problem by theory of torque balance in rotating coordinate system. Forward computation is used to calculate the weight and center of gravity of payload rack. Then makes an accuracy analysis of this method by inverse computation which focuses on calculating sensor readings including maximum expected errors, and finally makes an accuracy comparison when the payload rack weight is 10000 N and 1000 N. The results show that: if the accuracy of the sensors is 0.01%, measured weight is within 0.3% of actual weight, each of measured center of gravity is within 3 mm of actual center of gravity, and higher accuracy could be achieved by further increasing the weight of the rack under the same condition.

Friction is the key factor influencing high precision and super low-speed running performance of AC servo system. In order to factually simulate the influence of friction on AC servo system, three-loop nonlinear model of industry AC servo motor including measured Stribeck friction disturbance factors is established. The control performance of position loop is simulated and studied by adopting traditional PID and fuzzy PID. The results show that Stribeck friction can lead to “flat top” of position tracking and “dead zone” of speed tracking adopting traditional PID, while fuzzy PID decreases the influence of friction on servo system performance and improves tracking precision and robust performance of the system.

A novel partial silicon-on-insulator (PSOI) high-voltage LDMOS is proposed and its breakdown mechanism is investigated numerically and experimentally. The PSOI LDMOS features double-sided charge trenches on the top and bottom interfaces of the buried oxide (BOX) (DTPSOI). In high-voltage blocking state, the charges located in the trenches enhance the electric field strength in the BOX, and a Si window makes the substrate share the vertical voltage drop and modulates the lateral field in the SOI layer. Both increase the blocking voltage (BV). A BV>700V DTPSOI LDMOS is realized on a 8μm-thick SOI layer over the 1.2μm BOX and 1.5μm-deep trench. Moreover, the Si window alleviates the self-heating effect.

Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N+&P+ and a deep P+ are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.

A novel substrate-assisted (SA) RESURF technology aiming at improving off-state breakdown voltage (BV) of PN junction with small curvature radius is proposed and experimentally demonstrated in this paper. The SA RESURF technology not only realizes small curvature radius in the fingertip region, but also reduces electric field concentration in the curved metallurgical junction. Low-doped P-substrate, which increases depletion of the small curvature radius junction and reduces electric field concentration in the curved metallurgical junction, is adopted in the source fingertip region. Owing to the existence of low-doped P-substrate, the abrupt PN junction with small curvature radius is adjusted to low-doped PN junction with large curvature radius. The SA RESURF technology can be widely applied to lateral high voltage devices with small curved junction, especially to lateral super junction devices. A CBSLOP-LDMOS with the proposed SA RESURF technology has been developed. The experimental results show that the CBSLOP-LDMOS exhibits off-state BV of 700 V and specific on-resistance (R on, sp ) of 142 mΩ·cm2.

A SA-LIGBT with N+ diffusion and N-buffer layer in the anode has been described and analyzed. The onset voltage, on-resistance and turn-off speed of the device can be optimized by adjusting the width of P+ diffusion paralleled with N+ diffusion in the anode. A robust SA-LIGBT is optimized and fabricated successfully in a p-type single crystal without epitaxial layer or buried layer. The experimental SA-LIGBT has a breakdown voltage of 787 V, specific on-resistance of 53 mohm·cm2, turn-off time of 310 ns and onset voltage of 1 V. These qualities make it possible to apply the proposed SA-LIGBT in power integrated circuit.

In order to realize automatic trapezoidal thread manufacturing of large diameter fiber reinforced plastic (FRP) pipe, the numerical control machine tool, which can implement pre-taper manufacturing and thread grinding, is designed. This paper introduces the mechanical structure and the composition of the open numerical control system. A three-loop control model with friction effects is built for the radial axis servo platform which runs at low speed. The friction model of the motion platform is fitted by experiment data, and the friction dynamics simulation for low speed operation characteristics of speed loop and position loop is conducted. The influence of none-linear friction on dynamic characteristics of the servo platform is researched. The feedforward friction compensation control is applied to eliminating the phenomenon of “dead zone” and “flat top” caused by friction, and the low speed performance and the tracking accuracy are improved, which realizes the thread grinding of large diameter high-pressure FRP pipes with high accuracy.

Traveling speed of vehicle has a very important effect on the occurrence of road traffic accidents and the harmfulness of the accidents. The speed display error and its distributive regularity would be researched in depth. Based on the combination of speedometer test-bed measurement and statistical analysis, the speed display error and its distributive regularity of given type passenger cars have been revealed. The research discovers that the error obey normal distribution, which parameters and are 38.553 0 km/h and 2.744 0 km2/h2 respectively, and establishes corresponding distributive models. Simulative calculating shows that the model calculating results are consistent with the sample measuring data, and the model simulative calculating error is only 0.68%. The research has a very important effect on understanding the statistical regularity of speed display error, pledging the vehicle traveling safety and improving speedometer design and manufacture.