Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology

This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (R on, sp ) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (R on, sp ) by shortening the current flow path and smooth the surface electric field. Meanwhile P-buried layer is introduced to assist depletion and enhance the charge density of drift region, which reduces R on, sp further and keep higher breakdown. The R on, sp of proposed USTI-LDMOS devices is very competitive, 18V LDMOS has BV DSS =27V and R on, sp =7.1 mΩ·mm2; 20V LDMOS has BV DSS =30V and R on, sp =8.8mΩ·mm2; 30V LDMOS has BV DSS =42V and R on, sp =14.5mΩ·mm2; 40V LDMOS has BV DSS =52V and R on, sp =20.5mΩ·mm2.