Back to Search
Start Over
Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology
- Source :
- 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD).
- Publication Year :
- 2017
- Publisher :
- IEEE, 2017.
-
Abstract
- This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (R on, sp ) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (R on, sp ) by shortening the current flow path and smooth the surface electric field. Meanwhile P-buried layer is introduced to assist depletion and enhance the charge density of drift region, which reduces R on, sp further and keep higher breakdown. The R on, sp of proposed USTI-LDMOS devices is very competitive, 18V LDMOS has BV DSS =27V and R on, sp =7.1 mΩ·mm2; 20V LDMOS has BV DSS =30V and R on, sp =8.8mΩ·mm2; 30V LDMOS has BV DSS =42V and R on, sp =14.5mΩ·mm2; 40V LDMOS has BV DSS =52V and R on, sp =20.5mΩ·mm2.
- Subjects :
- 010302 applied physics
LDMOS
Materials science
business.industry
020208 electrical & electronic engineering
Electrical engineering
02 engineering and technology
01 natural sciences
Shallow trench isolation
0103 physical sciences
Trench
0202 electrical engineering, electronic engineering, information engineering
Optoelectronics
business
Layer (electronics)
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)
- Accession number :
- edsair.doi...........8f997ee3cfe646ca7209160897b30432