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The power consumption of a mobile application processor (AP) is strongly limited by the SRAM minimum operating voltage, VMIN [1], since the 6T bit cell must balance between write-ability and bit cell stability. However, the SRAM VMIN scales down gradually with advanced process nodes due to increased variability. This is evident with the quantized device-width and limited process-knobs of a FinFET technology, which has greatly affected SRAM design [2–4]. Therefore, assist-circuits are more crucial in a FinFET technology to improve VMIN, which in turn adds to the Power, Performance, and Area (PPA) gain of SRAM.

The remarkable evolution of human society over the centuries has been driven by information. As information became digitalized thanks to silicon technologies, creating, sharing, and searching of data have become much easier. Most recently, scaled silicon technology has been at the core of this information revolution, as it forms the basis on which digital devices, such as computers, smartphones, and tablets, are built. As the feature size of silicon technology approaches sub-10nm, there are concerns that it cannot satisfy the demand for high performance devices through scaling any longer. However, through innovations in materials, structures, and processes, it will continue to provide higher-performance components to electronics systems for the coming decades. With performance-enhancing technologies, such as 3D ICs and Through-Silicon Vias (TSVs), and systems technologies on servers, clients, and interconnections, the data-driven world will continue to expand in the future.

In this paper, we present high threshold voltage, low on-resistance, and high speed GaN-HEMT devices using a p-GaN layer in the gate stack. There are three novel features - first, for the first time, p-GaN gate HEMTs were fabricated on a 200-mm GaN on Si substrate using a Au-free fully CMOS-compatible process. Second, good electrical characteristics, including a threshold voltage of higher than 2.8 V, a low gate leakage current, no hysteresis, and fast switching, were obtained by employing a p-GaN and W gate stack. Finally, TO-220 packaged p-GaN gate HEMT devices, which can sustain a gate bias of up to 20 V, were demonstrated. Such properties indicate that our p-GaN HEMT devices are compatible with the conventional gate drivers for Si power devices.

We present here on a switch device made of a nitridized-chalcogenide glass for application in nanoscale array circuits. Previously, AsTeGeSi-based switches have had key issues with performance degradation over time. This is usually due to changes in the Te concentration in the device active region [1–3]. However, our AsTeGeSiN switches were able to overcome this limitation as well as scale down to 30 nm with an on current of 100 μA (J > 1.1×107A/cm2). Their cycling performance was shown to be greater than 108. Also, we demonstrate a memory cell using a TaO x resistance memory with the AsTeGeSiN select device.

This paper summarizes the development processes of 50kW induction motor for electric vehicle. The main goal of the motor development was to produce the motor satisfying the provided design and performance requirements. In this paper, motor design and performance requirements will be presented and electromagnetic, thermal, mechanical design and analysis results will be also introduced. And finally performance characteristics of the manufactured motors will be checked from various test results.

Dimensional scaling will continue in Si CMOS technology which will extend to beyond 10nm. Key challenges for dimensional scaling and expansion of silicon-based technologies as well as research directions will be reviewed in traditional semiconductor applications such as DRAM, NAND Flash, logic as well as advanced devices including STT-MRAM, ReRAM and reconfigurable logic. Furthermore, other areas where Si technologies play import roles will be presented including power electronics, solid-state lighting as well as DNA sequencing and medical imaging.

In the near future, photonics will complement Si CMOS technologies in high performance emerging applications. This convergence has been possible thanks to the compatibility with Si processes, which will be beneficial to applications such as optical interconnect, lighting, display and medicine.

The convergence of electronics and photonics on silicon CMOS will allow an ultrawide bandwidth with reduced power consumption. Furthermore, this convergence will also be beneficial for emerging applications in energy and medical areas in a near future.

The integration of electronically active oxide transistors onto silicon circuits represents an innovative approach to improving the performance of devices. In this paper, we present high performance oxide transistor for use as gate drive circuitry integrated on top of a power electronic device, providing a novel power system. Specifically, as a core device component in gate driver, oxide transistor exhibits remarkable performance such as, high mobility (23∼47cm2/Vs) and high breakdown voltage (BV) of 60∼340V despite low process temperatures (

A p-GaN/AlGaN/GaN based normally-off HEMT device has been demonstrated on a Si substrate. Our p-GaN based device shows not only a high threshold voltage of 3 V but also low gate leakage current. Buffer and device breakdown voltages exceed 1600 V with 5.2 um GaN buffer thickness and specific on-state resistance is 2.9mΩ cm2. The calculated figure of merit is 921 MV2/Ωcm2, which is the highest value reported for the GaN E-mode devices.

Novel spin transfer torque MRAM cells with three dimensional freelayer structures were suggested for the high density memory below 20nm technology node. By folding the freelayer to a special geometry, the 3D MTJ Cell structure retains large freelayer volume without an increase of cell foot-print, scaling down the MRAM cells even with in-plane magnetic anisotropy materials. From the micromagnetic calculation with Nudged Elastic Band (NEB) method, we confirmed the thermal stability over 60 in 3D MTJ cell with 15× 30nm2 area.

A highly reliable RRAM with multi-level cell (MLC) characteristics were fabricated using a triple-layer structure (base layer/oxygen exchange layer/barrier layer) for the storage class memory applications. A reproducible multi-level switching behaviour was successfully observed, and simulated by the modulated Schottky barrier model. Morevoer, a new programming algorithm was developed for more reliable and uniform MLC operation. As a result, more than 107 cycles of switching endurance and 10 years of data retention at 85°C for all the 2 bit/cell operation were archieved.

In this presentation, we report excellent electrical and optical characteristics of a dual gate photo thin film transistor (TFT) with bi-layer oxide channel, which was designed to provide virgin threshold voltage (V T ) control, improve the negative bias illumination temperature stress (NBITS) reliability, and offer high photoconductive gain. In order to address the photo-sensitivity of phototransistor for the incoming light, top transparent InZnO (IZO) gate was employed, which enables the independent gate control of dual gate photo-TFT without having any degradation of its photosensitivity. Considering optimum initial V T and NBITS reliability for the device operation, the top gate bias was judiciously chosen. In addition, the speed and noise performance of the photo-TFT is competitive with silicon photo-transistors, and more importantly, its superiority lies in optical transparency.

We successfully fabricated the highly sensitive and reliable X-ray flat panel detector with HgI 2 photoconductor and Oxide drive TFT. The HgI 2 was fabricated by screen printing of paste and various properties were tested. The HgI 2 has 3 times higher sensitivity than a-Se at the applied bias below 150V. Also it shows better stability under high accumulation dose and humidity. As a drive TFT, HfInZnO oxide TFT was used and it has lower leakage current and higher mobility than a-Si TFT indicating the improvement of signal-to-noise. These are very promising results for applications in large area X-ray flat panel detector with higher X-ray sensitivity and lower dose requirement for Mammography imaging.

A temperature-dependent mobility model in amorphous oxide semiconductor (AOS) thin film transistors (TFTs) extracted from measurements of source-drain terminal currents at different gate voltages and temperatures is presented. At low gate voltages, trap-limited conduction prevails for a broad range of temperatures, whereas variable range hopping becomes dominant at lower temperatures. At high gate voltages and for all temperatures, percolation conduction comes into the picture. In all cases, the temperature-dependent mobility model obeys a universal power law as a function of gate voltage.

This paper summarizes the landscape for semiconductor analysis. High-resolution imaging and microanalysis are discussed first because they are used in most of the core process technologies that enable device scaling beyond the current 30 nm technology node. Key technology for analysis of dopant distribution, contamination, and strain is reviewed from the viewpoints of sensitivity, spatial resolution, contamination level, and defect size. The final section describes microscopy based on in situ techniques, which can play an important role in developing extended complementary metal-oxide-semiconductor (CMOS) and beyond CMOS as well as play a role in understanding the fundamental physics of new and emerging semiconductor devices. Within each technology area, future directions that are being driven by new materials and processes are briefly outlined.

We measured Radio-Frequency (RF) performance of devices with graphene grown using low temperature Inductively-Coupled Plasma Chemical Vapor Deposition (ICP-CVD) method on 6-inch wafer for the first time. To remove the coupling of electrode in-plane, we introduced locally-embedded-back-gate using TiN metal. The symmetric structure of 2-gate fingers was adopted to reduce misalign issue during fabrication of the structure with underlap between Gate and Source/Drain, which was also adopted for the reduction of parasitic capacitance due to gate oxide with high dielectric constant. Cutoff frequency (ƒ T ) increase is moderately obtained with the decrease of gate length. Despite the low g m due to underlap region, we obtained ƒ T =80 GHz.

As silicon technology enters sub-20nm nodes, new materials, structures and processes are being introduced in order to continue with the advantages of dimensional scaling, e.g, 3D NAND, ReRAM, EUVL, etc. Beyond 10 nm, Si CMOS technology will remain as the mainstream. In this paper, key drivers for silicon-based nano-electronics as well as research directions will be reviewed from viewpoints of system, memory, logic and emerging Si technologies.

In the future, the world will undergo a big transition due to aging society, growing global competition, and energy & environmental problems. The most influential factor to the future will be the paradigm shift of science and technology.

In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, N t , with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance R sd effect. Due to the random distribution of traps in Si-NWFETs, the 1/f noise data are obtained by averaging the drain current power spectral density, S id , for several devices. By using the proposed 1/f model, the extracted volume trap density is compared for three different oxide processes (ISSG/RTO/GNOx) and verified by hot carrier stress test.

The rapid evolution of flash memory technologies in the previous decade has been achieved through the two distinctive ways; overcoming the scaling challenges and devising multi-bit cell transistors. The scaling challenges such as cell-to-cell interference, cell programming disturbance and patterning limit have been tackled with several breakthroughs; incorporating low-k material, relieving the stress on tunnel oxide and double patterning technology(DPT). Multi-bit cell transistors have multiplied the chip density up to 4 times with the new circuit technology and the controller algorithms. And now, the key technology in the sub-20nm technology region is finding how to integrate all the available solutions of process, device, circuit and controller issues with the most efficient ways. In the aspect of integrating each technology, we discuss technical scaling barrier in sub-20nm region and present the future candidate for high-density devices.

A nanoelectromechanical (NEM) switching device is developed with a new technique involving a liquid medium. Operation voltage is reduced by about 40% and the number of switching cycles with reliable device performance is improved dramatically, more than 5-fold. The device has a 50 nm thick TiN cantilever with a 40 nm air-gap. A CMOS compatible process is employed.

NAND memory cells scaled to 51–32 nm, when they receive stress due to program and erase cycles, not only reveal a gradual positive shift of a midgap voltage in a program state along the number of program and erase cycles but also possess inverse relationship between degradation of subthreshold swing values due to the cycling stress and their initial swing values. These properties were absent in the memory cells larger than 70 nm. A new reliability model is proposed based on non-uniform distribution of negative oxide charges which are generated much more near to floating gate edges than to the center due to the cycling stress. It is shown that the non-uniformly distributed charges hinder erase currents while leave program currents intact, leading to the positive midgap voltage shift in a program state. The dense oxide charges near the gate edges significantly influence source/drain junction potential, resulting in observed degradation of subthreshold swing values.

1D thickness scaling study on a-GST has been successfully demonstrated without the help of ultra-fine lithography. V th linearly scales down to ∼0.65 V at 6 nm scale, showing that stable read operation is possible at elevated temperature (70 °C). Reset R drift shows no dependency on the a-GST thickness up to 6 nm regime. Thin a-GST shows enhanced thermal stability compared to thick a-GST.

Fine patterning technologies - E-beam lithography, SPT (Spacer Patterning Technology) and SaDPT (Self aligned Double Patterning Technology)-have been introduced to develop a single unit of nano-scale MOSFET. However, in order to achieve manufacturable high density NAND Flash memories, the merits and demerits of each technology should be considered in three points of view: device characteristics, process controllability and mass production. In this paper, we suggest the appropriate technology for particular cell types, CTF(Charge Trap Flash) cell, floating poly-Si gate cell, and for process steps such as active, gate and bit-line.

Differential signaling is effective in suppressing common-mode noise in parallel links as well as in high-speed serial links. However, differential signaling is not cost effective for DRAM interfaces because the I/O-pin count is a significant portion of the chip cost. Since differential signaling requires 2n pins and channels to transmit n bits of data, the data rate must be doubled compared to single-ended signaling to accomplish the same per-pin data rate. However, ISI due to channel-bandwidth limits and technology limits degrade the performance [1]. Although single-ended signaling achieves a higher data rate per pin, two major problems limit increases of the data rate: reference ambiguity and power-supply fluctuation [2]. Several works are reported to solve the problems of single-ended signaling [3–7]. However, the skew between encoder outputs in [3] and receiver outputs in [4,5] degrades the performance of transceivers and the signaling in [6,7] keeps the reference signal. We describe pseudo-differential signaling schemes for DRAM interfaces that minimize the skew between data and suppress common-mode noise. The chip is implemented in a 0.13µm process and occupies 2.7×2.3mm2 and the active area is 1.0×0.3mm2.

As the workload and speed of a computer system increase, both the data bandwidth and capacity of main memory inevitably need to grow. However, the number of slots per channel is limited to maintain high bandwidth, making the capacity requirement difficult to meet. Another problem is that computer systems impose a limit on the supply of power since their power dissipation increases rapidly, where main memories account for roughly 15% of total power consumption. To address these issues, we design a 4Gb DDR3 SDRAM that supports a 1.2V supply voltage and 1.6Gb/s data rate.

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18mum CMOS process and operates at 5-Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The p-p jitter of output data is 52.82-ps.

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5-Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The p-p jitter of output data is 52.82-ps.

Future memory technologies are assessed in views of challenges and opportunities. The challenges which future memory confronts with are not just from technical challenges, but from techno-economical issues which become much critical. In this study, two most important memories: DRAM and NAND flash will be discussed in respects of challenges and opportunities and PRAM will be discussed as one of the important new emerging non-volatile random access memories (RAM).

One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.

Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding. This work tackles challenges in GDDR5 such as clock jitter and signal integrity.

As multi-core processors become mainstream, the demand for high-density cache memories has increased. Conventional 6T-cell-based SRAMs do not provide enough density for this trend, although they do have the desirable feature of high-speed access. To overcome the density limitation, an SRAM using a double- stacked S3 (stacked single-crystal Si) SRAM cell was introduced for mobile applications. This work demonstrates a high-speed SRAM using double-stacked-cell. From the process point of view, our design uses fully proven technologies for mass production at the sacrifice of cell size.From a circuit-design perspective, three schemes are introduced. They are automatic cell bias (ACB) for managing the current of SRAM cell transistors by controlling cell bias, adaptive block redundancy (ABR) for dealing with various defects from the new cell technology, and wordline pulse-width regulation (WPR) for adjusting wordline pulse-width according to cycle time.

Highly cost effective and high speed 72M bit density S3 SRAM technology was successfully achieved for standalone memory and embedded memory with selective epitaxial growth of Si films, low thermal SSTFT process , periphery only Co salicidation, and W shunt wordline scheme.

A 1.4 μm-pitch pixel of CMOS image sensor, which is the smallest to date, has been successfully developed and integrated into 8M density for the first time. To overcome the crucial degradation of the saturation charge and sensitivity, a novel photodiode structure extended under transfer gate and an elaborate optical design including very thin tungsten pixel routing with 65 nm-grade design rules are introduced, which result in enhanced electrical and optical performance.

A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100% BL cell-to-cell and almost 50% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge2Sb2Te5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO2 /SiN/Al2O3/TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30 nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8 Gb density in which all the technologies aforementioned are combined.

In order to realize a cost-effective high density FRAM product over 64-Mb, it is inevitable to develop technologies for a small cell and large wafer size without degradation during full integration. We have successfully demonstrated a fully functional 0.16 mum2 capacitor size, 64-Mb, 1T1C FRAM on an 8-inch wafer by introducing new integration technologies at 150 nm technology node. One of the key technologies is the use of novel capping layer, i.e. Al2O3, which prevents the capacitor from the degradation caused by following integration process. It was found that novel capping Al2O3 layer was very effective to block chronic hydrogen diffusion, and depending on the wafer size, the effective capping layer condition is changed. By introducing a novel capping layer of Al2O3 and optimizing its process conditions, the fully integrated ferroelectric capacitor for the 150 nm, 64-Mb, 1T1C FRAM on the 8-inch Si-substrate shows good ferroelectric properties such as a polarization value of 33 muC/cm2 with an uniform distribution of sigma = 1.27, and the sensing window of 300 mV at 85degC.

We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (metal-insulator-metal) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise (1) etching technology to have less plasma damage; (2) stack technology for the preparation of robust ferroelectrics; (3) capping technology to encapsulate cell capacitors; and (4) vertical conjunction technology to connect cell capacitors to the plate-line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but to ensure sensing margin of 300 mV in opposite-state retention even after 1000 hours at 150degC.

It was found that the charge loss behavior of TANOS (TaN-Al2O3-nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the gate structures for the first time. The gate structures with trap layers remained on source and drain regions showed increased charge loss compared to the one with trap layers separated between different gate lines. The improvement by removing the trap layers between gate lines suggests that the lateral charge spreading via trap layers from the programmed cells to the adjacent erased cells contributes to the charge loss of the TANOS cells.

A 512Mb diode-switch PRAM is developed in a 90nm CMOS technology. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described. Through these schemes, the PRAM achieves read throughput of 266MB/S and maximum write throughput of 4.64MB/S with a 1.8V supply.

Phase-change Random Access Memory (PRAM) has drawn much attention as a promising candidate for the next generation nonvolatile memory. This is because PRAM has a great potential not only to provide adequate solutions for solving the scaling issues that other conventional nonvolatile memories might face in near future, but also to create new functions and applications of its own with its fast write programming speed and direct overwrite capability. As a result, PRAM has been the fastest evolutionary memory and it is close to commercialization. In this paper, recent progresses in PRAM technologies will be discussed and future direction will be proposed.

A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.

Memory technologies for sub-40 nm will be reviewed, especially for DRAM and NAND Flash. First, technical challenges to be overcome in sub-40 nm node will be addressed, especially patterning and device's aspects. Then, possible solutions and directions will be discussed in detail. It is expected that memory technology scaling will be continued at least down to 30 nm node and beyond by developing novel structures and aggressively adopting new materials.

Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera (DSC) application

Fully functional 512Mb PRAM with 0.047mum2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC